DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/26/2024, 05/27/2025, 06/04/2025, 09/25/2025, and 01/09/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because Fig. 2 the labels for the gate lines the data lines and the voltages are poor quality and hard to read. Fig. 4 the labels for each of the signals is also poor quality and hard to read along with the lettering on the signals themselves at the top of the figure. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2 and 14-16 are rejected under 35 U.S.C. 102 as being anticipated by Cho et al. ( US 11,804181 B2; hereinafter Cho )
Regarding claim 1, Cho teaches a display substrate ( Fig. 6 SUB), comprising: a base substrate ( Fig. 6 SUB ), a plurality of data lines ( Fig. 9 DL1-DLm ) and sub-pixels ( Fig. 3 subpixels SP ) on the base substrate ( Fig. 3 SUB ); wherein the sub-pixel comprises a sub-pixel driving circuit ( Fig. 3 shows driving circuit ) and a light-emitting element ( Fig. 3 ED ); the sub-pixel driving circuit comprises a driving transistor ( Fig. 3 DRT ) and a data writing transistor ( Fig. 3 SCT ), and the light-emitting element comprises a first electrode ( Fig. 6 anode electrode AE ); a second electrode of the driving transistor ( Fig. 6 first source-drain electrode pattern SD1 ) is coupled to the corresponding first electrode ( Fig. 6 AE ) through a first connection structure ( Fig. 6 SD2 ); a first electrode of the data writing transistor ( Fig. 3 SCT ) is coupled to the corresponding data line through a second connection structure ( Col. 12 lines 42–45 The scan transistor SCT may be turned on and off by a scan signal SCAN that is a gate signal applied through a gate line GL and be electrically connected between the first node N1 of the driving transistor DRT and a data line DL ) ; the first connection structure ( Fig. 6 SD2 ) and the second connection structure ( as discussed above ) are in a non-aperture region of the sub-pixel ( They are below the PLN2 layer as shown in Fig. 6 ); and an orthographic projection of the first connection structure onto the base substrate and an orthographic projection of the second connection structure onto the base substrate are arranged along a first direction ( as shown in Fig. 6 ); the orthographic projection of the second connection structure onto the base substrate ( As shown in Fig. 3 the control circuit is connected to a 2D array ) and an aperture region of the sub-pixel are arranged along a second direction ( as shown in Fig. 3 the sub-pixels are arranged in a 2D array ), and the second direction intersects the first direction ( the directions are intersecting as shown the array of in Fig. 3 ).
Regarding claim 2, Cho teaches the display substrate according to claim 1 ( as discussed above ), wherein the first connection structure ( Fig. 6 area containing SD2 and SD1) comprises: a second conductive connection portion ( Col 21 lines 6-7 A second source-drain electrode pattern SD2 may be disposed on the first planarization layer PLn1 ), a first via-hole structure ( Col. 21 lines 7-12 The second source-drain electrode pattern SD2 may be connected to one of the two first source-drain electrode patterns SD1 through a contact hole formed in the first planarization layer PLN1 ), a fifth conductive connection portion ( Fig. 6 SD1 ) and a second via-hole structure ( bottom portion of Fig. 6 SD1 that passes through ILD2 ); the second conductive connection portion ( as described above) is coupled to the second electrode of the driving transistor ( as shown in Fig. 6 ), the second conductive connection portion is coupled to the fifth conductive connection portion ( Fig. 6 SD1) through the first via-hole structure ( as discussed above), and the fifth conductive connection portion ( Fig. 6 SD1 ) is coupled to the corresponding first electrode through the second via-hole structure ( as described above ).
Regarding claim 14, Cho teaches the display substrate according to claim 1 ( as discussed above), wherein the display substrate ( Fig. 6 ) further comprises: a plurality of light-emitting control lines ( Col. 9 lines 3 – 7 The display controller #240 can supply a data driving control signal DCS to the data driving circuit #220 ) , power lines ( Col. 28 lines 23-31 a plurality of power lines VL21 to VL2n ), an initialization signal line ( Col. 28 lines 23 – 31 the plurality of first initialization voltage lines VL11 to VL1n ), a reference signal line ( Col. 15 lines 52 – 60 include the reference voltage lines ), a plurality of first scan lines ( Fig. 10: SCAN1 signal GL1 ), a plurality of second scan lines ( Fig. 10: SCAN2 signal GL2 ), a plurality of third scan lines ( Fig. 10: SCAN3 signal GL3 ) and a plurality of partition control lines ( Fig. 2: gate control signal GCS ); the sub-pixel driving circuit further comprises: a compensation transistor ( Fig. 10: conductive layer BSM), a reset transistor ( Fig. 10: T5 ), the light-emitting control transistor ( Fig. 10: T2 ), a writing control transistor ( Fig. 10: T_com ) and a storage capacitor ( Fig. 10: Cstg ); a gate electrode of the data writing transistor ( Fig. 10: DRT ) is coupled to the corresponding first scan line ( as shown in Fig. 10 ) , and a second electrode of the data writing transistor ( Fig. 10: DRT ) is coupled to a first electrode of the writing control transistor ( as shown in Fig. 10 ); a second electrode of the writing control transistor ( Fig. 10: T1 ) is coupled to a gate electrode of the driving transistor ( Fig. 10: DRT ), and a gate electrode of the writing control transistor ( Fig. 10: T1 ) is coupled to the corresponding partition control line ( Fig. 10: GL1 ); a gate electrode of the compensation transistor ( Fig. 10: BSM ) is coupled to the corresponding second scan line ( Fig. 10: SCAN2 ), a first electrode of the compensation transistor ( Fig. 10: BSM ) is coupled to the reference signal line ( Fig. 10 VLd ), and a second electrode of the compensation transistor ( Fig. 10: BSM ) is coupled to the first electrode of the writing control transistor ( Fig. 10: T1 ); a gate electrode of the reset transistor ( Fig. 10: T5 ) is coupled to the corresponding third scan line ( Fig. 10: SCAN3 ), a first electrode of the reset transistor ( Fig. 10: T5 ) is coupled to the initialization signal line ( Fig. 10: Dvini ), and a second electrode of the reset transistor ( Fig. 10: T5 ) is coupled to the second electrode of the driving transistor ( Fig. 10: N3 ); a gate electrode of the light-emitting control transistor ( Fig. 10: T2 ) is coupled to the corresponding light- emitting control line ( as shown in Fig. 10 ), the first electrode of the light-emitting control transistor ( Fig. 10: T2 ) is coupled to the power line ( Fig. 10: Vdata ), and the second electrode of the light-emitting control transistor ( Fig. 10: T2 ) is coupled to the first electrode of the driving transistor ( Fig. 10 DRT ); a first electrode plate of the storage capacitor ( Fig. 10: Cstg ) is coupled to the gate electrode of the driving transistor ( Fig. 10: N1 ), and a second electrode plate of the storage capacitor ( Fig. 10 Cstg ) is coupled to the second electrode of the driving transistor ( as shown in Fig. 10 ).
Regarding claim 15, Cho teaches a display device ( Fig. 2 display device #100 ), comprising a display substrate ( Fig. 2 SUB ); wherein the display substrate comprises: a base substrate ( Fig. 6 SUB ) , a plurality of data lines ( Fig. 9 DL1-DLm ) and sub-pixels ( Fig. 3 subpixels SP ) on the base substrate ( Fig. 3 SUB ); wherein the sub-pixel comprises a sub-pixel driving circuit ( Fig. 3 shows driving circuit ) and a light-emitting element ( Fig. 3 ED ); the sub-pixel driving circuit comprises a driving transistor ( Fig. 3 DRT ) and a data writing transistor ( Fig. 3 SCT ), and the light-emitting element comprises a first electrode ( Fig. 6 anode electrode AE ); a second electrode of the driving transistor ( Fig. 6 first source-drain electrode pattern SD1 ) is coupled to the corresponding first electrode ( Fig. 6 AE ) through a first connection structure ( Fig. 6 SD2 ); a first electrode of the data writing transistor ( Fig. 3 SCT ) is coupled to the corresponding data line through a second connection structure ( Col. 12 lines 42–45 The scan transistor SCT may be turned on and off by a scan signal SCAN that is a gate signal applied through a gate line GL and be electrically connected between the first node N1 of the driving transistor DRT and a data line DL ) ; the first connection structure ( Fig. 6 SD2 ) and the second connection structure ( as discussed above ) are in a non-aperture region of the sub-pixel ( They are below the PLN2 layer as shown in Fig. 6 ); and an orthographic projection of the first connection structure onto the base substrate and an orthographic projection of the second connection structure onto the base substrate are arranged along a first direction ( as shown in Fig. 6 ); the orthographic projection of the second connection structure onto the base substrate ( As shown in Fig. 3 the control circuit is connected to a 2D array ) and an aperture region of the sub-pixel are arranged along a second direction ( as shown in Fig. 3 the sub-pixels are arranged in a 2D array ), and the second direction intersects the first direction ( the directions are intersecting as shown the array of in Fig. 3 ).
Regarding claim 16, Cho teaches the display device according to claim 15 ( as discussed above ), wherein the first connection structure ( Fig. 6 area containing SD2 and SD1) comprises: a second conductive connection portion ( Col 21 lines 6-7 A second source-drain electrode pattern SD2 may be disposed on the first planarization layer PLn1 ), a first via-hole structure ( Col. 21 lines 7-12 The second source-drain electrode pattern SD2 may be connected to one of the two first source-drain electrode patterns SD1 through a contact hole formed in the first planarization layer PLN1 ), a fifth conductive connection portion ( Fig. 6 SD1 ) and a second via-hole structure ( bottom portion of Fig. 6 SD1 that passes through ILD2 ); the second conductive connection portion ( as described above ) is coupled to the second electrode of the driving transistor ( as shown in Fig. 6 ), the second conductive connection portion is coupled to the fifth conductive connection portion ( Fig. 6 SD1 ) through the first via-hole structure ( as discussed above ), and the fifth conductive connection portion ( Fig. 6 SD1 ) is coupled to the corresponding first electrode through the second via-hole structure ( as described above ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-11, 13, and 17-20 are rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 11,804,181 B2; 09/2022 in view of Son et al.; US 2022/0246086 A1; 09/2021
Claim 3: Cho discloses the display substrate according to claim 2 (as discussed above ).
Cho does not appear to disclose the second connection structure comprises: a fourth conductive connection portion and a third via-hole structure; the fourth conductive connection portion is coupled to the first electrode of the data writing transistor, and the fourth conductive connection portion is coupled to the corresponding data line through the third via-hole structure.
However, Son teaches the second connection structure ( Fig. 11: CRE1(T1) structure ) comprises: a fourth conductive connection portion ( Fig. 11: CRE1(T1) DE) and a third via-hole structure ( Fig. 11 CRE1(T1) bottom portion of DE ); the fourth conductive connection portion ( as discussed above) is coupled to the first electrode of the data writing transistor ( [0177] the first transistor T1 of each stage ST as an example of the first circuit element CRE1 ), and the fourth conductive connection portion is coupled to the corresponding data line through the third via- hole structure ( [0166] The conductive pattern CDP may also overlap a portion of the first clock line CL1 connected to the first circuit element CRE1; [0168] the conductive pattern CDP may also overlap a portion of the at least one signal line and/or power source line ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Cho to implement the second connection structure comprises: a fourth conductive connection portion and a third via-hole structure; the fourth conductive connection portion is coupled to the first electrode of the data writing transistor, and the fourth conductive connection portion is coupled to the corresponding data line through the third via- hole structure because this configuration is used to create a vertical electrical pathway in a multi-layered display panel.
Claim 4: Cho and Son disclose the display substrate according to claim 3 ( as discussed above ).
Cho does not appear to disclose the display substrate further comprises a first organic layer and a second organic layer sequentially stacked in a direction away from the base substrate, the first via-hole structure is defined through the first organic layer, and the second via-hole structure is defined through the second organic layer; the second conductive connection portion is between the first organic layer and the base substrate, and the fifth conductive connection portion is between the first organic layer and the second organic layer.
However, Son discloses the display substrate further comprises a first organic layer ( Fig. 11: INS4 ) and a second organic layer ( Fig. 11: INS5 ) sequentially stacked in a direction away from the base substrate ( Fig. 11: BSL ), the first via-hole structure is defined through the first organic layer ( as shown in Fig. 11 ), and the second via-hole structure is defined through the second organic layer ( as shown in Fig. 11 ); the second conductive connection portion ( Fig. 11: SE ) is between the first organic layer ( Fig. 11: INS4 ) and the base substrate ( Fig. 11: BSL ), and the fifth conductive connection portion ( Fig. 11: CH1 ) is between the first organic layer ( Fig. 11: INS4 ) and the second organic layer ( Fig. 11: INS5 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Cho to implement the display substrate further comprises a first organic layer and a second organic layer sequentially stacked in a direction away from the base substrate, the first via-hole structure is defined through the first organic layer, and the second via-hole structure is defined through the second organic layer; the second conductive connection portion is between the first organic layer and the base substrate, and the fifth conductive connection portion is between the first organic layer and the second organic layer because this approach is used for maximizing device density, optimizing signal routing, and improving signal integrity.
Claim 5: Cho and Son disclose the display substrate according to claim 4 ( as discussed above ).
Cho does not appear to disclose the third via-hole structure is defined through the first organic layer; and the fourth conductive connection portion is between the first organic layer and the base substrate.
However, Son teaches the third via-hole structure ( Fig. 11 ) is defined through the first organic layer ( Fig. 11: INS4 ); and the fourth conductive connection portion ( Fig. 11: CRE1(T1) DE)) is between the first organic layer ( Fig. 11: INS4 ) and the base substrate ( Fig. 11 BSL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Cho to implement the third via-hole structure is defined through the first organic layer; and the fourth conductive connection portion is between the first organic layer and the base substrate because this optimizes signal routing and enables complex circuit designs.
Claim 6: Cho and Son disclose the display substrate according to claim 5 ( as discussed above ).
Cho teaches the display substrate further comprises: a first passivation layer ( Fig. 6: passivation layer PAS0 ) and a second passivation layer ( Fig. 6: passivation layer PAS1 ); the first passivation layer ( Fig. 6: PAS0 ) is between the first organic layer ( Fig. 6: PLN1 ) and the second passivation layer ( Fig. 6: PAS1 ), the second passivation layer ( Fig. 6: PAS1 ) is between the first passivation layer ( Fig. 6: PAS0 ) and the second organic layer ( Fig. 6 PCL ); the first via-hole structure ( Col. 21 lines 7-12 The second source-drain electrode pattern SD2 may be connected to one of the two first source-drain electrode patterns SD1 through a contact hole formed in the first planarization layer PLN1 ) and the third via-hole structure are both defined through the first passivation layer ( Fig. 6: PAS0 ), and the second via-hole structure ( bottom portion of Fig. 6 SD1 that passes through ILD2 ) is defined through the second passivation layer ( Fig. 6 PAS1 ); the fifth conductive connection portion ( Fig. 6 SD1 ) is between the first passivation layer ( Fig. 6 PAS0 ) and the second passivation layer ( Fig. 6 PAS1 ).
Claim 7: Cho and Son disclose the display substrate according to claim 1 ( as discussed above ).
Cho does not appear to disclose the display substrate further comprises: an auxiliary electrode, a third connection structure, and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure; the third connection structure is in the non-aperture region of the sub-pixel; and an orthographic projection of the third connection structure onto the base substrate and the orthographic projection of the first connection structure onto the base substrate are arranged along the first direction.
However, Son teaches the display substrate further comprises: an auxiliary electrode ( Fig. 11: conductive pattern CDP ), a third connection structure ( Fig. 11: area that includes CDP and PL2 in the center section ), and a second electrode layer ( Fig. 11: ELT2 and PL2 in the PXG2 (PXL1) area ); the auxiliary electrode is coupled to the second electrode layer through the third connection structure ( [0175] the conductive pattern CDP may extend toward at least one adjacent pixel PXL, and may be integrally connected to one electrode of the at least one adjacent pixel PXL ); the third connection structure is in the non-aperture region of the sub-pixel ( as shown in Fig. 11 ); and an orthographic projection of the third connection structure onto the base substrate and the orthographic projection of the first connection structure onto the base substrate are arranged along the first direction ( as shown in Fig. 11 the first and third structures are distributed along the first direction ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Cho to implement the display substrate further comprises: an auxiliary electrode, a third connection structure, and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure; the third connection structure is in the non-aperture region of the sub-pixel; and an orthographic projection of the third connection structure onto the base substrate and the orthographic projection of the first connection structure onto the base substrate are arranged along the first direction because this improves the aperture ratio and enhances signal transmission.
Claim 8: Cho and Son disclose the display substrate according to claim 1 ( as discussed above ).
Cho does not appear to disclose the display substrate further comprises: an auxiliary electrode, a third connection structure, and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure; the third connection structure is in the non-aperture region of the sub-pixel; and an orthographic projection of the third connection structure onto the base substrate is at least partly staggered from the orthographic projection of the first connection structure onto the base substrate.
However, Son teaches the display substrate further comprises: an auxiliary electrode ( Fig. 11: conductive pattern CDP ), a third connection structure ( Fig. 11: area that includes CDP and PL2 in the center section ), and a second electrode layer ( Fig. 11: ELT2 and PL2 in the PXG2 (PXL1) area ); the auxiliary electrode is coupled to the second electrode layer through the third connection structure ( [0175] the conductive pattern CDP may extend toward at least one adjacent pixel PXL, and may be integrally connected to one electrode of the at least one adjacent pixel PXL ); the third connection structure is in the non-aperture region of the sub-pixel ( as shown in Fig. 11 ); and an orthographic projection of the third connection structure onto the base substrate is at least partly staggered from the orthographic projection of the first connection structure onto the base substrate ( as shown in Fig. 11 the third connection structure and the first connection structure are not vertically aligned ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Cho to implement the display substrate further comprises: an auxiliary electrode, a third connection structure, and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure; the third connection structure is in the non-aperture region of the sub-pixel; and an orthographic projection of the third connection structure onto the base substrate is at least partly staggered from the orthographic projection of the first connection structure onto the base substrate because this optimizes the display’s aperture ratio while ensuring reliable electrical coupling and a uniform electric field.
Claim 9: Cho and Son disclose the display substrate according to claim 7 ( as discussed above ).
Cho does not appear to disclose the display substrate further comprises a second organic layer and a pixel definition layer sequentially stacked in a direction away from the base substrate; the third connection structure comprises: a fourth via-hole structure, a connecting pattern and a fifth via-hole structure; the auxiliary electrode is between the second organic layer and the base substrate; at least a portion of the second electrode layer is at a side of the pixel definition layer facing away from the base substrate; at least a portion of the connecting pattern is between the second organic layer and the pixel definition layer; the fourth via-hole structure is defined through the second organic layer, and the fifth via-hole structure is defined through the pixel definition layer; the connecting pattern is coupled to the auxiliary electrode through the fourth via-hole structure, and the connecting pattern is coupled to the second electrode layer through the fifth via- hole structure.
However, Son discloses the display substrate further comprises a second organic layer ( Fig. 11: INS5 ) and a pixel definition layer ( Fig. 11 DPL ) sequentially stacked in a direction away ( as shown in Fig. 11 ) from the base substrate ( Fig. 11: BSL ); the third connection structure ( Fig. 11: area that includes CDP and PL2 in the center section ) comprises: a fourth via-hole structure, a connecting pattern and a fifth via-hole structure ( [0175] the conductive pattern CDP may be connected to the second power source line PL2 through the second contact hole CH2 formed in the first PXL1 of the second pixel group PXG2 without forming a contact hole for connecting the conductive pattern CDP to the second power source line PL2 ); the auxiliary electrode ( Fig. 11: CDP ) is between the second organic layer ( Fig. 11: INS5 ) and the base substrate ( Fig. 11: BSL ); at least a portion of the second electrode layer ( Fig. 11: ELT2 and PL2 in the PXG2 (PXL1) area ) is at a side of the pixel definition layer facing away from the base substrate ( Fig. 11: BSL) ; at least a portion of the connecting pattern ( Fig. 11 flat portion of the CDP) is between the second organic layer ( Fig. 11: INS5 ) and the pixel definition layer ( Fig. 11: DPL ); the fourth via-hole structure ( [0175] the conductive pattern CDP may be connected to the second power source line PL2 through the second contact hole CH2 formed in the first PXL1 of the second pixel group PXG2 without forming a contact hole for connecting the conductive pattern CDP to the second power source line PL2 ) is defined through the second organic layer ( Fig. 11: INS5 ), and the fifth via-hole structure is defined through the pixel definition layer ( Fig. 11; DPL ); the connecting pattern is coupled to the auxiliary electrode through the fourth via-hole structure ( as discussed above ), and the connecting pattern is coupled to the second electrode layer through the fifth via- hole structure ( [0175] the conductive pattern CDP may extend toward at least one adjacent pixel PXL, and may be integrally connected to one electrode of the at least one adjacent pixel PXL ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Cho to implement the display substrate further comprises a second organic layer and a pixel definition layer sequentially stacked in a direction away from the base substrate; the third connection structure comprises: a fourth via-hole structure, a connecting pattern and a fifth via-hole structure; the auxiliary electrode is between the second organic layer and the base substrate; at least a portion of the second electrode layer is at a side of the pixel definition layer facing away from the base substrate; at least a portion of the connecting pattern is between the second organic layer and the pixel definition layer; the fourth via-hole structure is defined through the second organic layer, and the fifth via-hole structure is defined through the pixel definition layer; the connecting pattern is coupled to the auxiliary electrode through the fourth via-hole structure, and the connecting pattern is coupled to the second electrode layer through the fifth via- hole structure because this improves the conductivity and thermal management of the device.
Claim 10: Cho and Son disclose the display substrate according to claim 9 ( as discussed above).
Cho teaches the plurality of sub-pixels ( as shown in Fig. 4 ) are divided into an array of repeating units ( Fig. 4 OA1 and OA2 ), each repeating unit comprises two sub-units arranged along the first direction ( Fig. 4 OA1 and OA2 ), and each sub-unit comprises the plurality of sub-pixels arranged along the first direction ( Fig. 4L EA of Red SP, EA of Green SP, and EA of Blue SP are arranged in each of the sub-units ); the orthographic projection of the auxiliary electrode onto the base substrate is located between orthographic projections of the two sub-units onto the base substrate ( as shown in Fig. 6 ).
Claim 11: Cho and Son disclose the display substrate according to claim 10 ( as discussed above ).
Cho teaches the display substrate further comprises a power line ( Fig. 9 plurality of power lines VL21 to VL 2n ) and a power compensation line ( Fig. 10 pixel driving power line VLd ); the sub-pixel driving circuit further comprises a light-emitting control transistor ( Fig. 10: T3 ); a first electrode of the light-emitting control transistor ( Fig. 10: T3 ) is coupled to the power compensation line ( Fig. 10: VLd ), and a second electrode of the light-emitting control transistor ( Fig. 10: T3 ) is coupled to a first electrode of the driving transistor ( Fig. 10 a driving transistor DRT ); the power compensation line ( Fig. 10: VLd ) is coupled to the power line ( Fig. 10: ELVDD ) through a sixth via-hole structure ( Col. 30 lines 50 – 55 When the third transistor T3 is turned on by the emission signal EMS, the pixel driving power line VLd supplying the pixel driving voltage ELVDD and the second node N2 can be connected ), and the sixth via-hole structure is in the non-aperture region of the sub-pixel ( as shown in Fig. 2 the control structures are outside the active region of the display ).
Claim 13: Cho and Son disclose the display substrate according to claim 11 ( as discussed above).
Cho teaches orthographic projections of the power lines ( Fig. 5A: VL1 and Fig. 5B: VL2 ) onto the base substrate ( Fig. 6: SUB1 ) and orthographic projections of the repeating units ( Fig. 5A: OA1 and Fig. 5B: OA2 ) onto the base substrate ( Fig. 6: SUB1 ) are alternately arranged along the first direction (as shown in Figs. 5A and 5B ).
Claim 17: Cho discloses the display device according to claim 16 ( as discussed above).
Cho does not appear to disclose the second connection structure comprises: a fourth conductive connection portion and a third via-hole structure; the fourth conductive connection portion is coupled to the first electrode of the data writing transistor, and the fourth conductive connection portion is coupled to the corresponding data line through the third via- hole structure.
However, Son teaches the second connection structure ( Fig. 11: CRE1(T1) structure ) comprises: a fourth conductive connection portion ( Fig. 11: CRE1(T1) DE) and a third via-hole structure ( Fig. 11 CRE1(T1) bottom portion of DE ); the fourth conductive connection portion ( as discussed above) is coupled to the first electrode of the data writing transistor ( [0177] the first transistor T1 of each stage ST as an example of the first circuit element CRE1 ), and the fourth conductive connection portion is coupled to the corresponding data line through the third via- hole structure ( [0166] The conductive pattern CDP may also overlap a portion of the first clock line CL1 connected to the first circuit element CRE1; [0168] the conductive pattern CDP may also overlap a portion of the at least one signal line and/or power source line ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Cho to implement the second connection structure comprises: a fourth conductive connection portion and a third via-hole structure; the fourth conductive connection portion is coupled to the first electrode of the data writing transistor, and the fourth conductive connection portion is coupled to the corresponding data line through the third via- hole structure because this creates a compact, reliable vertical electrical connection between different conductive layers of the display panel.
Claim 18: Cho and Son disclose the display device according to claim 17 ( as discussed above).
Cho does not appear to disclose the display substrate further comprises a first organic layer and a second organic layer sequentially stacked in a direction away from the base substrate, the first via-hole structure is defined through the first organic layer, and the second via-hole structure is defined through the second organic layer; the second conductive connection portion is between the first organic layer and the base substrate, and the fifth conductive connection portion is between the first organic layer and the second organic layer.
However, Son discloses the display substrate further comprises a first organic layer ( Fig. 11: INS4 ) and a second organic layer ( Fig. 11: INS5 ) sequentially stacked in a direction away from the base substrate ( Fig. 11: BSL ), the first via-hole structure is defined through the first organic layer ( as shown in Fig. 11 ), and the second via-hole structure is defined through the second organic layer ( as shown in Fig. 11 ); the second conductive connection portion ( Fig. 11: SE ) is between the first organic layer ( Fig. 11: INS4 ) and the base substrate ( Fig. 11: BSL ), and the fifth conductive connection portion ( Fig. 11: CH1 ) is between the first organic layer ( Fig. 11: INS4 ) and the second organic layer ( Fig. 11: INS5 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Cho to implement the display substrate further comprises a first organic layer and a second organic layer sequentially stacked in a direction away from the base substrate, the first via-hole structure is defined through the first organic layer, and the second via-hole structure is defined through the second organic layer; the second conductive connection portion is between the first organic layer and the base substrate, and the fifth conductive connection portion is between the first organic layer and the second organic layer because this achieves complex, high-density electrical routing, providing electrical isolation between different conductive layers.
Claim 19: Cho and Son disclose the display device according to claim 18 ( as discussed above ).
Cho does not appear to disclose the third via-hole structure is defined through the first organic layer; and the fourth conductive connection portion is between the first organic layer and the base substrate.
However, Son teaches the third via-hole structure ( Fig. 11 ) is defined through the first organic layer ( Fig. 11: INS4 ); and the fourth conductive connection portion ( Fig. 11: CRE1(T1) DE)) is between the first organic layer ( Fig. 11: INS4 ) and the base substrate ( Fig. 11 BSL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Cho to implement the third via-hole structure is defined through the first organic layer; and the fourth conductive connection portion is between the first organic layer and the base substrate because this will optimize signal routing and maximize the available surface area for components.
Claim 20: Cho and Son disclose the display device according to claim 19 ( as discussed above ).
Cho teaches the display substrate further comprises: a first passivation layer ( Fig. 6: passivation layer PAS0 ) and a second passivation layer ( Fig. 6: passivation layer PAS1 ); the first passivation layer ( Fig. 6: PAS0 ) is between the first organic layer ( Fig. 6: PLN1 ) and the second passivation layer ( Fig. 6: PAS1 ), the second passivation layer ( Fig. 6: PAS1 ) is between the first passivation layer ( Fig. 6: PAS0 ) and the second organic layer ( Fig. 6 PCL ); the first via-hole structure ( Col. 21 lines 7-12 The second source-drain electrode pattern SD2 may be connected to one of the two first source-drain electrode patterns SD1 through a contact hole formed in the first planarization layer PLN1 ) and the third via-hole structure are both defined through the first passivation layer ( Fig. 6: PAS0 ), and the second via-hole structure ( bottom portion of Fig. 6 SD1 that passes through ILD2 ) is defined through the second passivation layer ( Fig. 6 PAS1 ); the fifth conductive connection portion ( Fig. 6 SD1 ) is between the first passivation layer ( Fig. 6 PAS0 ) and the second passivation layer ( Fig. 6 PAS1 ).
Claim 12 is rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 11,804,181 B2; 09/2022 in view of Son et al.; US 2022/0246086 A1; 09/2021 as it relates to claim 11 and further in view of Lee et al.; US 2022/0165217 A1; 09/2021
Claim 12: Cho and Son disclose the display substrate according to claim 11 ( as discussed above).
Neither Cho nor Son appear to disclose the display substrate further comprises a first organic layer, the power compensation line is between the first organic layer and the base substrate, the power line is on a side of the first organic layer facing away from the base substrate, and the sixth via-hole structure is defined through the first organic layer.
However, Lee teaches wherein the display substrate ( Fig. 4 ) further comprises a first organic layer ( Fig. 9 second planarization film #180 ), the power compensation line ( Fig. 4: VSL ) is between the first organic layer ( as shown in Fig. 22 VSL is in the NDA region and the organic layer is in the DA2 region ) and the base substrate ( Fig. 4: SUB1), the power line ( Fig 4: VSL ) is on a side of the first organic layer ( Fig. 9 #180 ) facing away from the base substrate ( Fig. 9: SUB1 ), and the sixth via-hole structure ( Fig. 9: ANCT3 ) is defined through the first organic layer ( Fig. 9 #180 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Cho and Son to implement the display substrate further comprises a first organic layer, the power compensation line is between the first organic layer and the base substrate, the power line is on a side of the first organic layer facing away from the base substrate, and the sixth via-hole structure is defined through the first organic layer because this improves signal integrity, voltage stabilization, and efficient power distribution.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817