DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 15 are rejected under 35 U.S.C. 102 as being anticipated by (Yu et al.; US 2022/0320225 A1; hereinafter Yu )
Regarding claim 1, Yu teaches a display substrate, comprising: a base substrate ( Fig. 17 base substrate 40 ), a plurality of data lines ( Fig. 16 data lines 981 and 982 ) and sub-pixels ( [0175] As shown in FIG. 16 to FIG. 19, in some embodiments, the multiple sub-pixels are divided into multiple pixel units. Each pixel unit includes a red sub-pixel R, a blue sub-pixel B, a first green sub-pixel G1 and a second green sub-pixel G2 ) on the base substrate ( Fig. 17 #40 ); wherein the sub-pixel comprises a sub-pixel driving circuit ( [0135] Each sub-pixel includes a sub-pixel driving circuit ) and a light-emitting element ( [0171] As shown in FIG. 16 to FIG. 19, in some embodiments, the sub-pixel further includes a light-emitting element ); the sub-pixel driving circuit comprises a driving transistor ( Fig. 16 driving transistor T3 ) and a data writing transistor ( Fig. 16 data writing transistor T4 ), and the light-emitting element comprises a first electrode ( Fig. 17 anode pattern 70 ); a second electrode of the driving transistor ( Fig. 16 drain electrode D3 ) is coupled to the corresponding first electrode through a first connection structure ( [0098] A source electrode S6 of the sixth transistor T6 is coupled with the drain electrode D3 of the third transistor T3. A drain electrode D6 of the sixth transistor T6 is coupled with an anode of the light-emitting element EL ); a first electrode of the data writing transistor ( Fig. 16 source electrode S4 ) is coupled to the corresponding data line through a second connection structure ( [0250] A source electrode S4 of the fourth transistor T4 is coupled with the first data line pattern 981 or the second data line pattern 982 ) ; the first connection structure ( as discussed above ) and the second connection structure ( as discussed above ) are in a non-aperture region of the sub-pixel ( [0153] By setting the orthographic projection of the anode pattern 70 onto the base substrate not overlapping the orthographic projection of the aperture 50 onto the base substrate, it avoids the anode pattern 700 from shielding the aperture 50, thereby better ensuring light transmittance of the aperture 50 ); and an orthographic projection of the first connection structure onto the base substrate and an orthographic projection of the second connection structure onto the base substrate are arranged along a first direction ( as shown in Fig. 17 ); the orthographic projection of the second connection structure onto the base substrate ( as shown in Fig. 17 ) and an aperture region of the sub-pixel are arranged along a second direction ( as shown in Fig. 16 ), and the second direction intersects the first direction ( as shown in Fig. 16 ); and wherein the second connection structure comprises: a fourth conductive connection portion ( Fig. 16 fourth conductive connection portion 964 ) and a third via-hole structure ( [0260] The second electrode of the sixth transistor T6 is coupled with the third conductive connection portion 963 through a first via-hole 61 in the third overlapping area ); the fourth conductive connection portion ( Fig. 16 #964 ) is coupled to the first electrode of the data writing transistor ( [0136] A first electrode of the data writing transistor is coupled with the first data line pattern 981or the second data line pattern 982 to receive data signal provided by the first data line pattern 981or the second data line pattern 982 ), and the fourth conductive connection portion ( Fig. 16 #964 ) is coupled to the corresponding data line through the third via-hole structure ( [0262] The fourth conductive connecting portion 964 is coupled with the anode pattern through a third via-hole 63 in the fifth overlapping area ).
Regarding claim 15, Yu teaches a display device ( [0085] In order to further illustrate a display substrate and a method for manufacturing the same, and a display device provided in the embodiments of the present disclosure, a detailed description is given hereinafter in conjunction with the accompanying drawings of the specification ), comprising a display substrate ( [0113] In addition, as shown in FIG. 4, in the display substrate provided in the present disclosure ); wherein the display substrate comprises a base substrate ( Fig. 17 #40 ), a plurality of data lines ( Fig. 16 data lines 981 and 982 ) and sub-pixels ( [0175] As shown in FIG. 16 to FIG. 19, in some embodiments, the multiple sub-pixels are divided into multiple pixel units. Each pixel unit includes a red sub-pixel R, a blue sub-pixel B, a first green sub-pixel G1 and a second green sub-pixel G2 ) on the base substrate ( Fig. 17 #40 ); wherein the sub-pixel comprises a sub-pixel driving circuit ( [0135] Each sub-pixel includes a sub-pixel driving circuit ) and a light-emitting element ( [0171] As shown in FIG. 16 to FIG. 19, in some embodiments, the sub-pixel further includes a light-emitting element ); the sub-pixel driving circuit comprises a driving transistor ( Fig. 16 driving transistor T3 ) and a data writing transistor ( Fig. 16 data writing transistor T4 ), and the light-emitting element comprises a first electrode ( Fig. 17 anode pattern 70 ); a second electrode of the driving transistor ( Fig. 16 drain electrode D3 ) is coupled to the corresponding first electrode through a first connection structure ( [0098] A source electrode S6 of the sixth transistor T6 is coupled with the drain electrode D3 of the third transistor T3. A drain electrode D6 of the sixth transistor T6 is coupled with an anode of the light-emitting element EL ); a first electrode of the data writing transistor ( Fig. 16 source electrode S4 ) is coupled to the corresponding data line through a second connection structure ( [0250] A source electrode S4 of the fourth transistor T4 is coupled with the first data line pattern 981 or the second data line pattern 982 ) ; the first connection structure ( as discussed above ) and the second connection structure ( as discussed above ) are in a non-aperture region of the sub-pixel ( [0153] By setting the orthographic projection of the anode pattern 70 onto the base substrate not overlapping the orthographic projection of the aperture 50 onto the base substrate, it avoids the anode pattern 700 from shielding the aperture 50, thereby better ensuring light transmittance of the aperture 50 ); and an orthographic projection of the first connection structure onto the base substrate and an orthographic projection of the second connection structure onto the base substrate are arranged along a first direction ( as shown in Fig. 17 ); the orthographic projection of the second connection structure onto the base substrate ( as shown in Fig. 17 ) and an aperture region of the sub-pixel are arranged along a second direction ( as shown in Fig. 16 ), and the second direction intersects the first direction ( as shown in Fig. 16 ); and wherein the second connection structure comprises: a fourth conductive connection portion ( Fig. 16 fourth conductive connection portion 964 ) and a third via-hole structure ( [0260] The second electrode of the sixth transistor T6 is coupled with the third conductive connection portion 963 through a first via-hole 61 in the third overlapping area ); the fourth conductive connection portion ( Fig. 16 #964 ) is coupled to the first electrode of the data writing transistor ( [0136] A first electrode of the data writing transistor is coupled with the first data line pattern 981or the second data line pattern 982 to receive data signal provided by the first data line pattern 981 or the second data line pattern 982 ), and the fourth conductive connection portion ( Fig. 16 #964 ) is coupled to the corresponding data line through the third via-hole structure ( [0262] The fourth conductive connecting portion 964 is coupled with the anode pattern through a third via-hole 63 in the fifth overlapping area ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Annotated Fig. 19 from Huang
Claim 2 is rejected under U.S.C. 103 as being unpatentable over Yu et al.; US 2022/0320225 A1; 08/2020 in view of Huang et al.; US 2024/0274611 A1; 06/2022
Claim 2: Yu discloses the display substrate according to claim 1 ( as discussed above ).
Yu does not appear to disclose the first connection structure comprises: a second conductive connection portion, a first via-hole structure, a fifth conductive connection portion and a second via-hole structure; the second conductive connection portion is coupled to the second electrode of the driving transistor, the second conductive connection portion is coupled to the fifth conductive connection portion through the first via-hole structure, and the fifth conductive connection portion is coupled to the corresponding first electrode through the second via-hole structure.
However, Huang teaches the first connection structure comprises: a second conductive connection portion ( Fig. 15: second conductive connection member L2 ), a first via-hole structure ( as shown in Fig. 19 via-holes connect the layers ), a fifth conductive connection portion ( Fig. 13 fifth conductive connection member L5 ) and a second via-hole structure ( as shown in Fig. 19 via-holes connect the layers ); the second conductive connection portion ( Fig. 15: L2 ) is coupled to the second electrode of the driving transistor ( [0048] The output circuitry 13 is electrically coupled to the first node N1, the second node N2, a driving signal output end E1, the first voltage line V1 and a second voltage line V2, and configured to control the driving signal output end E1 to be electrically coupled to the second voltage line V2 under the control of the potential at the first node N1, and control the driving signal output end E1 to be electrically coupled to the first voltage line V1 under the control of the potential at the second node N2 ), the second conductive connection portion ( Fig. 15: L2 ) is coupled to the fifth conductive connection portion ( Fig. 13: L5 ) through the first via-hole structure ( via hole structure shown in annotated Fig. 19 ), and the fifth conductive connection portion ( Fig. 13: L5 ) is coupled to the corresponding first electrode through the second via-hole structure ( as shown in the annotated Fig. 19 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Huang with Yu to implement the first connection structure comprises: a second conductive connection portion, a first via-hole structure, a fifth conductive connection portion and a second via-hole structure; the second conductive connection portion is coupled to the second electrode of the driving transistor, the second conductive connection portion is coupled to the fifth conductive connection portion through the first via-hole structure, and the fifth conductive connection portion is coupled to the corresponding first electrode through the second via-hole structure because this approach is used to electrically link the driving transistor to the pixel while improving reliability and electrical performance.
Claims 4, 7-9, and 18-19 are rejected under U.S.C. 103 as being unpatentable over Yu et al.; US 2022/0320225 A1; 08/2020 in view of Son et al.; US 2022/0246086 A1; 09/2021
Claim 4: Yu discloses the display substrate according to claim 1 ( as discussed above ).
Yu does not appear to disclose the display substrate further comprises a first organic layer and a second organic layer sequentially stacked in a direction away from the base substrate, the first via-hole structure is defined through the first organic layer, and the second via-hole structure is defined through the second organic layer; the second conductive connection portion is between the first organic layer and the base substrate, and the fifth conductive connection portion is between the first organic layer and the second organic layer.
However, Son discloses the display substrate further comprises a first organic layer ( Fig. 11: INS4 ) and a second organic layer ( Fig. 11: INS5 ) sequentially stacked in a direction away from the base substrate ( Fig. 11: BSL ), the first via-hole structure is defined through the first organic layer ( as shown in Fig. 11 ), and the second via-hole structure is defined through the second organic layer ( as shown in Fig. 11 ); the second conductive connection portion ( Fig. 11: SE ) is between the first organic layer ( Fig. 11: INS4 ) and the base substrate ( Fig. 11: BSL ), and the fifth conductive connection portion ( Fig. 11: CH1 ) is between the first organic layer ( Fig. 11: INS4 ) and the second organic layer ( Fig. 11: INS5 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Yu to implement the display substrate further comprises a first organic layer and a second organic layer sequentially stacked in a direction away from the base substrate, the first via-hole structure is defined through the first organic layer, and the second via-hole structure is defined through the second organic layer; the second conductive connection portion is between the first organic layer and the base substrate, and the fifth conductive connection portion is between the first organic layer and the second organic layer because this approach is used for maximizing device density, optimizing signal routing, and improving signal integrity.
Claim 7: Yu discloses the display substrate according to claim 1 ( as discussed above ).
Yu does not appear to disclose the display substrate further comprises: an auxiliary electrode, a third connection structure, and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure; the third connection structure is in the non-aperture region of the sub-pixel; and an orthographic projection of the third connection structure onto the base substrate and the orthographic projection of the first connection structure onto the base substrate are arranged along the first direction.
However, Son teaches the display substrate further comprises: an auxiliary electrode ( Fig. 11: conductive pattern CDP ), a third connection structure ( Fig. 11: area that includes CDP and PL2 in the center section ), and a second electrode layer ( Fig. 11: ELT2 and PL2 in the PXG2 (PXL1) area ); the auxiliary electrode is coupled to the second electrode layer through the third connection structure ( [0175] the conductive pattern CDP may extend toward at least one adjacent pixel PXL, and may be integrally connected to one electrode of the at least one adjacent pixel PXL ); the third connection structure is in the non-aperture region of the sub-pixel ( as shown in Fig. 11 ); and an orthographic projection of the third connection structure onto the base substrate and the orthographic projection of the first connection structure onto the base substrate are arranged along the first direction ( as shown in Fig. 11 the first and third structures are distributed along the first direction ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Yu to implement the display substrate further comprises: an auxiliary electrode, a third connection structure, and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure; the third connection structure is in the non-aperture region of the sub-pixel; and an orthographic projection of the third connection structure onto the base substrate and the orthographic projection of the first connection structure onto the base substrate are arranged along the first direction because this improves the aperture ratio and enhances signal transmission.
Claim 8: Yu discloses the display substrate according to claim 1 ( as discussed above ).
Yu does not appear to disclose the display substrate further comprises: an auxiliary electrode, a third connection structure, and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure; the third connection structure is in the non-aperture region of the sub-pixel; and an orthographic projection of the third connection structure onto the base substrate is at least partly staggered from the orthographic projection of the first connection structure onto the base substrate.
However, Son teaches the display substrate further comprises: an auxiliary electrode ( Fig. 11: conductive pattern CDP ), a third connection structure ( Fig. 11: area that includes CDP and PL2 in the center section ), and a second electrode layer ( Fig. 11: ELT2 and PL2 in the PXG2 (PXL1) area ); the auxiliary electrode is coupled to the second electrode layer through the third connection structure ( [0175] the conductive pattern CDP may extend toward at least one adjacent pixel PXL, and may be integrally connected to one electrode of the at least one adjacent pixel PXL ); the third connection structure is in the non-aperture region of the sub-pixel ( as shown in Fig. 11 ); and an orthographic projection of the third connection structure onto the base substrate is at least partly staggered from the orthographic projection of the first connection structure onto the base substrate ( as shown in Fig. 11 the third connection structure and the first connection structure are not vertically aligned ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Yu to implement the display substrate further comprises: an auxiliary electrode, a third connection structure, and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure; the third connection structure is in the non-aperture region of the sub-pixel; and an orthographic projection of the third connection structure onto the base substrate is at least partly staggered from the orthographic projection of the first connection structure onto the base substrate because this optimizes the display’s aperture ratio while ensuring reliable electrical coupling and a uniform electric field.
Claim 9: Yu and Son disclose the display substrate according to claim 7 ( as discussed above ).
Yu does not appear to disclose the display substrate further comprises a second organic layer and a pixel definition layer sequentially stacked in a direction away from the base substrate; the third connection structure comprises: a fourth via-hole structure, a connecting pattern and a fifth via-hole structure; the auxiliary electrode is between the second organic layer and the base substrate; at least a portion of the second electrode layer is at a side of the pixel definition layer facing away from the base substrate; at least a portion of the connecting pattern is between the second organic layer and the pixel definition layer; the fourth via-hole structure is defined through the second organic layer, and the fifth via-hole structure is defined through the pixel definition layer; the connecting pattern is coupled to the auxiliary electrode through the fourth via-hole structure, and the connecting pattern is coupled to the second electrode layer through the fifth via- hole structure.
However, Son discloses the display substrate further comprises a second organic layer ( Fig. 11: INS5 ) and a pixel definition layer ( Fig. 11 DPL ) sequentially stacked in a direction away ( as shown in Fig. 11 ) from the base substrate ( Fig. 11: BSL ); the third connection structure ( Fig. 11: area that includes CDP and PL2 in the center section ) comprises: a fourth via-hole structure, a connecting pattern and a fifth via-hole structure ( [0175] the conductive pattern CDP may be connected to the second power source line PL2 through the second contact hole CH2 formed in the first PXL1 of the second pixel group PXG2 without forming a contact hole for connecting the conductive pattern CDP to the second power source line PL2 ); the auxiliary electrode ( Fig. 11: CDP ) is between the second organic layer ( Fig. 11: INS5 ) and the base substrate ( Fig. 11: BSL ); at least a portion of the second electrode layer ( Fig. 11: ELT2 and PL2 in the PXG2 (PXL1) area ) is at a side of the pixel definition layer facing away from the base substrate ( Fig. 11: BSL) ; at least a portion of the connecting pattern ( Fig. 11 flat portion of the CDP) is between the second organic layer ( Fig. 11: INS5 ) and the pixel definition layer ( Fig. 11: DPL ); the fourth via-hole structure ( [0175] the conductive pattern CDP may be connected to the second power source line PL2 through the second contact hole CH2 formed in the first PXL1 of the second pixel group PXG2 without forming a contact hole for connecting the conductive pattern CDP to the second power source line PL2 ) is defined through the second organic layer ( Fig. 11: INS5 ), and the fifth via-hole structure is defined through the pixel definition layer ( Fig. 11; DPL ); the connecting pattern is coupled to the auxiliary electrode through the fourth via-hole structure ( as discussed above ), and the connecting pattern is coupled to the second electrode layer through the fifth via- hole structure ( [0175] the conductive pattern CDP may extend toward at least one adjacent pixel PXL, and may be integrally connected to one electrode of the at least one adjacent pixel PXL ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Yu to implement the display substrate further comprises a second organic layer and a pixel definition layer sequentially stacked in a direction away from the base substrate; the third connection structure comprises: a fourth via-hole structure, a connecting pattern and a fifth via-hole structure; the auxiliary electrode is between the second organic layer and the base substrate; at least a portion of the second electrode layer is at a side of the pixel definition layer facing away from the base substrate; at least a portion of the connecting pattern is between the second organic layer and the pixel definition layer; the fourth via-hole structure is defined through the second organic layer, and the fifth via-hole structure is defined through the pixel definition layer; the connecting pattern is coupled to the auxiliary electrode through the fourth via-hole structure, and the connecting pattern is coupled to the second electrode layer through the fifth via- hole structure because this improves the conductivity and thermal management of the device.
Claim 18: Yu discloses the display device according to claim 15 ( as discussed above).
Yu does not appear to disclose the display substrate further comprises a first organic layer and a second organic layer sequentially stacked in a direction away from the base substrate, the first via-hole structure is defined through the first organic layer, and the second via-hole structure is defined through the second organic layer; the second conductive connection portion is between the first organic layer and the base substrate, and the fifth conductive connection portion is between the first organic layer and the second organic layer.
However, Son discloses the display substrate further comprises a first organic layer ( Fig. 11: INS4 ) and a second organic layer ( Fig. 11: INS5 ) sequentially stacked in a direction away from the base substrate ( Fig. 11: BSL ), the first via-hole structure is defined through the first organic layer ( as shown in Fig. 11 ), and the second via-hole structure is defined through the second organic layer ( as shown in Fig. 11 ); the second conductive connection portion ( Fig. 11: SE ) is between the first organic layer ( Fig. 11: INS4 ) and the base substrate ( Fig. 11: BSL ), and the fifth conductive connection portion ( Fig. 11: CH1 ) is between the first organic layer ( Fig. 11: INS4 ) and the second organic layer ( Fig. 11: INS5 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Yu to implement the display substrate further comprises a first organic layer and a second organic layer sequentially stacked in a direction away from the base substrate, the first via-hole structure is defined through the first organic layer, and the second via-hole structure is defined through the second organic layer; the second conductive connection portion is between the first organic layer and the base substrate, and the fifth conductive connection portion is between the first organic layer and the second organic layer because this achieves complex, high-density electrical routing, providing electrical isolation between different conductive layers.
Claim 19: Yu and Son disclose the display device according to claim 18 ( as discussed above ).
Yu does not appear to disclose the third via-hole structure is defined through the first organic layer; and the fourth conductive connection portion is between the first organic layer and the base substrate.
However, Son teaches the third via-hole structure ( Fig. 11 ) is defined through the first organic layer ( Fig. 11: INS4 ); and the fourth conductive connection portion ( Fig. 11: CRE1(T1) DE)) is between the first organic layer ( Fig. 11: INS4 ) and the base substrate ( Fig. 11 BSL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Son with Yu to implement the third via-hole structure is defined through the first organic layer; and the fourth conductive connection portion is between the first organic layer and the base substrate because this will optimize signal routing and maximize the available surface area for components.
Claims 5-6, 10-11, and 13 are rejected under U.S.C. 103 as being unpatentable over Yu et al.; US 2022/0320225 A1; 08/2020 in view of Son et al.; US 2022/0246086 A1; 09/2021 and Cho et al.; US 11,804,181 B2; 09/2022
Claim 5: Yu and Son disclose the display substrate according to claim 4 ( as discussed above ).
Yu does not appear to disclose the third via-hole structure is defined through the first organic layer; and the fourth conductive connection portion is between the first organic layer and the base substrate.
However, Son teaches the third via-hole structure ( Fig. 11 ) is defined through the first organic layer ( Fig. 11: INS4 ); and the fourth conductive connection portion ( Fig. 11: CRE1(T1) DE)) is between the first organic layer ( Fig. 11: INS4 ) and the base substrate ( Fig. 11 BSL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yu with Cho to implement the third via-hole structure is defined through the first organic layer; and the fourth conductive connection portion is between the first organic layer and the base substrate because this optimizes signal routing and enables complex circuit designs.
Claim 6: Yu and Son disclose the display substrate according to claim 5 ( as discussed above ).
Neither Yu nor Son appear to disclose the display substrate further comprises: a first passivation layer and a second passivation layer; the first passivation layer is between the first organic layer and the second passivation layer, the second passivation layer is between the first passivation layer and the second organic layer; the first via-hole structure and the third via-hole structure are both defined through the first passivation layer, and the second via-hole structure is defined through the second passivation layer; the fifth conductive connection portion is between the first passivation layer and the second passivation layer.
However, Cho teaches the display substrate further comprises: a first passivation layer ( Fig. 6: passivation layer PAS0 ) and a second passivation layer ( Fig. 6: passivation layer PAS1 ); the first passivation layer ( Fig. 6: PAS0 ) is between the first organic layer ( Fig. 6: PLN1 ) and the second passivation layer ( Fig. 6: PAS1 ), the second passivation layer ( Fig. 6: PAS1 ) is between the first passivation layer ( Fig. 6: PAS0 ) and the second organic layer ( Fig. 6 PCL ); the first via-hole structure ( Col. 21 lines 7-12 The second source-drain electrode pattern SD2 may be connected to one of the two first source-drain electrode patterns SD1 through a contact hole formed in the first planarization layer PLN1 ) and the third via-hole structure are both defined through the first passivation layer ( Fig. 6: PAS0 ), and the second via-hole structure ( bottom portion of Fig. 6 SD1 that passes through ILD2 ) is defined through the second passivation layer ( Fig. 6 PAS1 ); the fifth conductive connection portion ( Fig. 6 SD1 ) is between the first passivation layer ( Fig. 6 PAS0 ) and the second passivation layer ( Fig. 6 PAS1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cho with Yu and Son to implement the display substrate further comprises: a first passivation layer and a second passivation layer; the first passivation layer is between the first organic layer and the second passivation layer, the second passivation layer is between the first passivation layer and the second organic layer; the first via-hole structure and the third via-hole structure are both defined through the first passivation layer, and the second via-hole structure is defined through the second passivation layer; the fifth conductive connection portion is between the first passivation layer and the second passivation layer because multiple passivation layers and strategic via-hole structures are used to improve performance, reliability, and manufacturability.
Claim 10: Yu and Son disclose the display substrate according to claim 9 ( as discussed above).
Neither Yu nor Son appear to disclose the plurality of sub-pixels are divided into an array of repeating units, each repeating unit comprises two sub-units arranged along the first direction, and each sub-unit comprises the plurality of sub-pixels arranged along the first direction; the orthographic projection of the auxiliary electrode onto the base substrate is located between orthographic projections of the two sub-units onto the base substrate.
However, Cho teaches the plurality of sub-pixels ( as shown in Fig. 4 ) are divided into an array of repeating units ( Fig. 4 OA1 and OA2 ), each repeating unit comprises two sub-units arranged along the first direction ( Fig. 4 OA1 and OA2 ), and each sub-unit comprises the plurality of sub-pixels arranged along the first direction ( Fig. 4L EA of Red SP, EA of Green SP, and EA of Blue SP are arranged in each of the sub-units ); the orthographic projection of the auxiliary electrode onto the base substrate is located between orthographic projections of the two sub-units onto the base substrate ( as shown in Fig. 6 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cho with Yu and Son to implement the plurality of sub-pixels are divided into an array of repeating units, each repeating unit comprises two sub-units arranged along the first direction, and each sub-unit comprises the plurality of sub-pixels arranged along the first direction; the orthographic projection of the auxiliary electrode onto the base substrate is located between orthographic projections of the two sub-units onto the base substrate because this approach provides uniformity and manufacturability, color and brightness control, and subpixel rendering and resolution enhancement.
Claim 11: Yu, Son and Cho disclose the display substrate according to claim 10 ( as discussed above ).
Neither Yu nor Son appear to disclose the display substrate further comprises a power line and a power compensation line; the sub-pixel driving circuit further comprises a light-emitting control transistor; a first electrode of the light-emitting control transistor is coupled to the power compensation line, and a second electrode of the light-emitting control transistor is coupled to a first electrode of the driving transistor; the power compensation line is coupled to the power line through a sixth via-hole structure, and the sixth via-hole structure is in the non-aperture region of the sub-pixel.
Cho teaches the display substrate further comprises a power line ( Fig. 9 plurality of power lines VL21 to VL 2n ) and a power compensation line ( Fig. 10 pixel driving power line VLd ); the sub-pixel driving circuit further comprises a light-emitting control transistor ( Fig. 10: T3 ); a first electrode of the light-emitting control transistor ( Fig. 10: T3 ) is coupled to the power compensation line ( Fig. 10: VLd ), and a second electrode of the light-emitting control transistor ( Fig. 10: T3 ) is coupled to a first electrode of the driving transistor ( Fig. 10 a driving transistor DRT ); the power compensation line ( Fig. 10: VLd ) is coupled to the power line ( Fig. 10: ELVDD ) through a sixth via-hole structure ( Col. 30 lines 50 – 55 When the third transistor T3 is turned on by the emission signal EMS, the pixel driving power line VLd supplying the pixel driving voltage ELVDD and the second node N2 can be connected ), and the sixth via-hole structure is in the non-aperture region of the sub-pixel ( as shown in Fig. 2 the control structures are outside the active region of the display ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cho with Yu and Son to implement the display substrate further comprises a power line and a power compensation line; the sub-pixel driving circuit further comprises a light-emitting control transistor; a first electrode of the light-emitting control transistor is coupled to the power compensation line, and a second electrode of the light-emitting control transistor is coupled to a first electrode of the driving transistor; the power compensation line is coupled to the power line through a sixth via-hole structure, and the sixth via-hole structure is in the non-aperture region of the sub-pixel because this approach provides voltage stability, current control, and pixel uniformity.
Claim 13: Yu, Son and Cho disclose the display substrate according to claim 11 ( as discussed above).
Neither Yu nor Son appear to disclose orthographic projections of the power lines onto the base substrate and orthographic projections of the repeating units onto the base substrate are alternately arranged along the first direction.
However, Cho teaches orthographic projections of the power lines ( Fig. 5A: VL1 and Fig. 5B: VL2 ) onto the base substrate ( Fig. 6: SUB1 ) and orthographic projections of the repeating units ( Fig. 5A: OA1 and Fig. 5B: OA2 ) onto the base substrate ( Fig. 6: SUB1 ) are alternately arranged along the first direction (as shown in Figs. 5A and 5B ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cho with Yu and Son to implement orthographic projections of the power lines onto the base substrate and orthographic projections of the repeating units onto the base substrate are alternately arranged along the first direction because this approach provides pattern alignment and registration, avoids symmetry conflicts, and uniformity and defect control.
Claim 20: Yu and Son disclose the display device according to claim 19 ( as discussed above ).
Neither Yu nor Son appear to disclose the display substrate further comprises: a first passivation layer and a second passivation layer; the first passivation layer is between the first organic layer and the second passivation layer, the second passivation layer is between the first passivation layer and the second organic layer; the first via-hole structure and the third via-hole structure are both defined through the first passivation layer, and the second via-hole structure is defined through the second passivation layer; the fifth conductive connection portion is between the first passivation layer and the second passivation layer.
However, Cho teaches the display substrate further comprises: a first passivation layer ( Fig. 6: passivation layer PAS0 ) and a second passivation layer ( Fig. 6: passivation layer PAS1 ); the first passivation layer ( Fig. 6: PAS0 ) is between the first organic layer ( Fig. 6: PLN1 ) and the second passivation layer ( Fig. 6: PAS1 ), the second passivation layer ( Fig. 6: PAS1 ) is between the first passivation layer ( Fig. 6: PAS0 ) and the second organic layer ( Fig. 6 PCL ); the first via-hole structure ( Col. 21 lines 7-12 The second source-drain electrode pattern SD2 may be connected to one of the two first source-drain electrode patterns SD1 through a contact hole formed in the first planarization layer PLN1 ) and the third via-hole structure are both defined through the first passivation layer ( Fig. 6: PAS0 ), and the second via-hole structure ( bottom portion of Fig. 6 SD1 that passes through ILD2 ) is defined through the second passivation layer ( Fig. 6 PAS1 ); the fifth conductive connection portion ( Fig. 6 SD1 ) is between the first passivation layer ( Fig. 6 PAS0 ) and the second passivation layer ( Fig. 6 PAS1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cho with Yu and Son to implement the display substrate further comprises: a first passivation layer and a second passivation layer; the first passivation layer is between the first organic layer and the second passivation layer, the second passivation layer is between the first passivation layer and the second organic layer; the first via-hole structure and the third via-hole structure are both defined through the first passivation layer, and the second via-hole structure is defined through the second passivation layer; the fifth conductive connection portion is between the first passivation layer and the second passivation layer because multiple passivation layers provides functional separation and protection.
Claim 12 is rejected under U.S.C. 103 as being unpatentable over Yu et al.; US 2022/0320225 A1; 08/2020 in view of Cho et al.; US 11,804,181 B2; 09/2022 and Son et al.; US 2022/0246086 A1; 09/2021 as it relates to claim 11 and further in view of Lee et al.; US 2022/0165217 A1; 09/2021
Claim 12: Yu, Son and Cho disclose the display substrate according to claim 11 ( as discussed above).
Neither Yu nor Cho nor Son appear to disclose the display substrate further comprises a first organic layer, the power compensation line is between the first organic layer and the base substrate, the power line is on a side of the first organic layer facing away from the base substrate, and the sixth via-hole structure is defined through the first organic layer.
However, Lee teaches wherein the display substrate ( Fig. 4 ) further comprises a first organic layer ( Fig. 9 second planarization film #180 ), the power compensation line ( Fig. 4: VSL ) is between the first organic layer ( as shown in Fig. 22 VSL is in the NDA region and the organic layer is in the DA2 region ) and the base substrate ( Fig. 4: SUB1), the power line ( Fig 4: VSL ) is on a side of the first organic layer ( Fig. 9 #180 ) facing away from the base substrate ( Fig. 9: SUB1 ), and the sixth via-hole structure ( Fig. 9: ANCT3 ) is defined through the first organic layer ( Fig. 9 #180 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Yu, Cho, and Son to implement the display substrate further comprises a first organic layer, the power compensation line is between the first organic layer and the base substrate, the power line is on a side of the first organic layer facing away from the base substrate, and the sixth via-hole structure is defined through the first organic layer because this improves signal integrity, voltage stabilization, and efficient power distribution.
Claims 14 and 16 are rejected under U.S.C. 103 as being unpatentable over Yu et al.; US 2022/0320225 A1; 08/2020 in view of Cho et al.; US 11,804,181 B2; 09/2022
Claim 14: Yu discloses the display substrate according to claim 1 ( as discussed above).
Yu does not appear to disclose the display substrate further comprises: a plurality of light-emitting control lines, power lines, an initialization signal line, a reference signal line, a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines and a plurality of partition control lines; the sub-pixel driving circuit further comprises: a compensation transistor, a reset transistor, the light-emitting control transistor, a writing control transistor and a storage capacitor; a gate electrode of the data writing transistor is coupled to the corresponding first scan line, and a second electrode of the data writing transistor is coupled to a first electrode of the writing control transistor; a second electrode of the writing control transistor is coupled to a gate electrode of the driving transistor, and a gate electrode of the writing control transistor is coupled to the corresponding partition control line; a gate electrode of the compensation transistor is coupled to the corresponding second scan line, a first electrode of the compensation transistor is coupled to the reference signal line, and a second electrode of the compensation transistor is coupled to the first electrode of the writing control transistor; a gate electrode of the reset transistor is coupled to the corresponding third scan line, a first electrode of the reset transistor is coupled to the initialization signal line, and a second electrode of the reset transistor is coupled to the second electrode of the driving transistor; a gate electrode of the light-emitting control transistor is coupled to the corresponding light-emitting control line, the first electrode of the light-emitting control transistor is coupled to the power line, and the second electrode of the light-emitting control transistor is coupled to the first electrode of the driving transistor; a first electrode plate of the storage capacitor is coupled to the gate electrode of the driving transistor, and a second electrode plate of the storage capacitor is coupled to the second electrode of the driving transistor.
However, Cho teaches the display substrate ( Fig. 6 ) further comprises: a plurality of light-emitting control lines ( Col. 9 lines 3 – 7 The display controller #240 can supply a data driving control signal DCS to the data driving circuit #220 ) , power lines ( Col. 28 lines 23-31 a plurality of power lines VL21 to VL2n ), an initialization signal line ( Col. 28 lines 23 – 31 the plurality of first initialization voltage lines VL11 to VL1n ), a reference signal line ( Col. 15 lines 52 – 60 include the reference voltage lines ), a plurality of first scan lines ( Fig. 10: SCAN1 signal GL1 ), a plurality of second scan lines ( Fig. 10: SCAN2 signal GL2 ), a plurality of third scan lines ( Fig. 10: SCAN3 signal GL3 ) and a plurality of partition control lines ( Fig. 2: gate control signal GCS ); the sub-pixel driving circuit further comprises: a compensation transistor ( Fig. 10: conductive layer BSM), a reset transistor ( Fig. 10: T5 ), the light-emitting control transistor ( Fig. 10: T2 ), a writing control transistor ( Fig. 10: T_com ) and a storage capacitor ( Fig. 10: Cstg ); a gate electrode of the data writing transistor ( Fig. 10: DRT ) is coupled to the corresponding first scan line ( as shown in Fig. 10 ) , and a second electrode of the data writing transistor ( Fig. 10: DRT ) is coupled to a first electrode of the writing control transistor ( as shown in Fig. 10 ); a second electrode of the writing control transistor ( Fig. 10: T1 ) is coupled to a gate electrode of the driving transistor ( Fig. 10: DRT ), and a gate electrode of the writing control transistor ( Fig. 10: T1 ) is coupled to the corresponding partition control line ( Fig. 10: GL1 ); a gate electrode of the compensation transistor ( Fig. 10: BSM ) is coupled to the corresponding second scan line ( Fig. 10: SCAN2 ), a first electrode of the compensation transistor ( Fig. 10: BSM ) is coupled to the reference signal line ( Fig. 10 VLd ), and a second electrode of the compensation transistor ( Fig. 10: BSM ) is coupled to the first electrode of the writing control transistor ( Fig. 10: T1 ); a gate electrode of the reset transistor ( Fig. 10: T5 ) is coupled to the corresponding third scan line ( Fig. 10: SCAN3 ), a first electrode of the reset transistor ( Fig. 10: T5 ) is coupled to the initialization signal line ( Fig. 10: Dvini ), and a second electrode of the reset transistor ( Fig. 10: T5 ) is coupled to the second electrode of the driving transistor ( Fig. 10: N3 ); a gate electrode of the light-emitting control transistor ( Fig. 10: T2 ) is coupled to the corresponding light- emitting control line ( as shown in Fig. 10 ), the first electrode of the light-emitting control transistor ( Fig. 10: T2 ) is coupled to the power line ( Fig. 10: Vdata ), and the second electrode of the light-emitting control transistor ( Fig. 10: T2 ) is coupled to the first electrode of the driving transistor ( Fig. 10 DRT ); a first electrode plate of the storage capacitor ( Fig. 10: Cstg ) is coupled to the gate electrode of the driving transistor ( Fig. 10: N1 ), and a second electrode plate of the storage capacitor ( Fig. 10 Cstg ) is coupled to the second electrode of the driving transistor ( as shown in Fig. 10 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cho with Yu to implement the display substrate further comprises: a plurality of light-emitting control lines, power lines, an initialization signal line, a reference signal line, a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines and a plurality of partition control lines; the sub-pixel driving circuit further comprises: a compensation transistor, a reset transistor, the light-emitting control transistor, a writing control transistor and a storage capacitor; a gate electrode of the data writing transistor is coupled to the corresponding first scan line, and a second electrode of the data writing transistor is coupled to a first electrode of the writing control transistor; a second electrode of the writing control transistor is coupled to a gate electrode of the driving transistor, and a gate electrode of the writing control transistor is coupled to the corresponding partition control line; a gate electrode of the compensation transistor is coupled to the corresponding second scan line, a first electrode of the compensation transistor is coupled to the reference signal line, and a second electrode of the compensation transistor is coupled to the first electrode of the writing control transistor; a gate electrode of the reset transistor is coupled to the corresponding third scan line, a first electrode of the reset transistor is coupled to the initialization signal line, and a second electrode of the reset transistor is coupled to the second electrode of the driving transistor; a gate electrode of the light-emitting control transistor is coupled to the corresponding light-emitting control line, the first electrode of the light-emitting control transistor is coupled to the power line, and the second electrode of the light-emitting control transistor is coupled to the first electrode of the driving transistor; a first electrode plate of the storage capacitor is coupled to the gate electrode of the driving transistor, and a second electrode plate of the storage capacitor is coupled to the second electrode of the driving transistor because this approach controls light emission, reset states, and drive voltages.
Claim 16: Yu discloses the display device according to claim 15 ( as discussed above ).
Yu does not appear to disclose the first connection structure comprises: a second conductive connection portion, a first via-hole structure, a fifth conductive connection portion and a second via-hole structure; the second conductive connection portion is coupled to the second electrode of the driving transistor, the second conductive connection portion is coupled to the fifth conductive connection portion through the first via-hole structure, and the fifth conductive connection portion is coupled to the corresponding first electrode through the second via-hole structure.
However, Cho teaches the first connection structure ( Fig. 6 area containing SD2 and SD1) comprises: a second conductive connection portion ( Col 21 lines 6-7 A second source-drain electrode pattern SD2 may be disposed on the first planarization layer PLn1 ), a first via-hole structure ( Col. 21 lines 7-12 The second source-drain electrode pattern SD2 may be connected to one of the two first source-drain electrode patterns SD1 through a contact hole formed in the first planarization layer PLN1 ), a fifth conductive connection portion ( Fig. 6 SD1 ) and a second via-hole structure ( bottom portion of Fig. 6 SD1 that passes through ILD2 ); the second conductive connection portion ( as described above ) is coupled to the second electrode of the driving transistor ( as shown in Fig. 6 ), the second conductive connection portion is coupled to the fifth conductive connection portion ( Fig. 6 SD1 ) through the first via-hole structure ( as discussed above ), and the fifth conductive connection portion ( Fig. 6 SD1 ) is coupled to the corresponding first electrode through the second via-hole structure ( as described above ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Cho with Yu to implement the first connection structure comprises: a second conductive connection portion, a first via-hole structure, a fifth conductive connection portion and a second via-hole structure; the second conductive connection portion is coupled to the second electrode of the driving transistor, the second conductive connection portion is coupled to the fifth conductive connection portion through the first via-hole structure, and the fifth conductive connection portion is coupled to the corresponding first electrode through the second via-hole structure because this approach improves reliability, manufacturability, and electrical performance.
Response to Amendment
Applicant’s arguments, see page 12 of remarks, filed 04/30/2026, with respect to Drawings have been fully considered and are persuasive. The objection of 02/05/2026 has been withdrawn.
Applicant’s arguments, see pages 14-15 of remarks, filed 04/30/2026, with respect to the rejection of claim 1 under Cho have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Yu.
Applicant’s arguments, see pages 15, filed 04/30/2026, with respect to the rejection of claim 1 under Son have been fully considered but are not persuasive since Son was not cited in the rejection of claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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