DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 8, and by extension, dependent claims 2-7 and 9-14, recite the limitation “the projection of the active layer on the substrate,” "the projection of an overlapping area between the scan line and the data line on the substrate," and “the projection of the gate on the substrate.” There is insufficient antecedent basis for these limitations in the claim.
Claims 4 and 11, and by extension, dependent claims 5-6 and 12-13 recite the limitation of “the projection of the touch line on the substrate” and “the projection of the data line on the substrate.” There is insufficient antecedent basis for these limitations in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Xue (US 2019/0146293 A1) in view of Xu (US 2023/0028565 A1) and Lu (US 2018/0240821 A1) as evidenced by Hao (US 2019/0237034 A1).
Regarding claim 1, Xue teaches an array substrate (Figs. 1-3; see Title), comprising:
a substrate (600);
a first metal layer (the data line layer of 400; see ¶ [0038]) disposed on an upper surface (upper surface of 600) of the substrate, wherein the first metal layer comprises a data line (¶ [0033]: 400 is a data line);
a first insulating layer (510) disposed on an upper surface (upper surface of 400) of the first metal layer, wherein the first insulating layer covers the data line (Fig. 2 shows 510 covering 400);
an active layer (300) disposed above the first insulating layer and a source (110, see also ¶ [0041]) electrically connected with the data line (see ¶ [0039]);
a gate insulating layer (520) disposed on the active layer and a second metal layer (140) disposed on the gate insulating layer (¶ [0047]: a portion of 140 is formed as gate electrode 130; Figs. 2 & 1 shows 130 disposed on 520), wherein the second metal layer comprises a scan line (¶ [0047]: 140 is a gate line; as evidenced by Hao ¶ [0027], a gate line is also known as a scan line) and a gate (130) electrically connected with the scan line;
a pixel electrode (210) disposed above the first insulating layer (Fig. 2 shows 210 is above 510), wherein the pixel electrode is electrically connected with a drain (120; see ¶ [0032], [0041]).
However, Xue does not teach the array substrate wherein the projection of the active layer on the substrate overlaps with the projection of an overlapping area between the scan line and the data line on the substrate, the projection of the gate on the substrate overlaps with the projection of the active layer on the substrate.
Xu, in the same field of invention, teaches an array substrate (1, see Fig. 1 and Title) wherein the projection (vertical projection of 70 towards 10) of the active layer (70) on the substrate (10) overlaps with the projection (vertical projection of the overlapping area towards 10) of an overlapping area (overlapping area between 92 and 30 when Fig. 1 is seen at a plan view) between the scan line (92) and the data line (30) on the substrate, the projection (vertical projection of 92 towards 10) of the gate (92 is a gate) on the substrate overlaps with the projection (vertical projection of 70 towards 10) of the active layer (70) on the substrate.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Xu into the device of Xue to have a projection of the active layer on the substrate overlap with a projection of an overlapping area between the scan line and the data line on the substrate, and a projection of the gate on the substrate overlaps with a projection of the active layer on the substrate. The ordinary artisan would have been motivated to modify Xue in the manner set forth above for at least the purpose of saving space occupied by data lines which reduces the size of the thin film transistor, improves pixel density, and increases product competitiveness (Xu ¶ [0018]).
Xue in view of Xu further teaches the active layer to be part of a thin film transistor, with the thin film transistor further comprising the source, the drain, and the gate (Xue ¶ [0041]; alternatively, Xu ¶ [0030] teaches the active layer (70) TFT to have a source (72) and a drain (73)). However, Xue in view of Xu does not teach the source, drain, and active layer to be a metal oxide semiconductor layer, wherein the source and drain are conductors, the active layer is a semiconductor, and the drain and source are connected through the active layer.
Lu, in the same field of invention teaches a thin film transistor (201, see Fig. 2A) having a source (206), a drain (208), and an active layer (204) to be a metal oxide semiconductor layer (see ¶ [0038]), wherein the source and drain are conductors (¶ [0039]: “the resistivity's of the MO source region 206 and the MO drain region 208 are lower than the resistivity of the MO channel region… the MO source region 206 and the MO drain region 208 can be made highly conductive” due to ion implantation), the active layer is a semiconductor (¶ [0039]: “This process reduces the initial conductivity of the channel region…”), and the drain and source are connected through the active layer (see Fig. 2A and ¶ [0038]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lu into the device of Xue in view of Xu to modify the source, drain, and active regions of the thin film transistor to be comprised of a metal oxide semiconductor layer, with the source and drain to be connected through the active layer, and with the source and drain region to be conductive and with the active layer to be semiconductive. The ordinary artisan would have been motivated to modify Xue in view of Xu in the manner set forth above for at least the purpose of increasing the performance of the device (Lu ¶ [0039]). The ordinary artisan would also find it obvious to connect the source and drain through the active layer so that the active layer functions as a channel region for the gate to control the current through the thin-film transistor (Lu ¶ [0038], [0029]).
Claims 2, 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Xue (US 2019/0146293 A1) in view of Xu (US 2023/0028565 A1) and Lu (US 2018/0240821 A1) as evidenced by Hao (US 2019/0237034 A1) as applied to claim 1 above, and further in view of Nam (US 2019/0172882 A1).
Regarding claim 2, Xue et al teaches the array substrate according to claim 1, wherein the array substrate further comprises a third insulating layer (700; see Xue Fig. 2) disposed on the second metal layer (Xue Fig. 2 shows 700 disposed on gate 130, which is part of metal layer 140), the third insulating layer covers the scan line and the gate (Xue Figs. 2 & 3 shows 700 covering gate 130 and scan line 140).
Xue et al further teaches the third insulating layer disposed above the drain (120) and below the pixel electrode (210). However, Xue et al does not teach: a transparent conductive layer disposed on the third insulating layer, with the transparent conductive layer comprises a plurality of common electrode blocks, and the common electrode block is insulated from the pixel electrode.
Nam, in the same field of invention, teaches an array substrate (200; ¶ [0037]) comprising of a transparent conductive layer (see Figs. 5C & 5E and ¶ [0058], [0060]: pixel electrodes 122 and common electrode blocks 132 are patterned from a transparent conductive layer) disposed on the third insulating layer (116; this is analogous to the third insulating layer since it is disposed above the drain 110 and below the pixel electrode 122), with the transparent conductive layer comprises a plurality of common electrode blocks (132; see Figs. 4 and ¶ [0042]), and the common electrode block is insulated (through 124, 126, and 128; see ¶ [0048]-[0047], [0052]) from the pixel electrode (122).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Nam into the device of Xue et al to add a transparent conductive layer that is disposed above the third insulating layer and that is then patterned to a form a plurality of common electrode blocks and pixel electrodes, with the common electrode blocks insulated from the pixel electrodes. The ordinary artisan would have been motivated to modify Xue et al in the manner set forth above for at least the purpose of enabling a touch-sensing display device (Nam ¶ [0003]), wherein the common electrode blocks are used as touch electrodes that are further connected to touch lines (TSLs; see ¶ [0050]) for the further purpose of reducing parasitic capacitances of the touch lines of the said device (¶ [0051], [0052]) and improving device touch accuracy (¶ [0004]).
Regarding claim 3, the array substrate according to claim 2, wherein the transparent conductive layer further comprises a second connecting block (Xue ¶ [0042]: “The via connecting the source electrode 110 and the data line 400”, see also Xue Fig. 2; in view of Nam, an ordinary artisan would make this via to be part of transparent conductive layer since Nam teaches a display device, i.e., an opaque via would impede the display device from displaying images correctly), and the data line is electrically connected with the source through the second connecting block (see Xue ¶ [0042]).
Regarding claim 4, the array substrate according to claim 2, wherein the array substrate further comprises a touch metal layer (the metal layer of TSL; see Nam Fig. 4) disposed on the first insulating layer (112; Xue et al in view of Nam teaches TSL above the first insulating layer of Xue since TSL is located above the source/drain of the TFT 100), the touch metal layer comprises a touch line (TSL), the projection (vertical projection of TSL towards 101) of the touch line on the substrate (101) overlaps with the projection (vertical projection of DL1 and/or DL2 towards 101) of the data line (left TSL overlaps with DL2; right TSL overlaps with DL1) on the substrate, an extension direction of the touch line is parallel to an extension direction of the data line (Nam ¶ [0042]), and each common electrode block is electrically connected with a corresponding touch line (Nam ¶ [0044]).
Regarding claim 7, the array substrate according to claim 2, wherein the transparent conductive layer further comprises the pixel electrode (Nam ¶ [0067]: “by patterning the transparent conductive mask layer 178... the pixel electrodes 122 … may be formed”), and both the common electrode block and the pixel electrode are of comb-like structures that are matched with each other (Nam Fig. 3 shows common electrode block 132 and pixel electrode 122 form comb-like structures; see also ¶ [0045]); or the metal oxide semiconductor layer is made of transparent metal oxide semiconductor material, the metal oxide semiconductor layer further comprises the pixel electrode which is a conductor, and the pixel electrode is directly connected with the drain.
Allowable Subject Matter
Claims 5, 6 and 8-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome their corresponding 35 U.S.C. § 112(b) rejection.
Regarding claim 5, no prior art of record was found to anticipate or render obvious the array substrate according to claim 4, wherein the touch metal layer is arranged between the first insulating layer and the metal oxide semiconductor layer, a second insulating layer is arranged between the touch metal layer and the metal oxide semiconductor layer, the touch metal layer further comprises a first connecting block, and the data line is electrically connected with the source through the first connecting block.
Regarding claim 6, Xue et al teaches the array substrate according to claim 4, wherein the transparent conductive layer further comprises a second connecting block (Xue ¶ [0042]: “The via connecting the source electrode 110 and the data line 400”, see also Xue Fig. 2; in view of Nam, an ordinary artisan would make this via to be part of transparent conductive layer since Nam teaches a display device, i.e., an opaque via would impede the display device from displaying correctly) and the data line is electrically connected with the source through the second connecting block (see Xue ¶ [0042]).
However, no prior art of record was found to anticipate or render obvious: wherein the touch metal layer is arranged between the first insulating layer and the metal oxide semiconductor layer, a second insulating layer is arranged between the touch metal layer and the metal oxide semiconductor layer, the touch metal layer further comprises a first connecting block, and the data line is electrically connected with the source through the first connecting block.
Regarding claims 8-14, the prior art of record generally teaches a manufacturing method of an array substrate, wherein the manufacturing method is configured for manufacturing the array according to claim 1 (see 35 U.S.C. § 103 rejection of claim 1). However, no prior art of record anticipates or render obvious a manufacturing method comprising:
forming a gate insulating layer and a second metal layer on the metal oxide semiconductor layer in sequence, forming a layer of photoresist on an upper surface of the second metal layer, and etching the second metal layer, such that the second metal layer is patterned to form a scan line and a gate electrically connected with the scan line;
using the second metal layer or the photoresist as a shelter to perform a conducting treatment to the metal oxide semiconductor layer, such that the source and the drain of the metal oxide semiconductor layer are made conductive, while the active layer of the metal oxide semiconductor layer remains as a semiconductor, the projection of the active layer on the substrate overlaps with the projection of an overlapping area between the scan line and the data line on the substrate, the projection of the gate on the substrate overlaps with the projection of the active layer on the substrate.
Conclusion
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Examiner, Art Unit 2899