DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/18/2025 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-8, 10-15 and 17-20 are rejected under 35 U.S.C. 1029(a)(1) as being anticipated by Fouquet et al. [US 2015/0356233 A1].
Regarding claims 1, 8 and 15, Fouquet et al. discloses a method / a system / an apparatus including a memory device storing instructions configured to cause one or more processing devices to perform operations (paragraphs [0004], [0088], see also Fig. 2) comprising:
simulating, by a computing system implementing off-line hotspot identification (paragraph [0088]), structures of an integrated circuit capable of being fabricated utilizing at least one lithographic mask based, at least in part, on a mask layout data describing the lithographic mask and a distribution of manufacturing parameters during fabrication (paragraph [0089]), wherein simulating the structures includes identifying different printed contours for the structures of the integrated circuit capable of being fabricated when using different manufacturing parameters within the distribution of the manufacturing parameters (paragraph [0088]-[0089]):
determining, by computing system implementing the off-line hotspot identification, edge placement errors for the different printed contours of the structures identified during the simulation (paragraph [0086] teaches edge placement errors):
generating, by computing system implementing the off-line hotspot identification, process variability bands for the structures of the integrated circuit, from the edge placement errors and the different printed contours for the structures of the integrated circuit (paragraph [0091]);
utilizing, by the computing system implementing the off-line hotspot identification, the process variability bands to identify a subset of the structures that correspond to hotspots in the integrated circuit and identify corresponding values for the manufacturing parameters associated with the identified hotspots (paragraphs [0086]-[0091]);
comparing, by a wafer testing system implementing real-time wafer assessment, measured manufacturing parameters associated with a fabricated integrated circuit to the values for the manufacturing parameters associated with the identified hotspots (paragraphs [0092]-[0093], steps 213, 214); and
dynamically identifying, by the wafer testing system implementing real-time wafer assessment, a disposition for the fabricated integrated circuit based on the comparison corresponding to one or more structures associated with the identified hotspot (paragraphs [0094]-[0095], step 216).
Regarding claims 3, 10 and 17, Fouquet et al. discloses wherein the process variability bands for the structures include outer contours, and wherein utilizing the process variability bands to identify the subset of the structures correspond to hotspots in the integrated circuit further comprises: measuring gap distances between the outer contours of the process variability bands for the structures; and identifying hotspots in the integrated circuit based on magnitudes of the gap distances between the outer contours (paragraphs [0015], [0031], [0093], [0095]).
Regarding claims 4, 11 and 18, Fouquet et al. discloses wherein the process variability bands for the structures include inner contours, and wherein utilizing the process variability bands to identify the subset of the structures correspond to hotspots in the integrated circuit further comprises: measuring overlap areas of the structures based the inner contours of the process variability bands for the structures; and identifying hotspots in the integrated circuit based on sizes of the overlap areas (paragraphs [0015], [0031], [0093], [0095]).
Regarding claims 5, 12 and 19, Fouquet et al. discloses further comprising generating, by the computing system, a lookup table storing information corresponding to the identified hotspots in the integrated circuit and the values for the manufacturing parameters associated with the identified hotspots, wherein comparing the measured manufacturing parameters to the values for the manufacturing parameters associated with the identified hotspots further comprises indexing the lookup table with the measured manufacturing parameters associated with the fabricated integrated circuit to identify the information corresponding to the identified hotspots in the integrated circuit (paragraph [0091]).
Regarding claims 6 and 13, Fouquet et al. discloses further comprising performing, by the computing system, an overlay simulation to identify a relative alignment between a plurality of the structures corresponding to different layers of the integrated circuit, wherein the identification of the subset of the structures corresponding to hotspots is based on the process variability bands and the relative alignment between the plurality of the structures corresponding to different layers of the integrated circuit (paragraph [0088]).
Regarding claims 7, 14 and 20, Fouquet et al. discloses wherein the manufacturing parameters correspond to at least one of a focus of light exposed through the lithographic mask onto the integrated circuit, an exposure dose for the light, and a relative alignment of the between the structures corresponding to different layers of the integrated circuit (paragraph [0012]).
Response to Arguments
Applicant's arguments filed 12/18/2025 have been fully considered but they are not persuasive.
Applicant argues that the applied reference does not teach “wherein simulating the structures includes identifying different printed contours for the structures of the integrated circuit capable of being fabricated when using different manufacturing parameters within the distribution of the manufacturing parameters: determining, by computing system implementing the off-line hotspot identification, edge placement errors for the different printed contours of the structures identified during the simulation: generating, by computing system implementing the off-line hotspot identification, process variability bands for the structures of the integrated circuit, from the edge placement errors and the different printed contours for the structures of the integrated circuit”, see pages 9-11 of the remarks.
The Examiner respectfully disagrees. As applied above, Fouquet et al. discloses “simulating the structures includes identifying different printed contours for the structures of the integrated circuit capable of being fabricated when using different manufacturing parameters within the distribution of the manufacturing parameters: determining, by computing system implementing the off-line hotspot identification, edge placement errors for the different printed contours of the structures identified during the simulation: generating, by computing system implementing the off-line hotspot identification, process variability bands for the structures of the integrated circuit, from the edge placement errors and the different printed contours for the structures of the integrated circuit” (paragraphs [0086]-[0091] teaches simulation for process variability bands for the structures of the integrated circuit, from the edge placement errors and the different printed contours for the structures of the integrated circuit).
As such, Applicant’s arguments are not persuasive and the rejection under 35 USC § 102 is maintained.
Conclusion
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/DEORAM PERSAUD/ Primary Examiner, Art Unit 2882