Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed on 03/05/2026 have been fully considered but they are no persuasive.
The Applicant argues that in regard to claims 1 and 17 that the combination of Cha and Bang prior art, does not teach the limitation of “a light shielding layer disposed in the second pixel region and arranged relative to a transistor in the second pixel region such that the light shielding layer overlaps at least a channel region of the transistor to block incident light from affecting operation of the channel region.”.
In response to this argument, the Examiner directs the applicant’s attention to the combination of Cha and Bang prior art, which clearly teaches the limitation of a light shielding layer (ABML) disposed in the second pixel region (DA1) and arranged relative to a transistor (T1) in the second pixel region (DA1) such that the light shielding layer (ABML) overlaps at least a channel region (A1) of the transistor (T1) to block incident light from affecting operation of the channel region (A1) (note: the material of ABML were known as a light shielding material and performing the claimed ) (see Cha, Fig.10 as shown below, ¶ [0141]- ¶ [0143], and ¶ [0149]).
In addition, during patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000). While the claims of issued patents are interpreted in light of the specification, prosecution history, prior art and other claims, this is not the mode of claim interpretation to be applied during examination. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004) (The USPTO uses a different standard for construing claims than that used by district courts; during examination the USPTO must give claims their broadest reasonable interpretation.) This means that the words of the claim must be given their plain meaning unless applicant has provided a clear definition in the specification. In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989) >; Chef America, Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1372, 69 USPQ2d 1857 (Fed. Cir. 2004).
The Examiner would further point out that “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain.” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). Therefore, the combination of Cha and Bang prior art reference does meet all the limitation in claims 1 and 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-6, 9, 12-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (U.S. 2022/0399407 A1, hereinafter refer to Cha) in view of Bang et al. (US 2021/0183983 A1, hereinafter refer to Bang).
Regarding Claim 1: Cha discloses an image display device (see Cha, Figs.1, 5, 8, and 10 as shown below and ¶ [0002]) comprising
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a plurality of pixels (PC) arranged two-dimensionally (see Cha, Figs.1, 5, 8, and 10 as shown above),
wherein the plurality of pixels (PC) includes:
a first pixel region (DA2) including a pixel (PC2) that includes a first region configured to emit light (OLED2) and a second region (BML-OP) configured to transmit visible light (see Cha, Figs.1, 5, 8, and 10 as shown above);
a second pixel region (DA1) arranged around the first pixel region (DA2), the second pixel region including a pixel configured to emit light with an area larger than a light-emitting area of the pixel in the first pixel region (see Cha, Figs.1, 5, 8, and 10 as shown above); and
a light shielding layer (ABML) disposed in the second pixel region (DA1) and arranged relative to a transistor (T1) in the second pixel region (DA1) such that the light shielding layer (ABML) overlaps at least a channel region (A1) of the transistor (T1) to block incident light from affecting operation of the channel region (A1) (note: the material of ABML were known as a light shielding material and performing the claimed ) (see Cha, Fig.10 as shown above, ¶ [0141]- ¶ [0143], and ¶ [0149]).
Cha is silent upon explicitly disclosing wherein the second pixel region including a pixel configured to emit light with an area larger than a light-emitting area of the pixel in the first pixel region.
For support see Bang, which teaches the second pixel region (DA1) including a pixel (PM) configured to emit light with an area larger than a light-emitting area of the pixel (PA) in the first pixel region (DA2) (see Bang, Figs.3, 14, 21, 22, 24, and 25 as shown below, ¶ [0236], and ¶ [0239]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Cha and Bang to enable the second pixel region including a pixel configured to emit light to have an area larger than a light-emitting area of the pixel in the first pixel region as taught by Bang in order to obtain a highly reliable display device.
Regarding Claim 4: Cha as modified teaches an image display device as set forth in claim 1 as above. The combination of Cha and Bang further teaches wherein the light shielding layer (ABML) has an area equal to or larger than an area of the channel region of the transistor (T1) (see Cha, Fig.10 as shown above).
Regarding Claim 5: Cha as modified teaches an image display device as set forth in claim 1 as above. The combination of Cha and Bang further teaches wherein the light shielding layer (ABML) is arranged so as to block light from being incident on a lightly doped drain (LDD) region arranged between the channel region (A1) and a source region of the transistor (T1) and between the channel region and a drain region of the transistor (T1), and the channel region (see Cha, Fig.10 as shown above).
Regarding Claim 6: Cha as modified teaches an image display device as set forth in claim 5 as above. The combination of Cha and Bang further teaches wherein the light shielding layer (ABML) has an area equal to or larger than a total area of the channel region of the transistor (T1) and the LDD regions on both sides of the channel region (see Cha, Fig.10 as shown above).
Regarding Claim 9: Cha as modified teaches an image display device as set forth in claim 1 as above. The combination of Cha and Bang further teaches wherein each of the plurality of pixels (PC) includes:
a light emitting element (OLED) (see Cha, Figs.5 and 10 as shown above); and
a drive transistor (T1) configured to drive the light emitting element (OLED) (see Cha, Figs.5 and 10 as shown above), and
the light shielding layer (ABML) shields the drive transistor (T1) arranged in the second region (DA1) from light (see Cha, Figs.5 and 10 as shown above).
Regarding Claim 12: Cha as modified teaches an image display device as set forth in claim 9 as above. The combination of Cha and Bang further teaches wherein an anode electrode layer (210) of the light emitting element (OLED) (see Cha, Figs.5 and 10 as shown above);
a first wiring layer (GE1) including a gate of the transistor (T1) arranged below the anode electrode layer (210) (see Cha, Figs.5 and 10 as shown above); and
a semiconductor layer (A1) including a channel region of the transistor (T1) arranged below the first wiring layer (GE1) (see Cha, Figs.5 and 10 as shown above),
wherein the light shielding layer (ABML) is arranged below the semiconductor layer (A1) to shield the channel region from light (see Cha, Figs.5 and 10 as shown above).
Regarding Claim 13: Cha as modified teaches an image display device as set forth in claim 9 as above. The combination of Cha and Bang further teaches wherein an anode electrode layer (210) of the light emitting element (OLED) (see Cha, Figs.5 and 10 as shown above);
a semiconductor layer (A1) arranged below the anode electrode layer (210) and including a channel region of the transistor (T1) arranged in the second region (DA1) (see Cha, Figs.5 and 10 as shown above); and
a first wiring layer (GE1) including a gate arranged below the semiconductor layer (A1) (see Cha, Figs.5 and 10 as shown above),
wherein the light shielding layer (ABML) is arranged below the first wiring layer (GE1) to shield the channel region from light (see Cha, Figs.5 and 10 as shown above).
Regarding Claim 14: Cha as modified teaches an image display device as set forth in claim 12 as above. The combination of Cha and Bang further teaches wherein a second wiring layer (GE3) arranged above the first wiring layer (GE1) and the semiconductor layer (A1) to shield the channel region from light (see Cha, Figs.5 and 10 as shown above).
Regarding Claim 15: Cha as modified teaches an image display device as set forth in claim 12 as above. The combination of Cha and Bang further teaches wherein the light shielding layer (ABML) has an area equal to or larger than an area of the semiconductor layer (A1) (see Cha, Figs.5 and 10 as shown above).
Regarding Claim 17: Cha discloses an electronic device (see Cha, Figs.1, 5, 8, and 10 as shown above and ¶ [0002]) comprising:
an image display device including a plurality of pixels (PC) arranged two-dimensionally (see Cha, Figs.1, 5, 8, and 10 as shown above); and
a light receiving device (20) configured to receive light incident through the image display device (see Cha, Figs.1, 5, 8, and 10 as shown above, Fig.4, and ¶ [0082]),
wherein the image display device includes the plurality of pixels (PC) arranged two-dimensionally (see Cha, Figs.1, 5, 8, and 10 as shown above), and
the plurality of pixels (PC) includes:
a first pixel region (DA2) including a pixel (PC2) that includes a first region configured to emit light (OLED2) and a second region (BML-OP) configured to transmit visible light (see Cha, Figs.1, 5, 8, and 10 as shown above);
a second pixel region (DA1) arranged around the first pixel region (DA2), the second pixel region (DA1) including a pixel (PC1) (see Cha, Figs.1, 5, 8, and 10 as shown above); and
a light shielding layer (ABML) disposed in the second pixel region (DA1) and arranged relative to a transistor (T1) in the second pixel region (DA1) such that the light shielding layer (ABML) overlaps at least a channel region (A1) of the transistor (T1) to block incident light from affecting operation of the channel region (A1) (note: the material of ABML were known as a light shielding material and performing the claimed ) (see Cha, Fig.10 as shown above, ¶ [0141]- ¶ [0143], and ¶ [0149]).
Cha is silent upon explicitly disclosing wherein the second pixel region including a pixel configured to emit light with an area larger than a light-emitting area of the pixel in the first pixel region.
For support see Bang, which teaches the second pixel region (DA1) including a pixel (PM) configured to emit light with an area larger than a light-emitting area of the pixel (PA) in the first pixel region (DA2) (see Bang, Figs.3, 14, 21, 22, 24, and 25 as shown above, ¶ [0236], and ¶ [0239]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Cha and Bang to enable the second pixel region including a pixel configured to emit light to have an area larger than a light-emitting area of the pixel in the first pixel region as taught by Bang in order to obtain a highly reliable display device.
Regarding Claim 18: Cha as modified teaches an electronic device as set forth in claim 17 as above. The combination of Cha and Bang further teaches wherein the light receiving device (20) receives light transmitted through the first pixel region (DA2) (see Cha, Figs.1, 5, 8, and 10 as shown above, Fig.4, and ¶ [0082]).
Regarding Claim 19: Cha as modified teaches an electronic device as set forth in claim 17 as above. The combination of Cha and Bang further teaches wherein a light source (OLED) configured to emit light of a predetermined wavelength that passes through the first pixel region (DA2) (see Cha, Figs.1, 5, 8, and 10 as shown above, Fig.4, and ¶ [0082]).
Regarding Claim 20: Cha as modified teaches an electronic device as set forth in claim 17 as above. The combination of Cha and Bang further teaches wherein the light receiving device (20) includes at least one of: an imaging sensor configured to photoelectrically convert light incident through the second region (see Cha, Figs.1, 5, 8, and 10 as shown above, Fig.4, and ¶ [0082]);
a distance measuring sensor configured to receive light incident through the second region to measure a distance (see Cha, Figs.1, 5, 8, and 10 as shown above, Fig.4, and ¶ [0082]); or
a temperature sensor configured to measure a temperature on a basis of light incident through the second region (see Cha, Figs.1, 5, 8, and 10 as shown above, Fig.4, and ¶ [0082]).
Claim(s) 7-8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (U.S. 2022/0399407 A1, hereinafter refer to Cha) and Bang et al. (US 2021/0183983 A1, hereinafter refer to Bang) as applied to claim 1 above, and further in view of Ke et al. (U.S. 2024/0032349 A1, hereinafter refer to Ke).
Regarding Claim 7: Cha as modified teaches an image display device as applied to claim 1 above. The combination of Cha and Bang is silent upon explicitly disclosing wherein the light shielding layer is connected to a source of the transistor and is arranged so as to cover the channel region of the transistor.
For support see Ke, which teaches wherein the light shielding layer (41/42) is connected to a source of the transistor and is arranged so as to cover the channel region of the transistor (note: the term source and drain regions of the transistor interchangeably used based on the applications) (see Ke, Fig.1 as shown below and ¶ [0080]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the combine the teachings of Cha, Bang, and Ke to enable the light shielding layer to be connected to a source of the transistor and arranged to cover the channel region of the transistor as taught by Ke in order to increase stability of the display panel.
Regarding Claim 8: Cha as modified teaches an image display device as applied to claim 1 above. The combination of Cha and Bang further teaches wherein in a case where a current flows bidirectionally between a source and a drain of the transistor (T3) arranged in the second region (see Cha, Figs.5 and 10 as shown above).
The combination of Cha and Bang is silent upon explicitly disclosing wherein the light shielding layer includes a first light shielding region having one end connected to the source and covering at least a part of the channel region of the transistor and a second light shielding region having one end connected to the drain and covering at least a part of the channel region.
For support see Ke, which teaches wherein the light shielding layer (41/42) includes a first light shielding region (41) having one end connected to the source and covering at least a part of the channel region of the transistor and a second light shielding region (42) having one end connected to the drain and covering at least a part of the channel region (note: the term source and drain regions of the transistor interchangeably used based on the applications) (see Ke, Fig.1 as shown above and ¶ [0080]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the combine the teachings of Cha, Bang, and Ke to enable the light shielding layer to include a first light shielding region having one end connected to the source and covering at least a part of the channel region of the transistor and a second light shielding region having one end connected to the drain and covering at least a part of the channel region as taught by Ke in order to increase stability of the display panel.
Regarding Claim 10: Cha as modified teaches an image display device as applied to claim 9 above. The combination of Cha and Bang further teaches wherein each of the plurality of pixels includes at least one switch transistor (T3) configured to operate in a linear region (see Cha, Figs.5 and 10 as shown above).
The combination of Cha and Bang is silent upon explicitly disclosing wherein the light shielding layer shields the switch transistor arranged in the second region from light.
For support see Ke, which teaches wherein the light shielding layer shields (42) the switch transistor (52) arranged in the second region from light (see Ke, Fig.1 as shown above and ¶ [0080]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the combine the teachings of Cha, Bang, and Ke to enable the light shielding layer to shield the switch transistor and the drive transistor arranged in the second region from light as taught by Ke in order to increase stability of the display panel.
Regarding Claim 11: Cha as modified teaches an image display device as set forth in claim 10 as above. The combination of Cha, Bang, and Ke further teaches wherein the light shielding layer (42) shields, from light, the switch transistor (52) configured to control a gate voltage of the drive transistor (51) (see Ke, Fig.1 as shown above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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