DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/2/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US 2016/0240623; hereinafter Chang) in view of Wang (US 2008/0157222; hereinafter Wang).
Regarding claim 1, Fig 1A of Chang discloses a semiconductor structure forming a plurality of transistors, the semiconductor structure comprising:
a source layer (110a; Fig 1A; ¶ [0014]);
a plurality of vertical nanowires (110b/210b; Fig 1A; ¶ [0014]) erecting vertically from the source layer (110a; Fig 1A; ¶ [0014]);
a first spacer layer (116; Fig 1A; ¶ [0033]) arranged on the source layer (110a; Fig 1A; ¶ [0014]) and around each of the plurality of vertical nanowires (110b/210b; Fig 1A; ¶ [0014]);
a gate layer (114/214; Fig 1A; ¶ [0032]) arranged on the first spacer layer (116; Fig 1A; ¶ [0033]) and around each of the plurality of vertical nanowires (110b/210b; Fig 1A; ¶ [0014]);
a second spacer layer (118b; Fig 1A; ¶ [0038]) arranged on the gate layer (114/214; Fig 1A; ¶ [0032]) and around each of the plurality of vertical nanowires;
a drain layer (110c/210c; Fig 1A; ¶ [0014]) arranged on the second spacer layer and in contact with each of the plurality of vertical nanowires;
wherein the gate layer (114/214; Fig 1A; ¶ [0032]) comprises a first gate (114; Fig 1A; ¶ [0032]) and a second gate (214; Fig 1A; ¶ [0032]) and wherein the first gate (114; Fig 1A; ¶ [0032]) is a gate of a first transistor (102; Fig 1A; ¶ [0009]) and the second gate (214; Fig 1A; ¶ [0032]) is a gate of a second transistor (202; Fig 1A; ¶ [0009]).
However Chang does not expressly disclose the first gate comprises a first interconnecting gate portion interconnecting the gate fingers of the first gate, wherein the second gate comprises a second interconnecting gate portion interconnecting the gate fingers of the second gate, wherein the plurality of gate fingers of the first gate is interleaved with the plurality of gate fingers of the second gate.
In the same field of endeavor, Fig 3 of Wang discloses a first gate comprises a first interconnecting gate portion interconnecting the gate fingers (G31a-G37a; Fig 3; ¶ [0017]), wherein the second gate comprises a second interconnecting gate portion interconnecting the gate fingers (G31b-G37b; Fig 3; ¶ [0017]) of the second gate, wherein the plurality of gate fingers of the first gate is interleaved with the plurality of gate fingers of the second gate (Fig 3).
Accordingly it would have obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the first gate comprises a first interconnecting gate portion interconnecting the gate fingers of the first gate, wherein the second gate comprises a second interconnecting gate portion interconnecting the gate fingers of the second gate, wherein the plurality of gate fingers of the first gate is interleaved with the plurality of gate fingers of the second gate as interleaved gate fingers in the arrangement of two adjacent vertical nanowire transistors would help in reducing layout area and parasitic capacitance (¶ [0002]).
Regarding claim 2, Fig 1A of Chang discloses the plurality of vertical nanowires (110b/210b; Fig 1A; ¶ [0014]) are at least 100 vertical nanowires (¶ [0013]).
Regarding claim 3, Fig 1A of Chang discloses the plurality of vertical nanowires (110b/210b; Fig 1A; ¶ [0014]) are at least 1000 vertical nanowires (¶ [0013]).
Regarding claim 4, Fig 1A of Chang discloses the drain layer comprises a first drain (110c; Fig 1A; ¶ [0014]) and a second drain (210c; Fig 1A; ¶ [0014]), wherein the first drain (110c; Fig 1A; ¶ [0014]) is a drain of the first transistor (102; Fig 1A; ¶ [0009]) and the second drain (210c; Fig 1A; ¶ [0014]) is a drain of the second transistor (202; Fig 1A; ¶ [0009]).
However Chang does not expressly disclose a first drain and a second drain each comprising a plurality of drain fingers wherein the first drain comprises a first interconnecting drain portion interconnecting the drain fingers of the first drain, wherein the second drain comprises a second interconnecting drain portion interconnecting the drain fingers of the second drain, wherein the plurality of drain fingers of the first drain is interleaved with the plurality of drain fingers of the second drain.
In the same field of endeavor, Fig 3 of Wang discloses a first drain comprises a first interconnecting drain portion interconnecting the drain fingers (D31-D34; Fig 3; ¶ [0017]), wherein the second drain comprises a second interconnecting drain portion interconnecting the drain fingers (D35-D38; Fig 3; ¶ [0017]) of the second drain, wherein the plurality of drain fingers of the first drain is interleaved with the plurality of drain fingers of the second drain (Fig 3).
Accordingly it would have obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a first drain and a second drain each comprising a plurality of drain fingers wherein the first drain comprises a first interconnecting drain portion interconnecting the drain fingers of the first drain, wherein the second drain comprises a second interconnecting drain portion interconnecting the drain fingers of the second drain, wherein the plurality of drain fingers of the first drain is interleaved with the plurality of drain fingers of the second drain as interleaved drain fingers in the arrangement of two adjacent vertical nanowire transistors would help in reducing layout area and parasitic capacitance (¶ [0002]).
Regarding claim 5, Chang in view of Wang as modified in above claims will disclose a subset of plurality of vertical nanowires (110b/210b; Fig 1A; ¶ [0014] in Chang- also compared to S31-S37 in Fig 3 of Wang) extend between each gate finger of the first gate and each drain finger of the first drain and wherein ta subset of the plurality of vertical nanowires extend between each gate finger of the second gate and each drain finger of the second drain.
Regarding claim 6, Fig 1A of Chang discloses the source layer comprises a first source (110a; Fig 1A; ¶ [0014]) and a second source (210a; Fig 1A; ¶ [0014]), wherein the first source (110a; Fig 1A; ¶ [0014]) is a source of the first transistor (102; Fig 1A; ¶ [0009]) and the second source (210a; Fig 1A; ¶ [0014]) is a source of the second transistor (202; Fig 1A; ¶ [0009]).
However Chang does not expressly disclose a first source and a second source each comprising a plurality of source fingers, wherein the plurality of source fingers of the first source is interleaved with the plurality of source fingers of the second source.
In the same field of endeavor, Fig 3 of Wang discloses a first source and a second source each comprising a plurality of source fingers (S31-S37), wherein the plurality of source fingers of the first source (S31-S32) is interleaved with the plurality of source fingers of the second source(Fig 3).
Accordingly it would have obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a a first source and a second source each comprising a plurality of source fingers, wherein the plurality of source fingers of the first source is interleaved with the plurality of source fingers of the second source in the arrangement of two adjacent vertical nanowire transistors would help in reducing layout area and parasitic capacitance (¶ [0002]).
Regarding claim 7, Chang in view of Wang as modified in above claims will disclose a subset of plurality of vertical nanowires (110b/210b; Fig 1A; ¶ [0014] in Chang- also compared to S31-S37 in Fig 3 of Wang) interconnect each source finger of the first source, each gate finger of the first gate and each drain finger of the first drain and wherein a subset of the plurality of vertical nanowires interconnect each source finger of the second source, each gate finger of the second gate and each drain finger of the second drain.
Regarding claim 8, Chang in view of Wang as modified above (Fig 3 of Wang in particular) discloses the interleaving means that the fingers of the gate (G31a/b-G37a/b; Fig 3; ¶ [0017] of Wang), drain (D31-D38; Fig 3; ¶ [0017] of Wang) of the first transistor are fitted into the space between the fingers of the gate, drain of the second transistor (Fig 3 of Wang).
Regarding claim 9, Chang in view of Wang as modified above (Fig 3 of Wang in particular) discloses the first interconnecting gate portion and the second interconnecting drain portion are vertically aligned and forming a plate capacitor (Fig 3 of Wang).
Regarding claim 10, Chang does not expressly disclose the source layer forms a common source for the first transistor and the second transistor.
In the same field of endeavor, Fig 3 of Wang discloses a source layer (Ws; Fig 3; ¶ [0020]) forms a common source for the first transistor and the second transistor.
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the source layer forms a common source for the first transistor and the second transistor such that source line can be formed which can be electrically connected to the source fingers (¶ [0020]).
Regarding claim 11, Chang does not expressly disclose the drain layer forms a common drain for the first transistor and the second transistor, wherein the source layer is electrically connected to the drain layer.
In the same field of endeavor, Fig 3 of Wang discloses a drain layer (WD1; Fig 3; ¶ [0020]) forms a common drain for the first transistor and the second transistor (Fig 3), wherein the source layer is electrically connected to the drain layer.
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the drain layer forms a common drain for the first transistor and the second transistor such that drain line can be formed which can be electrically connected to the drain fingers (¶ [0020]).
Regarding claim 12, Chang in view of Wang as modified in above claims (Fig 3 of Wang in particular) discloses the first interconnecting gate portion (Long interconnecting gate line; Fig 3 of Wang) is electrically connected to the second interconnecting drain portion, wherein the second interconnecting gate portion is electrically connected to the first interconnecting drain portion (Fig 3 of Wang).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Song et al (US 2022/0077143) Glass et al (US 2020/0357930) Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817