DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 thru 3, and 6 thru 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 111312898 A published on 6/19/20 as disclosed by the IDS filed 7/11/25. CN 111312898 A discloses (see, for example, translation of claim 1) a method for manufacturing a reservoir computing apparatus comprising providing a TiN bottom electrode layer, Al2O3 dielectric layer, Hf0.5Zr.5O2 resistive switching layer, and TiN top electrode layer. Regarding the limitation “a temperature of the annealing ranges from 300°C to 700°C, and duration of the annealing duration ranges from 30s to 100 s”, see, for example, the translation of claim 9 wherein CN 111312898 A discloses an example of annealing at a temperature 440-460 C and keeping it for 28-32 seconds, but does not expressly disclose a temperature of the annealing ranges from 300°C to 700°C, and duration of the annealing duration ranges from 30s to 100 s. It would have been obvious to one of ordinary skill in the art to have a temperature of the annealing ranges from 300°C to 700°C, and duration of the annealing duration ranges from 30s to 100 s in order to form an apparatus with good rectangularity and low leakage current, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 2, see, for example, the translation of claim 4 wherein CN 111312898 A discloses the TiN bottom electrode layer being formed by sputtering.
Regarding claim 3, see, for example, the translation of claim 1 wherein CN 111312898 A discloses TiN bottom electrode, and claim 3 wherein the translation states a thickness of 30-60 nm. CN 111312898 A does not expressly disclose a thickness of the bottom electrode layer ranges from 15 nm to 300 nm; however, it would have been obvious to one of ordinary skill in the art to have a thickness of the bottom electrode layer ranges from 15 nm to 300 nm in order to maintain device stability while having low leakage current, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 6, see, for example, the translation of claim 4 wherein CN 111312898 A discloses the Hf0.5Zr.5O2 resistive switching layer being formed by atomic layer deposition.
Regarding claim 7, see, for example, the translation of claim 4 wherein CN 111312898 A discloses the Hf.5Zr.5O2 film. CN 111312898 A does not disclose a thickness of the resistive switching layer ranging from 2.5 nm to 6 nm; however, it would have been obvious to one of ordinary skill in the art to have a thickness of the resistive switching layer ranging from 2.5 nm to 6 nm in order to improve scalability with reduced power consumption, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 8, see, for example, the translation of claim 4 wherein CN 111312898 A discloses the TiN top electrode being formed by sputtering.
Regarding claim 9, see, for example, the translation of claim 3 wherein CN 111312898 A discloses the TiN top electrode having a thickness between 5-60 nm. It would have been obvious to one of ordinary skill in the art to have a thickness of the top electrode layer ranges from 20 nm to 60 nm in order to maintain device stability while having low leakage current, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 1 thru 6, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. US 2014/0264231 A1. Wang discloses (see, for example, FIG. 3) a method for manufacturing a reservoir computing apparatus comprising providing a bottom electrode layer 302, dielectric layer 304, resistive switching layer 306, and top electrode layer 308. Regarding the limitation “a temperature of the annealing ranges from 300°C to 700°C, and duration of the annealing duration ranges from 30s to 100 s”, see, for example, FIG. 4 wherein Wang discloses anneal stack 410, and then in paragraph [0086], Wang further discloses an example of 500 to 800 C for between 30 seconds and 60 minutes, but does not expressly disclose a temperature of the annealing ranges from 300°C to 700°C, and duration of the annealing duration ranges from 30s to 100 s. It would have been obvious to one of ordinary skill in the art to have a temperature of the annealing ranges from 300°C to 700°C, and duration of the annealing duration ranges from 30s to 100 s in order to form an apparatus with good rectangularity and low leakage current, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 2, see, for example, paragraph [0070] wherein Wang discloses the bottom electrode layer 302 being formed by ALD, i.e. a type of chemical vapor deposition.
Regarding claim 3, see, for example, paragraph [0070] wherein Wang discloses the bottom electrode layer 302 being polysilicon, i.e. polycrystalline silicon, titanium nitride, etc. Wang does not expressly disclose a thickness of the bottom electrode layer ranges from 15 nm to 300 nm; however, it would have been obvious to one of ordinary skill in the art to have a thickness of the bottom electrode layer ranges from 15 nm to 300 nm in order to maintain device stability while having low leakage current, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 4, see, for example, paragraph [0084] wherein Wang discloses the dielectric layer 304 being formed by sputtering.
Regarding claim 5, see, for example, paragraph [0060] wherein Wang discloses the dielectric layer 304 being made of TiO2.
Regarding claim 6, see, for example, paragraph [0070] wherein Wang discloses the resistive switching layer 306 being formed by ALD, i.e. atomic layer deposition.
Regarding claim 9, see, for example, paragraph [0067] wherein Wang discloses the top electrode layer 308 being TiN, i.e. atomic layer deposition. Wang does not disclose a thickness of the tope electrode layer ranging from 20 nm to 60 nm; however, it would have been obvious to one of ordinary skill in the art to have a thickness of the top electrode layer ranges from 20 nm to 60 nm in order to maintain device stability while having low leakage current, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 10, see, for example, paragraph [0086] wherein Wang further discloses an example of 500 to 800 C for between 30 seconds and 60 minutes.
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Eugene Lee
January 13, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815