DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election, without traverse, of Group I: claims 1-10, in the “Response to Election / Restrict. ion Filed - 07/09/2026”, is acknowledged.
This office action considers claims 1-16 are thus pending for prosecution, of which, non-elected claims 11-16 are withdrawn, and elected claims 1-10 are examined on their merits.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as SBD; Fig 1; [0064]) or C 1, L 13-14)= (element SBD; Figure No. 1; Paragraph No. [0064]) or Column No 1, Line Nos. 13-14. For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference, in this case Takeda, citation may not be preceded by the inventor tag, wherein the other reference citation, for example Takeshi and like, will carry inventor tag. These conventions are used throughout this document.
Claims 1-2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over to Takeda; Hiroshi et al. (US 20140084386 A1) hereinafter Takeda, and Takeshi Tonegawa et al. (JP 2014078631 A) hereinafter Takeshi.
Regarding Claim 1. Takeda teaches a Schottky barrier diode (SBD; Fig 1; [0064]: first contact CON1, the second impurity region CS, and the second low-concentration impurity region AND form a Schottky barrier diode SBD), comprising: (see the entire document, Fig 1, along with other figures referenced subject matter for details, specifically, as cited below):
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Takeda Figure 1
a silicon layer (an n-type "second low-concentration impurity region that is formed on the surface of an n-type "substrate SUB" composed of silicon; Fig 1; [0063]); and
a silicide layer ( SIL 6; fig 6; [0068]) that is disposed on the silicon layer and contains Pt and Ni (composed of NiPtSi or the like [0071]),
but, Takeda does not expressly disclose: “wherein a peak value of a concentration of Pt in the silicide layer with a thickness of 50 nm on the silicide layer side from an interface between the silicide layer and the silicon layer, or a peak value of the concentration of Pt in the silicide layer in a case where the thickness of the silicide layer is less than 50 nm is 1 at % to 60 at %”.
However, in the analogous art, Takeshi discloses a semiconductor device having metal material constituting nickel silicide to which platinum (Pt) is added. i.e., Pt-containing Ni silicide (Ni (1-x) Ptx) Si) (0.01 <x <0.2) whose main component is Ni. and the layer thickness of the "source-drain silicide layer DS1" is 10 nm to 30 nm inclusive.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate composition and thickness property of Takeshi into Takeda and thereafter the combination of (Takeshi and Takeda) comprises wherein a peak value of a concentration of Pt in the silicide layer with a thickness of 50 nm on the silicide layer side from an interface between the silicide layer and the silicon layer, or a peak value of the concentration of Pt in the silicide layer in a case where the thickness of the silicide layer is less than 50 nm is 1 at % to 60 at %”,, since this modification, at least, because of advantages such as the resistance of the fine gate and source / drain regions being stabilized; and improve the operation speed of the semiconductor device (Takeshi),
Regarding Claim 2. the combination of (Takeshi and Takeda) as applied to Schottky barrier diode according to claim 1, further teaches; (the SBD) further comprising:
a PtNi alloy layer or a mixed layer of Pt and Ni disposed on the silicide layer (a silicide layer (SIL 6; fig 6; [0068] that is disposed on the silicon layer and contains Pt and Ni i.e., composed of NiPtSi or the like [0071]),
Regarding Claim 6. the combination of (Takeshi and Takeda) as applied to Schottky barrier diode according to claim 1, further teaches; wherein a Ti layer (obvious from [0074]: the "second contact CON 2" is connected to the "second low-concentration impurity region AND" via the "silicide layer SIL 6" and a "barrier metal BM" that is obtained by laminating a Ti layer and a TiN layer in the stated order) (or a Mo layer is) disposed on the silicide layer.
Claims 3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over to Takeda; Hiroshi et al. (US 20140084386 A1) hereinafter Takeda, and Takeshi Tonegawa et al. (JP 2014078631 A) hereinafter Takeshi, in further view of Huang; Chih-Tsung et al. US 20100258899 A1) hereinafter Huang.
Regarding Claim 3. the combination of (Takeshi and Takeda) as applied to the Schottky barrier diode according to claim 1, does not expressly disclose; (the SBD) further further comprising:
a guard ring that is located at an end of the silicide layer and is disposed inside the silicon layer.
However, in the analogous art, Huang discloses a Schottky diode device with an extended guard ring ([0002]), wherein ([0010]) the Schottky diode device including a silicon substrate; growing an epitaxial silicon layer on the silicon substrate; a guard ring in the epitaxial silicon layer; the guard ring, the epitaxial silicon layer and the silicon substrate to form an annular trench; a silicide layer on the epitaxial silicon layer; and forming a conductive layer on the silicide layer..
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to contemplate Chen’s teaching into the combination of (Takeshi and Takeda) and thereafter, the combination of (Takeshi,Takeda and Huang) comprises a guard ring that is located at an end of the silicide layer and is disposed inside the silicon layer, since this inclusion, at least, provides can completely solve the leakage problem resulting from the abrupt P-N junction 230a (Huang [0020]),
Regarding Claim 9. the combination of (Takeshi and Takeda) as applied to the Schottky barrier diode according to claim 1, does not expressly disclose wherein the silicon layer is an epitaxial layer, and a silicon substrate is disposed below the epitaxial layer.
However, in the analogous art, Huang discloses a Schottky diode device with an extended guard ring ([0002]), wherein ([0010]) the Schottky diode device including a silicon substrate; growing an epitaxial silicon layer on the silicon substrate; a guard ring in the epitaxial silicon layer; the guard ring, the epitaxial silicon layer and the silicon substrate to form an annular trench; a silicide layer on the epitaxial silicon layer; and forming a conductive layer on the silicide layer..
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to contemplate Chen’s teaching into the combination of (Takeshi and Takeda) and thereafter, the combination of (Takeshi,Takeda and Huang) comprises the silicon layer is an epitaxial layer, and a silicon substrate is disposed below the epitaxial layer, since this inclusion, at least, provides isolation of the epitaxial layer from bulk substrate and thus removes impurity.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over to Takeda; Hiroshi et al. (US 20140084386 A1) hereinafter Takeda, and Takeshi Tonegawa et al. (JP 2014078631 A) hereinafter Takeshi, in further view of Wu, Shye-Lin US 20050230744 A1) hereinafter Wu’744.
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Regarding Claim 4. the combination of (Takeshi and Takeda) as applied to Schottky barrier diode according to claim 1, does not expressly disclose further comprising:
a groove that is formed in the silicon layer and is located below the silicide layer;
an insulator layer disposed on an inner wall of the groove; and
a conductor layer that is disposed inside the groove and on the insulator layer,
wherein the silicon layer is disposed adjacent to the groove.
However, in the analogous art, Wu’744 discloses a Schottky Barrier Diode (title), wherein (Fig 3F)
a groove (135; Fig 3B; [0040]) that is formed in the silicon layer (101) and is located below the silicide layer (165; Fig 3F; [0045]);
an insulator layer (125; [0041]) disposed on an inner wall of the groove; and
a conductor layer (145; [0041]) that is disposed inside the groove and on the insulator layer,
wherein the silicon layer (101) is disposed adjacent to the groove ..
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to contemplate Wu’744’s teaching into the combination of (Takeshi and Takeda) and thereafter, the combination of (Takeshi,Takeda and Wu’744) comprises groove structure as claimed, since this inclusion, at least, provides a high switching speed (Wu [0001]) by reducing reverse leakage current, and improve breakdown voltage, and reduce minority current while forward biase,
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over to Takeda; Hiroshi et al. (US 20140084386 A1) hereinafter Takeda, and Takeshi Tonegawa et al. (JP 2014078631 A) hereinafter Takeshi, in further view of NAGATA; Toshio US 20220181447 A1) hereinafter Nagata.
Regarding Claim 5-8. the combination of (Takeshi and Takeda) as applied to the Schottky barrier diode according to claim 1, does not expressly disclose wherein:
For claim 5: a Ti layer is disposed on the silicide layer, and a Mo layer is disposed on the Ti layer.
For claim 6: a Ti layer or a Mo layer is disposed on the silicide layer.
For claim 7: a Ti layer is disposed on the silicide layer, and a Mo layer is disposed on the Ti layer.
For claim 8: a laminated film disposed on the silicide layer,
wherein the laminated film is a film in which at least two films among an Al film, a Ni film, and a Mo film are laminated.
However, in the analogous art, Huang discloses an SBD (Schottky barrier diode) ([0059]), wherein (Figs 5A, 5B; [0071-0074]) a Ti layer is disposed on the silicide layer, and a Mo layer is disposed on the Ti layer; and/or wherein the laminated film is a film in which at least two films among an Al film, a Ni film, and a Mo film are laminated. Huang further discloses in [0139] the second main surface of silicide layer 38 may include at least one among the Ti layer 33.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to contemplate Nagata’s teaching into the combination of (Takeshi and Takeda) and thereafter, the combination of (Takeshi,Takeda and Nagata) comprises the features as claimed in claims 5-8, since this modification, at least, provides relaxation for chips structure accommodating SBD (Nagata [0071]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over to Takeda; Hiroshi et al. (US 20140084386 A1) hereinafter Takeda, and Takeshi Tonegawa et al. (JP 2014078631 A) hereinafter Takeshi, in further view of Hokazono; Akira et al. (US 9437735 B1) hereinafter Hokazono.
Regarding Claim 10. the combination of (Takeshi and Takeda) as applied to Schottky barrier diode according to claim 1, does not expressly disclose; wherein the peak value of the concentration of Pt occurs at the interface or on the interface side in the silicide layer.
However, in the analogous art, Hokazono discloses a Schottky barrier junction in a a tunnel FET (C 1, L 11-12) , wherein (fig. 4; C 3, L 38-54) the Schottky barrier height (hereinafter referred to as "SBH") on the drain side can be controlled by the amount of Pt added to NiSi, and the more Pt is added, the higher the SBH becomes.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to contemplate teaching of Hokazono into the combination of (Takeshi and Takeda), and thus increased the Pt concentration of the "silicide layer" on the side thereof at the interface with the "second low-concentration impurity region" on the basis of said disclosures and arrives at the invention as in claim 10, since inclusion, at least, makes differences in the SBH in FIG. 5 can be controlled by the amount of Pt added to NiSi, for example, and the more Pt is added, the higher the SBH becomes (Hokazono C 3, L 35-54).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
August 6, 2026
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