DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Application 18/560,100 filed on 11/10/2023 with Preliminary Amendment. Claims 1-12 are pending in the office action.
Claims 7-10 have been amended.
Claims 11-12 are newly added.
Claim Objections
Claim 2 is objected to because of the following informalities:
As per claim 2, line 2: replace “the mothed further” with -- the method further --.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
As per claims 1-12: the claim invention is directed to a mathematical concept without significantly more.
As per claim 1:
Step 1: claim 1 is directed to “a method” which is considered as “a process”. Thus, claim 1 falls into four categories statutory of invention (Step 1: YES).
Step 2A Prong One Analysis:
Claim 1 is broadest interpretation to describe a mathematical concept, such as:
The step “establishing an impedance model for a DC loop of a high-voltage direct current (HVDC) system” that establishes a mathematical formula/concept (i.e., an impedance model) of an electrical circuit/system (as data information)).
The following step “scanning parameters in the HVDC system based on the impedance model, to obtain a feasible region of each of the parameters” which is gathering data information (scanned parameters) or assign mathematical variable of the mathematical formula/concept (i.e., an impedance model).
The next step “substituting, for each of the parameters, the parameter in the feasible region into a DC loop impedance equation, to obtain an impedance corresponding to the parameter, the DC loop impedance equation being obtained by transforming the impedance model” which is a mathematical solving process step with different values of variables/parameters (i.e., substitute parameters) of the mathematical formula/equation (i.e., a DC loop impedance equation (also see claim 6)).
The last step “comparing, for each of the parameters, the impedance corresponding to the parameter with a target impedance value, and determining the impedance that meets the target impedance value and the parameter corresponding to the impedance as an optimal impedance and an optimal parameter of the DC loop” which is also a mathematical concept step, such as “compare with a target (impedance) value” and validating the output value being calculated from the mathematical process step.
As above analysis, claim 1 is directed to a mathematical process which is a judicial exception (step 2A, Prong One: YES)
Step 2A Prong Two Analysis:
Claim 1 does/do not recited (1) additional element in the claim beyond the judicial exception, and (2) evaluating those addition elements individual or combination to determine whether the claim as a whole integrates the exception into a practical application. See MPEP 2106.04(d). The claim itself does not include additional element either from claim language, specification, and drawings. The claim list the step of mathematical concept and maybe solving the mathematical problem by using pencil and paper, or by a generic computer.
The step “scanning parameters” using “a scanning unit” (see Application specification, paragraph [0024] [0090] [0092]), but nothing more than labeling “a scanning unit”. However, the Application specification, paragraph [0055], described “all key parameters of the HVDC system are scanned by using the state space equation in step 101 (also see the state space equation in claim 5), and the feasible region of each of the key parameters is determined by using an eigenvalue method or impedance analysis method. The feasible regions are used as value ranges of respective parameters in subsequent DC loop impedance optimization”.
Furthermore, as taking figure 3 into account, establishing unit 301, scanning unit 302, calculation unit 303, and comparison unit 304 are nothing more than conventional calculator or a genetic computer.
Hence, There is no additional element in the claim beyond the judicial exception (Step 2A, Prong two analysis: No).
Step 2B analysis:
Claim 1 purely a processing solving mathematical concept/equation without include additional elements and insufficient extra-solution activity which do not provide an inventive concepted (Step 2B: NO).
Thus, claim 1, is not eligibility subject matter under 35 U.S.C 101.
As per claims 2-6 are further mathematical concept from claim 1. There are still a mathematical concept and insignificant extra-solution which do not provide an inventive concepted.
As per claims 7-12: recited to a system as a computer device, but nothing more than “a generic computer” for performing a mathematical concept as per claims 1-6. Hence, claims 7-12 are also rejected as similar above analysis. Hence, claims 7-12 are not eligibility subject matter under 35 U.S.C 101.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 7, and 10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yin et al., (Impedance-Based Stability Analysis and Stabilization Control Strategy of MMC-HVDC Considering Complete Control Loops, IEEE Access, August 4, 2020, Vol. 8, pages 142900 -142915).
As per claims 1 and 7: Yin discloses a method and computer system for determining a direct current (DC) loop impedance (Yin, the abstract, optimal design method and page 142901, col. 1, “PC system for computation”), comprising:
establishing an impedance model for a DC loop of a high-voltage direct current (HVDC) system (Yin, the abstract, modular multilevel converter-based high-voltage DC (MMC-HVDC) and impedance model, page 142901, col. 2, “an accurate impedance model of MMC is established with consideration of power outer-loop control”; page 142909, V. Statbility Analysis and Stabilization Control Strategy, A. Stability Analysis, col. 1, “MMC operating in power outer-loop and current inner-loop control model”, fig. 12-13, DC loop in MCC that connected to grid);
scanning parameters in the HVDC system based on the impedance model, to obtain a feasible region of each of the parameters (Yin, the abstract, “controller parameters”, page 1420901, col. 2, “based on this impedance model, the influence of parameters in different control loops and time delay on impedance characteristics are analyzed” and also see table 2: parameters of MMC-HVDC);
substituting, for each of the parameters, the parameter in the feasible region into a DC loop impedance equation, to obtain an impedance corresponding to the parameter, the DC loop impedance equation being obtained by transforming the impedance model (Yin, page 142911, adjusting the control parameters of PQR can change the MMC impedance, thus change the phase margin at the impedance intersection to improve the system stability); and
comparing, for each of the parameters, the impedance corresponding to the parameter with a target impedance value, and determining the impedance that meets the target impedance value and the parameter corresponding to the impedance as an optimal impedance and an optimal parameter of the DC loop (Yin, page 142911-142912, fig. 21-23, col. 2, optimal parameters of QPR controller are selected and also see Simulation Results).
As per claims 4 and 10: Yin discloses wherein the scanning parameters in the HVDC system based on the impedance model, to obtain a feasible region of each of the parameters comprises: scanning, by using an eigenvalue analysis method or impendence analysis method, the parameters in the HVDC system based on the impedance model, to obtain the feasible region of each of the parameters (Yin, page 142907, col. 1, C. Analysis of controller Parameters, the influence of parameters of current loop controller).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al., (Impedance-Based Stability Analysis and Stabilization Control Strategy of MMC-HVDC Considering Complete Control Loops, IEEE Access, August 4, 2020, Vol. 8, pages 142900 -142915) in view of Trinh et al., (Generic Model of MMC-VSC-HVDC for Interaction Study with AC Power System, IEEE, January 2016, Vol. 13, pages 27-34).
As per claims 2 and 8: Yin does not teach selecting the parameters in the HVDC system by using a particle algorithm or a genetic evolutionary algorithm.
Trinh teaches developing a generic rms model of a MMC-VSC-HVDC (Trinh, page 31, col. 1, V. Generic RMS Model Identification) using parameter identification Algorithm (Trinh, page 31, col. 2, A. Parameter Identification Algorithm).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine Trinh and Yen using Trinh’s generic RSM model with identified parameters to prove the good dynamic performances of the proposed generic RSM model (Trinh, pages. 33, col. 2, VII. Conclusion).
Claim(s) 3, 5, 9, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al., (Impedance-Based Stability Analysis and Stabilization Control Strategy of MMC-HVDC Considering Complete Control Loops, IEEE Access, August 4, 2020, Vol. 8, pages 142900 -142915) in view of Tyagi et al., (State Space Modeling of High Gain DC-DC Boost Converter with Coupling Inductor, IJERT, January, 2014, Vol. 3, pages 2945-2949).
As per claims 3, 5, 9, and 11: Yin does not teach establishing a state space equation associated with a primary system and a secondary control system of the HVDC system based on a structure of the HVDC system.
Tyagi teaches the state space modeling techniques is used to model the High gain DC-DC boost converter includes primary and secondary control system (Tyagi’s fig. 1-2) with different operation modes corresponding to different state space equations
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(Tyagi, page 2948, col. 1 and col. 2, standard state space form/equation for mode 1 and mode 2).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine Tyagi and Yin using Tyagi’s state space equation can be used for analyzing the system performance and development of controller for stability studies, thus derivation of state space models of high gain DC-DC boost converter topology helps in analyzing circuits with ease (Tyagi’s, pages 2949, col. 1, V. Conclusion).
Claim(s) 6 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al., (Impedance-Based Stability Analysis and Stabilization Control Strategy of MMC-HVDC Considering Complete Control Loops, IEEE Access, August 4, 2020, Vol. 8, pages 142900 -142915) in view of Agbemuko et al., (Impedance-Based Modeling of Hybrid AC/DC Grid with Synchronous Generator for Interaction Study and Dynamic Improvement, ScienceDirect, November 16, 2019, pages 1-11).
Yin does not teach the DC loop impedance equation of claim 6 and 12.
Agbermuko teaches wherein the DC loop impedance equation is expressed as:
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wherein s represents a Laplacian operator, A represents a state matrix of the HVDC system, and B represents an input matrix of the HVDC system.
(Agbermuko, page 2, col. 1- col. 2, 2. Impedance-modeling of Subsystem, see equation (2).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine Agbermuko and Yin using Agbermuko’s DC loop impedance equation using Laplace domain to derives the impedance models for all identified subsystem in the grid (Agbermuko, page 2, col. 1).
Conclusion
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/ Primary Examiner, Art Unit 2851
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