Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-15 are cancelled.
Claims 16-41 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation "the lateral device" in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim. As understood by the examiner, the recited element should be “the lateral transistor device”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-21 and 23-34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2016/0268423 A1 Koepp et al (herein “Koepp”).
Regarding Claim 16, Koepp discloses:
A semiconductor die (#2, see top down view in Fig. 4A comprising semiconductor devices (semiconductor bodies) #1 and #3), comprising:
a vertical power transistor (#35, Figs. 4A and 4B, [0057]-[0058], cross sectional view shown in Fig. 4B) device having a source region (#401) and a drain region (#409) at opposite sides of a semiconductor body (#3);
a lateral transistor device (#5, Figs. 8A-8C, [0075]-[0080], cross sectional view shown in Fig. 8A) having a body region (space occupied by lateral transistor #5) with a lateral channel region (not explicitly labelled, see [0076]: “The transistor 5 comprises a source region 201, a drain region 205, a channel region, a drift zone and a gate electrode 210 adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface.”), and a source region (#201) and a drain region (#205) formed at a frontside of the semiconductor body (top side with respect to Fig. 8A); and
a deep trench (#292, #293, #393, Figs. 1, 4A, and 8B, [0037], [0041], [0057], [0063]-[0065], and [0078]) arranged laterally between the vertical power transistor device and the lateral transistor device (see top down view in Fig. 4B), wherein the deep trench (#292, #293, #393) forms a deep trench isolation (see cross sectional views in Figs. 4B and 8A).
Regarding Claim 17, Koepp discloses: The semiconductor die of claim 16, further comprising:
a shielding field electrode region (#250) with a shielding field electrode (#270) formed in a shielding field electrode trench (#214, Fig. 8B, [0076]) in the semiconductor body (#1),
wherein at least a portion of the lateral transistor device (#5) is arranged vertically above the shielding field electrode region (see cross sectional view in Fig. 8A, gate electrode #210 is vertically above portion #270 of field plate #250).
Regarding Claim 18, Koepp discloses: The semiconductor die of claim 17,
the vertical power transistor device (#3, Fig. 4B) comprises a field electrode region (region defined by space occupied by gate dielectric layer #407) with a field electrode (#405) formed in a field electrode trench (trench defined by space occupied by gate dielectric layer #407), and wherein the field electrode trench of the vertical power transistor device (#3) and the shielding field electrode trench (#250) differ from each other in at least one of vertical depth and lateral width (see Figs. 4B and 8A).
Regarding Claim 19, Koepp discloses: The semiconductor die of claim 17,
wherein a contact region (rightmost portion of #250, i.e. portion that makes electrical contact with #252 in Fig. 8A) of the shielding field electrode (#250) extends laterally aside the channel region (#220, Fig. 4A) of the lateral transistor device (#5) and vertically up to the frontside of the semiconductor body (#1).
Note, emphasis added, see 112(b) antecedent basis rejection above.
Regarding Claim 20, Koepp discloses: The semiconductor die of claim 17,
wherein a gate electrode (#210) of the lateral transistor device (#5) is arranged in a trench ([0076]) laterally aside the channel region (#220) of the lateral transistor device (#5).
Regarding Claim 21, Koepp discloses: The semiconductor die of claim 20,
wherein the gate electrode (#210) of the lateral transistor device (#5) is arranged above the shielding field electrode (#250) in the shielding field electrode trench (#214, Fig. 8B, [0076]).
Regarding Claim 23, Koepp discloses: The semiconductor die of claim 20,
wherein the lateral channel region (#220) is offset downwards (see Fig. 8A) into the semiconductor body (#1).
Regarding Claim 24, Koepp discloses: The semiconductor die of claim 23, further comprising:
a surface channel blocker region (#280a), which is made of a same conductivity type as the body region ([0039]) of the lateral transistor device (#5) but with a higher doping concentration (“heavily doped” [0059]),
formed above the body region (space occupied by lateral transistor #5) of the lateral transistor device (#5).
Regarding Claim 25, Koepp discloses: The semiconductor die of claim 20,
wherein a lateral field electrode (#250) of the lateral transistor device (#5) is arranged aside the drift region (#260) of the lateral transistor device (#5) with respect to a first lateral direction, and aside the gate electrode (#210) of the lateral transistor device (#5) with respect to a second lateral direction, in the same trench (#214) with the gate electrode (#210).
Regarding Claim 26, Koepp discloses: The semiconductor die of claim 16,
wherein the source region (#201) and/or the drain region (#205) of the lateral transistor device (#5) comprises a surface implant with a higher doping concentration ([0035]) compared to a body region (see Fig. 4B, includes elements in gate trench #310) of the vertical power transistor device (#3).
Regarding Claim 27, Koepp discloses: The semiconductor die of claim 16, further comprising:
a source contact (#202) electrically contacting the source region (#201) of the lateral transistor device (#5) and vertically extending through the source region (#201) down into the body region (space occupied by lateral transistor #5) of the lateral transistor device (#5), wherein the source contact (#202) forms a body contact (#281, Fig. 8A).
Regarding Claim 28, Koepp discloses: The semiconductor die of claim 16,
wherein a gate electrode (#210) of the lateral transistor device (#5) is arranged in a trench (#214) laterally aside the channel region (#220, see top-down view in Fig. 8B) of the lateral transistor device (#5).
Regarding Claim 29, Koepp discloses: The semiconductor die of claim 16,
wherein the lateral transistor device (#5) comprises a lateral drift region (#260) which is arranged laterally between the lateral channel region (#220) and the drain region (#205) of the lateral transistor device (#5), and wherein the drift region (#260) is made of a same conductivity type as the drain region (#205) but with a lower doping concentration ([0035]).
Regarding Claim 30, Koepp discloses:
A method of manufacturing a semiconductor die (#2, see top down view in Fig. 4A comprising semiconductor devices (semiconductor bodies) #1 and #3), the method comprising:
Forming a vertical power transistor (#35, Figs. 4A and 4B, [0057]-[0058], cross sectional view shown in Fig. 4B) device having a source region (#401) and a drain region (#409) at opposite sides of a semiconductor body (#3);
forming a lateral transistor device (#5, Figs. 8A-8C, [0075]-[0080], cross sectional view shown in Fig. 8A) having a body region (space occupied by lateral transistor #5) with a lateral channel region (not explicitly labelled, see [0076]: “The transistor 5 comprises a source region 201, a drain region 205, a channel region, a drift zone and a gate electrode 210 adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface.”), and a source region (#201) and a drain region (#205) formed at a frontside of the semiconductor body (top side with respect to Fig. 8A);
etching a deep trench (#292, #293, #393, Figs. 1, 4A, and 8B, [0037], [0041], [0057], [0063]-[0065], and [0078], specifically [0064] discloses etching step) laterally between the vertical power transistor device and the lateral transistor device (see top down view in Fig. 4B);
and filling the deep trench (#292, #293, #393) to form a deep trench isolation (see cross sectional views in Figs. 4B and 8A).
Regarding Claim 31, Koepp discloses: The method of claim 30,
wherein forming the lateral transistor device (#5) comprises:
implanting a dopant ([0039]) obliquely via a sidewall of the deep trench (#292, #293, #393) into the semiconductor body to form the body region (space occupied by lateral transistor #5) of the lateral transistor device (#5).
Regarding Claim 32, Koepp discloses:
A semiconductor device, comprising: a semiconductor body (#2, see top down view in Fig. 4A comprising semiconductor devices (semiconductor bodies) #1 and #3);
a first transistor device (#35) having a source region (#401) and a drain region (#409) at opposite sides of the semiconductor body (#2), the first transistor device () being a vertical power transistor device (#35, Figs. 4A and 4B, [0057]-[0058], cross sectional view shown in Fig. 4B);
a second transistor device (#5, Figs. 8A-8C, [0075]-[0080], cross sectional view shown in Fig. 8A) having a source region (#201) and a drain region (#205) formed at a frontside of the semiconductor body (top side with respect to Fig. 8A); and
a deep trench (#292, #293, #393, Figs. 1, 4A, and 8B, [0037], [0041], [0057], [0063]-[0065], and [0078]) arranged laterally between the first transistor device and the second transistor device (see top down view in Fig. 4B), wherein the deep trench (#292, #293, #393) forms a deep trench isolation (see cross sectional views in Figs. 4B and 8A).
Regarding Claim 33, Koepp discloses: The semiconductor device of claim 32,
wherein the first transistor device (#35) comprises a plurality of first trenches (#310, Fig. 4B, [0057]), each of the first trenches having a field plate (#405) and a gate electrode (#403) formed therein.
Regarding Claim 34, Koepp discloses: The semiconductor device of claim 33,
wherein the second transistor device (#5) comprises a plurality of second trenches (#214), each of the second trenches having a field plate (#250) and a gate electrode (#210) formed therein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0268423 A1 Koepp et al in view of US 2020/0235237 A1 Qian (herein “Qian”).
Regarding Claim 22, Koepp discloses: The semiconductor die of claim 20.
Koepp does not explicitly disclose:
further comprising:
a counterdoping layer disposed laterally between the body region and a gate dielectric of the lateral transistor device,
wherein the counterdoping layer is made of an opposite conductivity type compared to the body region of the lateral transistor device.
However, in analogous art, Qian teaches:
See Fig. 1A and [0010]-[0018].
a counterdoping layer (#103, second conductivity type well 103, [0012]) disposed laterally between the body region (#102, first conductivity type drift region, [0011]) and a gate dielectric (#105, [0011]) of the lateral transistor device (device shown in Fig. 1A),
wherein the counterdoping layer (#103) is made of an opposite conductivity type compared to the body region (#102) of the lateral transistor device.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Qian to the device disclosed by Koepp and include a layer of opposite conductivity type adjacent to the body region of the lateral transistor device. Doing so would improve the reliability of the device and expand the safe working range of the device [0114], and additionally allow adjustment of the device threshold voltage for specific applications.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0268423 A1 Koepp et al
Regarding Claim 35, Koepp discloses: The semiconductor device of claim 34,
wherein the plurality of first trenches (#310) and the plurality of second trenches (#214) extend from the frontside (top side) of the semiconductor body (#2) along a first direction into the semiconductor body (#2),
Koepp does not explicitly disclose:
wherein the plurality of first trenches and the plurality of second trenches have a same depth.
Koepp is silent regarding the depths of the first and second trenches in relation to one another. However, the person of ordinary skill having the benefit of Koepp would be motivated to make all trenches the same depth to simplify processing absent any teaching to the contrary. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider forming the first and second trenches to have the same depth in order to simplify the manufacturing process as to form the first and second trenches in a similar manner during the same manufacturing step, thus resulting in the first and second trenches having the same depth.
Allowable Subject Matter
Claims 36-41 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 36: The following is a statement of reasons for the indication of allowable subject matter: The prior art of record as considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations. The prior art fails to teach or suggest the claimed limitations, namely: “wherein upper surfaces of the field plates within the plurality of first trenches and upper surfaces of the field plates within the plurality of second trenches are horizontally aligned.”
Regarding Claim 36: The following is a statement of reasons for the indication of allowable subject matter: Claims 37-41 either directly or indirectly depend on objected to but allowable claim 36, and are also objected to but allowable for at least the same reasons as claim 36, see above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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