Response to Amendment
The amendment filed 0611/2026 has been accepted and entered.
Response to Arguments
Applicant’s amendments to independent claims 16 and 30, and their respective dependent claims, see pages 9-10 of Applicant’s remarks filed 06/11/2026, with respect to the 35 U.S.C. 102 and 103 rejections of claims 16-35 have been fully considered and are persuasive. Koepp (with respect to independent claims 16 and 30) does not teach all of the limitations of amended independent claims 16 and 30 (i.e. having a deep trench that completely intersects the semiconductor body) and thus and its respective dependent claims.
In view of the amendments, a new reference has been applied (new reference includes US 2018/0204838 A1 Hsu et al, see below).
Claims 16-21 and 23-31 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0268423 A1 Koepp et al in view of US 2018/0204838 A1 Hsu et al.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0268423 A1 Koepp et al in view of US 2018/0204838 A1 Hsu et al and further in view of US 2020/0235237 A1 Qian.
Status of Claims
Claims 1-15, 33-34, and 36 are cancelled.
Claims 16-32, 35, and 37-41 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 16-21 and 23-31 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0268423 A1 Koepp et al (herein “Koepp”) in view of US 2018/0204838 A1 Hsu et al (herein “Hsu”).
Regarding Claim 16, Koepp discloses:
A semiconductor die (#2, see top down view in Fig. 4A comprising semiconductor devices (semiconductor bodies) #1 and #3), comprising:
a vertical power transistor (#35, Figs. 4A and 4B, [0057]-[0058], cross sectional view shown in Fig. 4B) device having a source region (#401) at a frontside (top side of Fig. 4B) of a semiconductor body (#3) and a drain region (#409) at a backside (bottom side of Fig. 4B) of the semiconductor body (#3) opposite the frontside;
a lateral transistor device (#5, Figs. 8A-8C, [0075]-[0080], cross sectional view shown in Fig. 8A) having a body region (space occupied by lateral transistor #5) with a lateral channel region (not explicitly labelled, see [0076]: “The transistor 5 comprises a source region 201, a drain region 205, a channel region, a drift zone and a gate electrode 210 adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface.”), and a source region (#201) and a drain region (#205) formed at the frontside of the semiconductor body (top side with respect to Fig. 8A); and
a deep trench (#292, #293, #393, Figs. 1, 4A, and 8B, [0037], [0041], [0057], [0063]-[0065], and [0078]) arranged laterally between the vertical power transistor device and the lateral transistor device (see top down view in Fig. 4B), wherein the deep trench (#292, #293, #393) forms a deep trench isolation (see cross sectional views in Figs. 4B and 8A).
Koepp does not explicitly disclose:
wherein the deep trench completely intersects the semiconductor body, extending from the frontside to the backside.
However, in analogous art, Hsu teaches:
See Figs. 1 and 2. See
wherein the deep trench completely intersects the semiconductor body, extending from the frontside to the backside.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Hsu to the device disclosed by Koepp and form the deep trench isolation structure such that it entirely passes through the semiconductor body. Hsu discloses in [0018] “The UD trench isolation structure 12 penetrates the substrate 10 by extending from the top surface 10a to the bottom surface 10b of the substrate 10, as shown in FIG. 1 B. According to the embodiment, the UD trench isolation structure structurally (and physically) isolates the semiconductor devices within different regions of the regions.” emphasis added. Additionally, Hsu [0019] states “Since the UD trench isolation structure 12 penetrates through the substrate 10, it provides great isolation between the semiconductor devices within the different regions.” Therefore, doing so in the device disclosed by Koepp would assist in the electrical isolation of adjacent/corresponding regions for better device performance.
Regarding Claim 17, Koepp in view of Hsu discloses: The semiconductor die of claim 16, Koepp further discloses:
further comprising:
a shielding field electrode region (#250) with a shielding field electrode (#270) formed in a shielding field electrode trench (#214, Fig. 8B, [0076]) in the semiconductor body (#1),
wherein at least a portion of the lateral transistor device (#5) is arranged vertically above the shielding field electrode region (see cross sectional view in Fig. 8A, gate electrode #210 is vertically above portion #270 of field plate #250).
Regarding Claim 18, Koepp in view of Hsu discloses: The semiconductor die of claim 17,
Koepp further discloses:
the vertical power transistor device (#3, Fig. 4B) comprises a field electrode region (region defined by space occupied by gate dielectric layer #407) with a field electrode (#405) formed in a field electrode trench (trench defined by space occupied by gate dielectric layer #407), and wherein the field electrode trench of the vertical power transistor device (#3) and the shielding field electrode trench (#250) differ from each other in at least one of vertical depth and lateral width (see Figs. 4B and 8A).
Regarding Claim 19, Koepp in view of Hsu discloses: The semiconductor die of claim 17,
Koepp further discloses:
wherein a contact region (rightmost portion of #250, i.e. portion that makes electrical contact with #252 in Fig. 8A) of the shielding field electrode (#250) extends laterally aside the channel region (#220, Fig. 4A) of the lateral transistor device (#5) and vertically up to the frontside of the semiconductor body (#1).
Regarding Claim 20, Koepp in view of Hsu discloses: The semiconductor die of claim 17,
Koepp further discloses:
wherein a gate electrode (#210) of the lateral transistor device (#5) is arranged in a trench ([0076]) laterally aside the channel region (#220) of the lateral transistor device (#5).
Regarding Claim 21, Koepp in view of Hsu discloses: The semiconductor die of claim 20,
Koepp further discloses:
wherein the gate electrode (#210) of the lateral transistor device (#5) is arranged above the shielding field electrode (#250) in the shielding field electrode trench (#214, Fig. 8B, [0076]).
Regarding Claim 23, Koepp in view of Hsu discloses: The semiconductor die of claim 20,
Koepp further discloses:
wherein the lateral channel region (#220) is offset downwards (see Fig. 8A) into the semiconductor body (#1).
Regarding Claim 24, Koepp in view of Hsu discloses: The semiconductor die of claim 23, further comprising:
Koepp further discloses:
a surface channel blocker region (#280a), which is made of a same conductivity type as the body region ([0039]) of the lateral transistor device (#5) but with a higher doping concentration (“heavily doped” [0059]),
formed above the body region (space occupied by lateral transistor #5) of the lateral transistor device (#5).
Regarding Claim 25, Koepp in view of Hsu discloses: The semiconductor die of claim 20,
Koepp further discloses:
wherein a lateral field electrode (#250) of the lateral transistor device (#5) is arranged aside the drift region (#260) of the lateral transistor device (#5) with respect to a first lateral direction, and aside the gate electrode (#210) of the lateral transistor device (#5) with respect to a second lateral direction, in the same trench (#214) with the gate electrode (#210).
Regarding Claim 26, Koepp in view of Hsu discloses: The semiconductor die of claim 16,
Koepp further discloses:
wherein the source region (#201) and/or the drain region (#205) of the lateral transistor device (#5) comprises a surface implant with a higher doping concentration ([0035]) compared to a body region (see Fig. 4B, includes elements in gate trench #310) of the vertical power transistor device (#3).
Regarding Claim 27, Koepp in view of Hsu discloses: The semiconductor die of claim 16, further comprising:
Koepp further discloses:
a source contact (#202) electrically contacting the source region (#201) of the lateral transistor device (#5) and vertically extending through the source region (#201) down into the body region (space occupied by lateral transistor #5) of the lateral transistor device (#5), wherein the source contact (#202) forms a body contact (#281, Fig. 8A).
Regarding Claim 28, Koepp in view of Hsu discloses: The semiconductor die of claim 16,
Koepp further discloses:
wherein a gate electrode (#210) of the lateral transistor device (#5) is arranged in a trench (#214) laterally aside the channel region (#220, see top-down view in Fig. 8B) of the lateral transistor device (#5).
Regarding Claim 29, Koepp in view of Hsu discloses: The semiconductor die of claim 16,
Koepp further discloses:
wherein the lateral transistor device (#5) comprises a lateral drift region (#260) which is arranged laterally between the lateral channel region (#220) and the drain region (#205) of the lateral transistor device (#5), and wherein the drift region (#260) is made of a same conductivity type as the drain region (#205) but with a lower doping concentration ([0035]).
Regarding Claim 30, Koepp discloses:
A method of manufacturing a semiconductor die (#2, see top down view in Fig. 4A comprising semiconductor devices (semiconductor bodies) #1 and #3), the method comprising:
Forming a vertical power transistor (#35, Figs. 4A and 4B, [0057]-[0058], cross sectional view shown in Fig. 4B) device having a source region (#401) at a frontside (top side of Fig. 4B) of a semiconductor body (#3) and a drain region (#409) at a backside (bottom side of Fig. 4B) of the semiconductor body (#3) opposite the frontside;
forming a lateral transistor device (#5, Figs. 8A-8C, [0075]-[0080], cross sectional view shown in Fig. 8A) having a body region (space occupied by lateral transistor #5) with a lateral channel region (not explicitly labelled, see [0076]: “The transistor 5 comprises a source region 201, a drain region 205, a channel region, a drift zone and a gate electrode 210 adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface.”), and a source region (#201) and a drain region (#205) formed at a frontside of the semiconductor body (top side with respect to Fig. 8A);
etching a deep trench (#292, #293, #393, Figs. 1, 4A, and 8B, [0037], [0041], [0057], [0063]-[0065], and [0078], specifically [0064] discloses etching step) laterally between the vertical power transistor device and the lateral transistor device (see top down view in Fig. 4B);
and filling the deep trench (#292, #293, #393) to form a deep trench isolation (see cross sectional views in Figs. 4B and 8A).
Koepp does not explicitly disclose:
wherein the deep trench completely intersects the semiconductor body, extending from the frontside to the backside.
However, in analogous art, Hsu teaches:
See Figs. 1 and 2. See
wherein the deep trench completely intersects the semiconductor body, extending from the frontside to the backside.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Hsu to the device disclosed by Koepp and form the deep trench isolation structure such that it entirely passes through the semiconductor body. Hsu discloses in [0018] “The UD trench isolation structure 12 penetrates the substrate 10 by extending from the top surface 10a to the bottom surface 10b of the substrate 10, as shown in FIG. 1 B. According to the embodiment, the UD trench isolation structure structurally (and physically) isolates the semiconductor devices within different regions of the regions.” emphasis added. Additionally, Hsu [0019] states “Since the UD trench isolation structure 12 penetrates through the substrate 10, it provides great isolation between the semiconductor devices within the different regions.” Therefore, doing so in the device disclosed by Koepp would assist in the electrical isolation of adjacent/corresponding regions for better device performance.
Regarding Claim 31, Koepp in view of Hsu discloses: The method of claim 30,
Koepp further discloses:
wherein forming the lateral transistor device (#5) comprises:
implanting a dopant ([0039]) obliquely via a sidewall of the deep trench (#292, #293, #393) into the semiconductor body to form the body region (space occupied by lateral transistor #5) of the lateral transistor device (#5).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0268423 A1 Koepp et al in view of US 2018/0204838 A1 Hsu et al and further in view of US 2020/0235237 A1 Qian (herein “Qian”).
Regarding Claim 22, Koepp in view of Hsu discloses: The semiconductor die of claim 20.
Koepp in view of Hsu does not explicitly disclose:
further comprising:
a counterdoping layer disposed laterally between the body region and a gate dielectric of the lateral transistor device,
wherein the counterdoping layer is made of an opposite conductivity type compared to the body region of the lateral transistor device.
However, in analogous art, Qian teaches:
See Fig. 1A and [0010]-[0018].
a counterdoping layer (#103, second conductivity type well 103, [0012]) disposed laterally between the body region (#102, first conductivity type drift region, [0011]) and a gate dielectric (#105, [0011]) of the lateral transistor device (device shown in Fig. 1A),
wherein the counterdoping layer (#103) is made of an opposite conductivity type compared to the body region (#102) of the lateral transistor device.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Qian to the device disclosed by Koepp in view of Hsu and include a layer of opposite conductivity type adjacent to the body region of the lateral transistor device. Doing so would improve the reliability of the device and expand the safe working range of the device [0114], and additionally allow adjustment of the device threshold voltage for specific applications.
Allowable Subject Matter
Claims 32, 35, and 37-41 are allowed. The following is an examiner’s statement of reasons for allowance: Applicant amended previously marked allowable subject matter and intervening dependent claims into independent claim 32. See Non-Final page 11 filed 04/06/2026 for details. See also Claim Amendments in Applicant’s Remarks on page 9 filed 06/11/2026.
Regarding Independent Claim 32: The subject matter of claim 36 and intervening claim 33-34 that was previously indicated objected to but allowable has been amended into independent claim 32 (see Allowable Subject Matter on page 11 of the non-final rejection dated 04/06/2026 for details). Dependent claims 25 and 37-41 are allowed for their dependency on allowable independent claim 32.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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