DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-8, 11-21 and 24 are pending in the application and are currently being examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/14/2024 is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities:
The contents of paragraph [0056] appear to be identical to the first half of paragraph [0054].
In paragraph [0064] there appears to be a typo of “SOW” in place of “SoW”
From paragraph [0067] onwards, every instance of element 26 appears as "structure26" and is missing a space.
In paragraph [0093], the phrase "A layer of thermal interface layer" is grammatically incorrect, examiner is unsure the desired meaning.
Appropriate correction is required.
Drawings
The drawings are objected to because it is unclear if the horizontal lines in layer 92 of Figs. 7A and 7B are physical elements requiring a label. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-11, and 13-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gong et al. (US 2020/0227338 A1, hereafter Gong).
Regarding claim 1, Fig. 2 of Gong teaches an electronic assembly comprising:
an electronic component (220, [0032]) having a first side (see annotated Fig. 2);
a heat removing structure (240, [0033]) coupled to the first side of the electronic component (220); and
a thermal interface structure (101, [0021]) comprising a thermal interface layer (105, [0021]) and an adhesion layer (110, [0021]), the thermal interface layer (105) positioned between the first side of the electronic component (220) and the heat removing structure (240), and the adhesion layer (110) positioned between the heat removing structure (240) and the thermal interface layer (105).
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Regarding claim 2, Gong teaches the assembly of Claim 1, wherein the electronic component is a system on a wafer (SoW). Gong [0032] describes IC die 220 can include one or more ICs or be a system on a chip. So while not using the common verbiage of wafer in this instance, Gong still teaches a system on a wafer under BRI.
Regarding claim 3, Gong teaches the assembly of Claim 1, wherein the thermal interface layer (101, [0021]) comprises a vertically aligned graphite layer ([0025]) that is aligned generally perpendicular to the first side of the electronic component (220, [0032]). As the layer 105 can be the same size as layer 220 (described as the footprint of TIM stack 101, which includes layer 105, [0033]), this allows for vertical alignment of the layers (most directly shown in the combination of Fig. 1B and Fig. 2). With the layer 105 being deposited on top of layer 220, the alignment is also perpendicular to electronic component 220.
Regarding claim 4, Gong teaches the assembly of Claim 1, wherein the thermal interface layer (101, [0021]) comprises a carbon nanotube layer ([0025]).
Regarding claim 5, Gong teaches the assembly of Claim 1, wherein a thickness of the thermal interface layer (101, [0021]) is greater than a thickness of the adhesion layer (110, [0021]) ([0023]).
Regarding claim 8, Gong teaches the assembly of Claim 1, wherein the adhesion layer (110, [0021]) comprises a metal adhesion layer ([0030]).
Regarding claim 11, Gong teaches the assembly of Claim 1, Fig. 1B further teaches a second adhesion layer (110, [0021]) between the electronic component (220, [0032]) and the thermal interface layer (105, [0021]).
Regarding claim 13, Fig. 2 of Gong teaches a method of manufacturing an electronic assembly, the method comprising:
providing (a) a thermal interface layer (105, [0021]) between a first side (see annotated Fig. 2) of an electronic component (220, [0032])and a heat removing structure (240, [0033]) and (b) an adhesion layer (110, [0021]) between the thermal interface layer (105) and the heat removing structure (240); and
applying pressure ([0041]) to bond the electronic component (220) and the heat removing structure (240) by way of the thermal interface layer (105).
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Regarding claim 14, Gong teaches the method of Claim 13, wherein the electronic assembly is a system on a wafer assembly and the electronic component is a system on a wafer (SoW). Gong [0032] describes IC die 220 can include one or more ICs or be a system on a chip. So while not using the common verbiage of wafer in this instance, Gong still teaches a system on a wafer under BRI.
Regarding claim 15, Gong teaches the method of Claim 13, wherein a thickness of the thermal interface layer (101, [0021]) is greater than a thickness of the adhesion layer (110, [0021]) ([0023]).
Regarding claim 16, Gong teaches the method of Claim 13, wherein the adhesion layer (110, [0021]) comprises one of:
a horizontally aligned graphite layer that is aligned generally parallel with a first side of the electronic component;
a metal adhesion layer; or
a thermal grease layer. Gong teaches a metal adhesion layer in ([0030]).
Regarding claim 17, Gong teaches the method of Claim 13, Fig. 1B further teaches a second adhesion layer (110, [0021]) between the electronic component (220, [0032]) and the thermal interface layer (105, [0021]), wherein the adhesion layer and the second adhesion layer comprise a same material. As both adhesion layers are denoted with 110, it can be reasonably assumed they comprise the same material.
Claim(s) 19-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bet-Shliemoun (US 2015/0279761 A1, hereafter Bet-Shliemoun).
Regarding claim 19, Fig. 2 of Bet-Shliemoun teaches a wafer assembly comprising:
a wafer (124 [0023] is described as also being a wafer in [0020]) having a first side (see annotated Fig. 2);
a heat removing structure (120, [0022]) coupled to the wafer (124);
a thermal interface structure (131, [0023]) disposed between and bonding the first side of the wafer (124) and the heat removing structure (120), the thermal interface structure (131) comprising a thermal interface material [0023]; and
a groove (tracks 134, 136, [0024]) between the wafer (124) and the heat removing structure (120), at least a portion of the thermal interface material (131) is disposed in the groove (134, 136).
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Regarding claim 20, Bet-Shliemoun teaches the assembly of Claim 19, wherein the groove (tracks 136, [0024]) is in a surface of the wafer (124, [0023]).
Regarding claim 21, Bet-Shliemoun teaches the assembly of Claim 19, wherein the groove (tracks 134, [0024]) is in a surface of the heat removing structure (120, [0022]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gong as applied to claim 1 above, and further in view of Tseng et al. (US 2018/0247912 A1, hereafter Tseng).
Regarding claim 6, Gong teaches the assembly of Claim 1, wherein the adhesion layer (110, [0021]) comprises a horizontally aligned layer that is aligned generally parallel to the first side of the electronic component (220, [0032]). A horizontally aligned layer merely requires deposition atop another layer in a stack, and the adhesion layer is atop the electronic component, making it horizontally aligned.
Gong fails to teach the adhesion layer to be a graphite layer. However, Tseng teaches graphite being used as an adhesive to increase thermal conductivity of the adhesive layer ([0023]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adhesive layer of Gong to be formed of graphite in order to form a conductive adhesive layer.
Regarding claim 7, Gong teaches assembly of Claim 1, wherein the thermal interface layer (105, [0021]) comprises a vertically aligned graphite layer ([0025]) that is aligned generally perpendicular to the first side of the electronic component (220, [0032]), and the adhesion layer (110, [0021]) comprises a horizontally aligned layer that is aligned generally parallel to the first side of the electronic component (220). As the layer 105 can be the same size as layer 220 (described as the footprint of TIM stack 101, which includes layer 105, [0033]), this allows for vertical alignment of the layers (most directly shown in the combination of Fig. 1B and Fig. 2). With the layer 105 being deposited on top of layer 220, the alignment is also perpendicular to electronic component 220. Similarly, a horizontally aligned layer merely requires deposition atop another layer in a stack, and the adhesion layer is atop the electronic component, making it horizontally aligned.
Gong fails to teach the adhesion layer to be a graphite layer. However, Tseng teaches graphite being used as an adhesive to increase thermal conductivity of the adhesive layer ([0023]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adhesive layer of Gong to be formed of graphite in order to form a conductive adhesive layer.
Claim(s) 12 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gong as applied to claims 1 and 13 above, and further in view of Wan et al. (US 2020/0111720 A1, hereafter Wan).
Regarding claim 12, Gong teaches the assembly of Claim 1, further comprising a control board (230, [0032]) coupled to a second side (see annotated Fig. 2) of the electronic component (220, [0032]) opposite the first side (see annotated Fig. 2).
Gong fails to teach a second heat removing structure between the second side of the electronic component and the control board.
However, Wan teaches a similar device in which a heat removing structure is between an electronic component and a control board (Fig. shows 112 and 607 not in contact, though [0056] says they can be in thermal contact with one another). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Gong to include the second heat removing structure between the electronic component and the control board to get the expected result of increased heat dissipation in the device.
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Regarding claim 18, Gong teaches the method of Claim 13, further comprising a control board (230, [0032]) coupled to a second side (see annotated Fig. 2) of the electronic component (220, [0032]) opposite the first side (see annotated Fig. 2).
Gong fails to teach a second heat removing structure between the second side of the electronic component and the control board.
However, Wan teaches a similar device in which a heat removing structure is between an electronic component and a control board (Fig. shows 112 and 607 not in contact, though [0056] says they can be in thermal contact with one another). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Gong to include the second heat removing structure between the electronic component and the control board to get the expected result of increased heat dissipation in the device.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bet-Shliemoun as applied to claim 19 above, and further in view of Wan.
Regarding claim 24, Bet-Shliemoun teaches the assembly of Claim 19, further comprising a control board (116, [0022]) coupled to a second side (see annotated Fig. 2) of the wafer (124, [0023]) opposite the first side (see annotated Fig. 2).
Bet-Shliemoun fails to teach a second heat removing structure between the second side of the electronic component and the control board.
However, Wan teaches a similar device in which a heat removing structure is between an electronic component and a control board (Fig. shows 112 and 607 not in contact, though [0056] says they can be in thermal contact with one another). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Bet-Shliemoun to include the second heat removing structure between the electronic component and the control board to get the expected result of increased heat dissipation in the device.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892