DETAILED ACTION
This action is in response to the Application filed on 05/14/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 11/13/2023 and 11/20/2023 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Claim Objections
Claim(s) 1, 3, 5, 7 and 8 is/are objected to because of the following informalities:
Claim 1 recites “the direct conversion” in line 5. Said limitation lacks antecedent basis.
Claim 1 recites “an H-bridge arrangement with interphase transformers” in line 7. It appears that it should be “the H-bridge arrangement with the interphase transformers”.
Claim 3 recites “wherein step for the adaptation” in line 1. It appears that it should be “wherein the step for the adaptation”.
Claim 3 recites “the delivery” in line 3. Said limitation lacks antecedent basis.
Claim 3 recites “the temporally staggered” in line 3. Said limitation lacks antecedent basis.
Claim 5 recites “the direct conversion” in lines 5 – 6. Said limitation lacks antecedent basis.
Claim 5 recites “an H-bridge arrangement with interphase transformers” in line 8. It appears that it should be “the H-bridge arrangement with the interphase transformers”.
Claim 7 recites “the temporally staggered” in line 3. Said limitation lacks antecedent basis.
Claim 8 recites “the first interphase transformer (18a) and the second interphase transformer (18b)” in line 4. Both limitations lack antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 2 and 4 – 6 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2011/0002445; (hereinafter Hattrup) in view of US Pub. No. 2011/0234191; (hereinafter Yeon).
Regarding claim 1, Hattrup [e.g. Fig. 5] discloses a method for operating a DC-DC voltage converter for supplying an electrolysis device [e.g. the term “for” is intended use which is deemed non-limiting] with electrical operating power [e.g. output power] wherein, in one step, at least four actuatable semiconductor switching elements in an H-bridge arrangement [e.g. see 402a-b] with interphase transformers connected down-circuit [e.g. Lp, Ls, 406; abstract recites “a control method which assures that the interphase transformer (406) is not saturated”] are actuated by a predetermined actuation signal sequence [e.g. Fig. 6; paragraph 041 recites “All possible combinations of operation modes having two DC/AC power inverter stages working on one high-voltage transformer are depicted in the table as depicted in FIG. 6”] for the direct conversion of a DC electric input voltage [e.g. Uin1 / Uin2] into a DC electric output voltage [e.g. Uout], characterized in that at least two DC voltage converter units are employed [e.g. 402a, 403a, 404, 405 and 402b, 403b, 404 and 405], each having four actuatable switching elements in an H-bridge arrangement [e.g. 402a, 402b] with interphase transformers [e.g. 406] connected down-circuit.
Hattrup fails to disclose incorporating the following steps: detection of a number of DC voltage converter units, and adaptation of the actuation signal sequence to the number of DC voltage converter units detected.
Yeon [e.g. Figs. 1 - 3] teaches incorporating the following steps: detection of a number of DC voltage converter units [e.g. paragraph 062 recites “determine the number of resonant converters to be operated among the n resonant converters according to the load is to determine the number of phases of the multi-channel converter 1”], and adaptation of the actuation signal sequence to the number of DC voltage converter units detected [e.g. paragraph 065 – 067 recite “The count generator 500 operates the resonant converter of the number determined according to the load among the n resonant converters, and determines the phase difference between the gate signals transmitted to the n resonant converters. The count generator 500 determines the reference clock number RCC, and counts the reference clock signal RCLK as one period unit. The count generator 500 counts the reference clock signals RCLK until the reference clock number corresponds to the load. The count generator 500 transmits the count signal CNT according to the count result to the count comparison unit 600. The count comparison unit 600 compares the count signal CNT and the n reference signals to generate n comparison signals. The gate driver 800 generates the n upper gate signals VG11-VG1n and the n lower gate signals VG21-VG2n according to the n comparison signals COM1-COMn. The multi-phase frequency modulation device 700 according to an exemplary embodiment of the present invention increases the number of resonant converters that are operated among the n resonant converters as the load is increased. As the number of operated resonant converters is increased, the rectification current of each resonant converter is added, and thereby the rectification current ID is increased. Thus, the converter supplying the output power of the high current by using the plurality of resonant converters may be provided. The output terminals of the plurality of resonant converters are coupled in parallel, and the output voltage of the resonant converter is uniformly controlled. Accordingly, the output voltage is controlled as the level that is appropriate for the load”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Hattrup by incorporating the following steps: detection of a number of DC voltage converter units, and adaptation of the actuation signal sequence to the number of DC voltage converter units detected as taught by Yeon in order of being able to improve efficiency and lifespan of the converter, paragraph 07.
Regarding claim 2, Hattrup fails to disclose wherein the step for the adaptation of the actuation signal sequence to the detected number of DC voltage converter units comprises an adaptation of a pulse frequency of the actuation signal sequence to the detected number of DC voltage converter units.
Yeon [e.g. Figs. 1 - 3] teaches wherein the step for the adaptation of the actuation signal sequence to the detected number of DC voltage converter units comprises an adaptation of a pulse frequency of the actuation signal sequence to the detected number of DC voltage converter units [e.g. paragraph 061 recites “The multi-phase frequency modulation device 700 determines the number of resonant converters and the number of driving channels to be operated among the n resonant converters. The multi-phase frequency modulation device 700 controls the gate driver 800 to generate the phase difference according to the number of driving channels between the upper gate signals of the resonant converters that are operated. Also, the multi-phase frequency modulation device 700 controls the gate driver 800 to generate the phase difference according to the number of driving channels between the lower gate signals of the resonant converters that are operated.” Paragraph 064 recites “The frequency modulator 400 receives the output voltage VOUT, and modulates the switching frequency according to the increasing and decreasing of the load. That is, if the load is increased, the switching frequency is decreased to compensate the increase. In contrary, if the load is decreased, the switching frequency is increased. Through this operation, the output voltage VOUT is maintained as a uniform voltage. The frequency modulator 400 generates a reference clock signal RCLK determining the switching frequency, and outputs it to the count generator 500”. Paragraph 067 recites “The multi-phase frequency modulation device 700 according to an exemplary embodiment of the present invention increases the number of resonant converters that are operated among the n resonant converters as the load is increased.”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Hattrup by wherein the step for the adaptation of the actuation signal sequence to the detected number of DC voltage converter units comprises an adaptation of a pulse frequency of the actuation signal sequence to the detected number of DC voltage converter units as taught by Yeon in order of being able to improve efficiency and lifespan of the converter, paragraph 07.
Regarding claim 4, Hattrup fails to disclose a computer program product, which is configured to execute a method as claimed in claim 1.
Yeon [e.g. Figs. 1 - 3] teaches a computer program product, which is configured to execute a method as claimed in claim 1 [e.g. paragraph 050 recites “A single processor or other unit may fulfill the functions of several items recited in the claims… A computer program may be stored/distributed on a suitable medium, such as e.g. an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as e.g. via the Internet or other wired or wireless telecommunication systems”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Hattrup by a computer program product, which is configured to execute a method as claimed in claim 1 as taught by Yeon in order of being able to improve efficiency and lifespan of the converter, paragraph 07.
Regarding claim 5, Hattrup [e.g. Fig. 5] discloses a DC voltage converter for supplying an electrolysis device [e.g. the term “for” is intended use which is deemed non-limiting] with electrical operating power [e.g. output power], comprising at least four actuatable semiconductor switching elements in an H-bridge arrangement [e.g. see 402a-b] with interphase transformers connected down-circuit [e.g. Lp, Ls, 406; abstract recites “a control method which assures that the interphase transformer (406) is not saturated”], wherein a control device of the DC voltage converter is configured to deliver a predefined actuation signal sequence [e.g. Fig. 6; paragraph 041 recites “All possible combinations of operation modes having two DC/AC power inverter stages working on one high-voltage transformer are depicted in the table as depicted in FIG. 6”; claim 5 recites “wherein said DC/AC power inverter control unit is adapted to minimize the magnitude of the inverter output currents' difference value (ΔI) to a value which ensures that the interphase transformer is not operated in a saturated state by controlling the switching states and/or switching times of the DC/AC power inverter stages dependent on this current difference (ΔI), thus enabling zero current operation”] to the at least four actuatable semiconductor switching elements for the direct conversion of a DC electric input voltage [e.g. Uin1 / Uin2] into a DC electric output voltage [e.g. Uout], characterized in that the DC voltage converter comprises at least two DC voltage converter units [e.g. 402a, 403a, 404, 405 and 402b, 403b, 404 and 405] each having four actuatable semiconductor switching elements in an H-bridge arrangement [e.g. 402a, 402b] with interphase transformers connected down-circuit [e.g. 406].
Hattrup fails to disclose wherein the control device of the DC voltage converter is configured to identify a number of DC voltage converter units and to adapt the actuation signal sequence to the number of DC voltage converter units identified.
Yeon [e.g. Figs. 1 - 3] teaches wherein the control device of the DC voltage converter is configured to identify a number of DC voltage converter units [e.g. paragraph 062 recites “determine the number of resonant converters to be operated among the n resonant converters according to the load is to determine the number of phases of the multi-channel converter 1”] and to adapt the actuation signal sequence to the number of DC voltage converter units identified [e.g. paragraph 065 – 067 recites “The count generator 500 operates the resonant converter of the number determined according to the load among the n resonant converters, and determines the phase difference between the gate signals transmitted to the n resonant converters. The count generator 500 determines the reference clock number RCC, and counts the reference clock signal RCLK as one period unit. The count generator 500 counts the reference clock signals RCLK until the reference clock number corresponds to the load. The count generator 500 transmits the count signal CNT according to the count result to the count comparison unit 600. The count comparison unit 600 compares the count signal CNT and the n reference signals to generate n comparison signals. The gate driver 800 generates the n upper gate signals VG11-VG1n and the n lower gate signals VG21-VG2n according to the n comparison signals COM1-COMn. The multi-phase frequency modulation device 700 according to an exemplary embodiment of the present invention increases the number of resonant converters that are operated among the n resonant converters as the load is increased. As the number of operated resonant converters is increased, the rectification current of each resonant converter is added, and thereby the rectification current ID is increased. Thus, the converter supplying the output power of the high current by using the plurality of resonant converters may be provided. The output terminals of the plurality of resonant converters are coupled in parallel, and the output voltage of the resonant converter is uniformly controlled. Accordingly, the output voltage is controlled as the level that is appropriate for the load”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Hattrup by wherein the control device of the DC voltage converter is configured to identify a number of DC voltage converter units and to adapt the actuation signal sequence to the number of DC voltage converter units identified as taught by Yeon in order of being able to improve efficiency and lifespan of the converter, paragraph 07.
Regarding claim 6, Hattrup fails to disclose wherein the control device of the DC voltage converter is configured to adapt a pulse frequency of the actuation signal sequence to the detected number of DC voltage converter units.
Yeon [e.g. Figs. 1 - 3] teaches wherein the control device of the DC voltage converter is configured to adapt a pulse frequency of the actuation signal sequence to the detected number of DC voltage converter units [e.g. paragraph 061 recites “The multi-phase frequency modulation device 700 determines the number of resonant converters and the number of driving channels to be operated among the n resonant converters. The multi-phase frequency modulation device 700 controls the gate driver 800 to generate the phase difference according to the number of driving channels between the upper gate signals of the resonant converters that are operated. Also, the multi-phase frequency modulation device 700 controls the gate driver 800 to generate the phase difference according to the number of driving channels between the lower gate signals of the resonant converters that are operated.” Paragraph 064 recites “The frequency modulator 400 receives the output voltage VOUT, and modulates the switching frequency according to the increasing and decreasing of the load. That is, if the load is increased, the switching frequency is decreased to compensate the increase. In contrary, if the load is decreased, the switching frequency is increased. Through this operation, the output voltage VOUT is maintained as a uniform voltage. The frequency modulator 400 generates a reference clock signal RCLK determining the switching frequency, and outputs it to the count generator 500”. Paragraph 067 recites “The multi-phase frequency modulation device 700 according to an exemplary embodiment of the present invention increases the number of resonant converters that are operated among the n resonant converters as the load is increased.”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Hattrup by wherein the control device of the DC voltage converter is configured to adapt a pulse frequency of the actuation signal sequence to the detected number of DC voltage converter units as taught by Yeon in order of being able to improve efficiency and lifespan of the converter, paragraph 07.
Claim(s) 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hattrup in view of Yeon and further in view of US Pub. No. 2009/0152949; (hereinafter Adragna).
Regarding claim 3, Hattrup fails to disclose wherein step for the adaptation of the actuation signal sequence to the detected number of DC voltage converter units comprises the delivery of an actuation signal sequence for the temporally staggered actuation of actuatable semiconductor switching elements, at least of the DC voltage converter units.
Adragna teaches wherein step for the adaptation of the actuation signal sequence to the detected number of DC voltage converter units comprises the delivery of an actuation signal sequence for the temporally staggered actuation of actuatable semiconductor switching elements [e.g. switches in Conv1-ConvN], at least of the DC voltage converter units [e.g. paragraph 015 recites “the device further includes a generating circuit that generates a plurality of signals staggered temporally by a given period of time, the plurality of signals received at the input of the plurality of control circuits”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Hattrup by wherein step for the adaptation of the actuation signal sequence to the detected number of DC voltage converter units comprises the delivery of an actuation signal sequence for the temporally staggered actuation of actuatable semiconductor switching elements, at least of the DC voltage converter units as taught by Adragna in order of being able to reduce power consumption, paragraph 011.
Regarding claim 7, Hattrup fails to disclose wherein the control device of the DC voltage converter is configured to deliver an actuation signal sequence for the temporally staggered actuation of the actuatable semiconductor switching elements of the DC voltage converter units.
Adragna teaches wherein the control device of the DC voltage converter is configured to deliver an actuation signal sequence for the temporally staggered actuation of the actuatable semiconductor switching elements of the DC voltage converter units [e.g. switches in Conv1-ConvN; paragraph 015 recites “the device further includes a generating circuit that generates a plurality of signals staggered temporally by a given period of time, the plurality of signals received at the input of the plurality of control circuits”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Hattrup by wherein the control device of the DC voltage converter is configured to deliver an actuation signal sequence for the temporally staggered actuation of the actuatable semiconductor switching elements of the DC voltage converter units as taught by Adragna in order of being able to reduce power consumption, paragraph 011.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hattrup in view of Yeon and further in view of US Pub. No. 2016/0349288; (hereinafter Barnette).
Regarding claim 8, Hattrup discloses a first interphase transformer [e.g. Lp] and a second interphase transformer [e.g. Ls].
Hattrup fails to disclose upon the actuation of the DC voltage converter, the actuation signal sequence is determined thereby such that a current of equal current strength flows through the first interphase transformer and the second interphase transformer.
Barnette [e.g. Fig. 2A, 2B] teaches upon the actuation of the DC voltage converter, the actuation signal sequence [e.g. Fig. 2B] is determined thereby such that a current of equal current strength flows through the first winding [e.g. upper of 218] and the second winding [e.g. lower of 218; paragraph 032 recites “in the directly coupled inductor (218) in the example of FIG. 2A, current generally flows equal in magnitude and in the opposite direction in the coils of the coupled inductor. That is, when current enters one dot, current is induced to exit the other dot”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Hattrup by upon the actuation of the DC voltage converter, the actuation signal sequence is determined thereby such that a current of equal current strength flows through the first interphase transformer and the second interphase transformer as taught by Barnette in order of being able to provide current balance between phases.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838