Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Reply to Requirement for Restriction
Applicant’s election without traverse of Group 1 in the reply filed on 10 February, 2026 is acknowledged.
Objections to the Drawings
Figures 2 and 3 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, 12, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shiromizu et al. (JP 2015-162645), hereinafter referred to as Shiromizu.
Regarding claim 1, Shiromizu teaches a semiconductor device comprising: a semiconductor element (Shiromizu, 3, Fig. 2, para. 18); a lead electrode terminal having an extending portion separated from an upper surface of the semiconductor element and bonded to the semiconductor element (Shiromizu, 28, Fig. 2, para. 22); a first sealing member that seals the lead electrode terminal (Shiromizu, 6, Fig. 2, para. 24); and an intervening member (Shiromizu 2, Fig. 2, para. 18) provided between an end portion of the extending portion in an extending direction and the semiconductor element, the intervening member having an interface with the first sealing member under the end portion.
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Regarding claim 7, Shiromizu teaches the semiconductor device according to claim 1, wherein the intervening member includes a buffer layer provided on the upper surface of the semiconductor element (Shiromizu, 2, Fig. 2), and the first sealing member (Shiromizu, 6, Fig. 2) further seals the semiconductor element and the buffer layer (Shiromizu, para. 14-18).
Regarding claim 12, Shiromizu teaches the semiconductor device according to claim 1, wherein a region of the semiconductor element (Shiromizu, 15, Fig 2). immediately below the end portion of the extending portion in the extending direction is a non-conductive region (Shiromizu, para. 40 states that there is no clear interface between the oxygen-containing layer 15 and the underlying semiconductor substrate 3.
Regarding claim 13, Shiromizu teaches the semiconductor device according to claim 1, wherein a material of the semiconductor element includes a wide band gap semiconductor (Shiromizu, para. 21).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3, 5, 8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Shiromizu in view of Sasaki et al. (US Pub 20200194324), hereinafter referred to as Sasaki.
Regarding claim 2, Shiromizu teaches the semiconductor device according to claim 1, but does not teach wherein the intervening member includes a second sealing member that seals the semiconductor element.
However, Sasaki teaches a semiconductor device comprising: a semiconductor element (Sasaki, 4, Fig. 1, para. 19); a lead electrode terminal (Sasaki, 9, Fig. 1, paras.19-20) having an extending portion (Sasaki, Fig. 1, see diagram below) separated from an upper surface of the semiconductor element and bonded to the semiconductor element; a first sealing member that seals the lead electrode terminal (Sasaki, 22, paras. 23); and an intervening member (Sasaki, 21, Fig. 1, para. 23) provided between an end portion of the extending portion in an extending direction and the semiconductor element, (Sasaki, 21, Fig. 1, para. 23), wherein the intervening member includes a second sealing member (Sasaki, 21, Fig. 1, para. 23), that seals the semiconductor element (Sasaki, para 23).
Examiner’s note: Sasaki does not teach, from claim 1, the intervening member having an interface with the first sealing member under the end portion.
Therefore it is obvious to one having ordinary skill in the art before the filing date of the invention to combine the semiconductor element of Shiromizu with the sealing second member of Sasaki to reduce the stress on the semiconductor element and suppress cracks.
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Regarding claim 3, modified Shiromizu teaches the semiconductor device according to claim 2, wherein a physical property value of the first sealing member and a physical property value of the second sealing member are different from each other (Sasaki, paras 23, specifically mentions that the linear coefficient of the first sealing resin, 21 is lower than that of the second sealing resin 22).
Regarding claim 5, modified Shiromizu teaches the semiconductor device according to claim 2, wherein the second sealing member includes a resin (Sasaki, para. 23).
Sasaki does not explicitly state that the resin is molded, However, the resin of Sasaki is the same material as the claimed invention. Per MPEP 2113, "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process."
Regarding claim 8, Shiromizu teaches the semiconductor device according to claim 1,but does not teach wherein the intervening member includes a bonding member that bonds the semiconductor element and the lead electrode terminal, and the first sealing member further seals the semiconductor element and the bonding member.
However, Sasaki teaches wherein the intervening member includes a bonding member (Sasaki, 7, Fig. 1, para. 20) that bonds the semiconductor element and the lead electrode terminal and the first sealing member (Sasaki, 22, Fig. 1) further seals the semiconductor element and the bonding member(sealing resin 22 is above sealing member 21, solder 7, semiconductor 4 and inner frame 9, providing a seal).
Therefore it is obvious to one having ordinary skill in the art before the filing date of the invention to combine the semiconductor element of Shiromizu with the sealing second member and bonding member of Sasaki to reduce the stress on the semiconductor element and suppress cracks (Sasaki, para. 43).
Regarding claim 10, Shiromizu teaches the semiconductor device according to claim l, but does not teach wherein a protrusion is provided on an upper surface side of the end portion of the extending portion in the extending direction
However, Sasaki teaches a protrusion provided on an upper surface side of the end portion of the extending portion in the extending direction (Sasaki, 9, Fig. 1)
Therefore it is obvious to one having ordinary skill in the art before the filing date of the invention to combine the semiconductor element of Shiromizu with the protrusion on the upper surface of the electrode of Sasaki to reduce the stress on the semiconductor element and suppress cracks (Sasaki, para. 43).
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Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shiromizu and Sasaki in view of Tanimoto et al. (JP 2015-220238), hereinafter referred to as Tanimoto.
Regarding claim 4, modified Shiromizu teaches the semiconductor device according to claim 2, but does not teach wherein a material of the second sealing member includes a silicone gel.
However, Tanimoto teaches a semiconductor device which use a silicone gel (Tanimoto, 19, Fig. 13b, para. 111) to seal the semiconductor element (Tanimoto, 15, Fig. 12b).
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to have combined the silicone gel of Tanimoto with the second sealing member of modified Shiromizu to create a second sealing member of silicone gel to reduce the effects of heat and extend the lifetime of the system (Tanimoto, paras 105, 111).
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Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Shiromizu in view of Tanimoto et al. (JP 2015-220238), hereinafter referred to as Tanimoto.
Regarding claim 6, Shiromizu teaches the semiconductor device according to claim 1, but does not teach wherein the intervening member includes a stress buffer frame, and the first sealing member further seals the semiconductor element and the stress buffer frame.
However, Tanimoto teaches an in-plane stress relaxation body (Tanimoto, 21’, Fig. 12b, paras. 105-11) which is sealed by the silicone resin (Tanimoto, 19H, Fig. 12b).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to add the stress relaxation body of Tanimoto to the intervening member of Shiromizu to create a stress buffer frame sealed by the first sealing member, thereby reducing stress on the resin portion and delay cracks (Tanimoto, para. 105).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Shiromizu in view of Fujino et al. (US Pub 20170018495) hereinafter referred to as Fujino.
Regarding claim 11, Shiromizu teaches the semiconductor device according to claim l, but does not teach wherein the extending direction of the extending portion is inclined with respect to the upper surface of the semiconductor element.
However, Fujino teaches a lead terminal (Fujino, 62, Fig. 1B) wherein the extending direction of the extending portion (Fujino, 62t, Fig. 1B) is inclined with respect to the upper surface of the semiconductor element (Fujino, 3, Fig. 1B, para. 23) .
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the inclined portion of the lead electrode of Shiromizu with the inclined lead electrode of Fujino to create a lead electrode with inclined ends sealed in the intervening member to mitigate stress (Fujino, para. 38).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Murata (US Pub. 20210098344) teaches a semiconductor device with a first and second sealing member and an electrode with an inclined lead electrode terminal.
Okumura et al. (JP 2009-64852) teaches a semiconductor device with two sealing members and the second sealing member is made of resin.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893