Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Applicant’s arguments, see page 5, line 28- page. 6, line 2, filed 18 June 2026, with respect to Figs. 2 and 3 have been fully considered and are persuasive. The objection of Figs. 2 and 3 has been withdrawn.
Claim Rejections 35. U.S. C. § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 7 rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as based on a disclosure which is not enabling. The disclosure does not enable one of ordinary skill in the art to practice the invention without adding another layer, such as a solder layer between the intervening member and the upper surface of the semiconductor element, which is critical or essential to the practice of the invention but not included in the claim(s). See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976). In claim 1, lines 9 and 10, the amended claim recites wherein the interface of the intervening member with the first sealing member is entirely spaced from the semiconductor element. However, claim 7 does not disclose any member or layer between the semiconductor element and the intervening member, therefore the interface between the intervening member and the first sealing member would be in contact with the semiconductor element, as shown in Fig. 11 of the application. At present, neither the drawings not the specification teach an intervening layer between the semiconductor element and the intervening member.
Claim Rejections 35. U.S. C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 8, 11, 13, 14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Murata (US Pub. 20210098344), hereinafter referred to as Murata.
Regarding claim 1, Murata teaches a semiconductor device comprising: a semiconductor element (Murata 40, Figs. 1, 2, para. 23); a lead electrode terminal (Murata, 50, Figs. 1, 2, para. 24) having an extending portion separated from an upper surface of the semiconductor element and bonded to the semiconductor element; a first sealing member that seals the lead electrode terminal (Murata, 62, Fig. 1, 2, para. 26); and an intervening member (Murata, 61, Figs. 1, 2, para. 26) provided between an end portion of the extending portion in an extending direction and the semiconductor element, the intervening member having an interface with the first sealing member under the end portion, wherein, the interface of the intervening member with the first sealing member is entirely spaced from the semiconductor element (Murata, Fig. 2, para. 26).
Regarding claim 2, Murata teaches the semiconductor device according to claim 1, wherein the intervening member includes a second sealing member (Murata, 61, Figs. 1, 2, para. 26) that seals the semiconductor element.
Regarding claim 3, Murata teaches the semiconductor device according to claim 2, wherein a physical property value of the first sealing member and a physical property value of the second sealing member are different from each other (Murata, para. 28).
Regarding claim 5, Murata teaches the semiconductor device according to claim 2, wherein the second sealing member includes a resin (Murata, 45, Figs. 1, 2, para. 45).
Murata does not explicitly state that the resin is molded. However, per MPEP 2113, “Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process."
Regarding claim 8, Murata teaches the semiconductor device according to claim 1, wherein the intervening member includes a bonding member (Murata, 50a, Figs. 1, 2, para. 24) that bonds the semiconductor element and the lead electrode terminal, and the first sealing member further seals the semiconductor element and the bonding member (Murata, para. 26).
Regarding claim 11, Murata teaches the semiconductor device according to claim 1, wherein the extending direction of the extending portion is inclined with respect to the upper surface of the semiconductor element (Murata, Figs 1, 2).
Regarding claim 13, Murata teaches the semiconductor device according to claim 1, wherein a material of the semiconductor element includes a wide band gap semiconductor (Murata, 40, Figs. 1, 2, para. 46).
Regarding claim 14, Murata teaches the semiconductor device according to claim 1, wherein a physical property value of the intervening member and a physical property value of the first sealing member are different from each other (Murata para. 28).
Regarding claim 16, Murata teaches the semiconductor device according to claim 1, wherein the interface is provided so as to extend from an outside toward an inside of the end portion of the extending portion in plan view (Murata, Fig. 1, in plan view the interface between the first sealing member, 61, and the second sealing member, 62, would extend from the case ,20, para. 25, to under the angled end of the extending portion of terminal 50).
Claim Rejections 35. U.S. C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Murata.
Regarding claim 4, Murata teaches the semiconductor device according to claim 2, but does not teach wherein a material of the second sealing member includes a silicone gel.
Murata does teach wherein a material of the first sealing member includes a silicone gel (Murata, 62, Figs. 1, 2, para. 45) and a material of the second sealing member contains an epoxy resin (Murata, 61, Figs. 1, 2, para. 45).
It would be an obvious variant to select the sealing member with the higher elastic modulus to surround the part of the device which experiences higher thermal stress (Murata para. 31). Therefore if the lead electrode is of a material that will experience higher thermal stress than the semiconductor element it would be obvious to one having ordinary skill in the art before the filing date of the invention to place the higher elastic modulus material in a position to seal the lead electrode to resist the thermal stress Murata, para. 31).
Claims 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Murata as applied to claim 1 above, and further in view of Sasaki et al. (US Pub 20200194324), hereinafter referred to as Sasaki.
Regarding claim 6, Murata teaches the semiconductor device according to claim 1, but does not teach, wherein the intervening member includes a stress buffer frame, and the first sealing member further seals the semiconductor element and the stress buffer frame.
However, Sasaki teaches a polyimide layer (Sasaki, 17m Fig. 6, para. 66) between the first sealing resin (Sasaki, 21, Fig. 6, para. 65) and the second sealing resin (Sasaki, 22, Fig. 6, para. 65).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the polyimide layer of Sasaki with the semiconductor device of Murata in order to absorb the stress between the resins (Sasaki, para. 66) at the interface below the electrode.
Regarding claim 10, Murata teaches the semiconductor device according to claim l, but does not teach wherein a protrusion is provided on an upper surface side of the end portion of the extending portion in the extending direction.
However, Sasaki teaches a protrusion provided on an upper surface side of the end portion of the extending portion in the extending direction (Sasaki, 9, Fig. 1).
Therefore it would be obvious to one having ordinary skill in the art before the filing date of the invention to combine the semiconductor device of Murata with the protrusion on the upper surface of the electrode of Sasaki to reduce the stress on the semiconductor element and suppress cracks (Sasaki, para. 43).
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Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Murata and Sasaki.
Regarding claim 15, Murata teaches a semiconductor device comprising: a semiconductor element (Murata, 40, Figs. 1, 2, para. 23); a lead electrode terminal (Murata, 50, Figs. 1, 2, para. 24) having an extending portion separated from an upper surface of the semiconductor element and bonded to the semiconductor element; a first sealing member (Murata, 61, Figs. 1, 2, para. 26) that seals the lead electrode terminal; and an intervening member(Murata, 61, Figs. 1, 2, para. 26) provided between an end portion of the extending portion in an extending direction and the semiconductor element, the intervening member having an interface with the first sealing member under the end portion (Murata, Fig. 2).
Murata does not teach wherein the intervening member includes a stress buffer frame, and the first sealing member further seals the semiconductor element and the stress buffer frame.
However, Sasaki teaches a polyimide layer (Sasaki, 17m Fig. 6, para. 66) between the first sealing resin (Sasaki, 21, Fig. 6, para. 65) and the second sealing resin (Sasaki, 22, Fig. 6, para. 65).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the polyimide layer of Sasaki with the semiconductor device of Murata in order to absorb the stress between the resins (Sasaki, para. 66).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Murata as applied to claim 1 above, and further in view of Ishiyama et al. (US Pub. 20160111379), hereinafter known as Ishiyama.
Regarding claim 7, Murata teaches the semiconductor device according to claim 1, but does not teach wherein the intervening member includes a buffer layer provided on the upper surface of the semiconductor element, and the first sealing member further seals the semiconductor element and the buffer layer.
However, Ishiyama teaches a terminal cover (Ishiyama 19, Fig. 20, para. 85) arranged on a layer of the first sealing member (Ishiyama, 5, para. 86,) on the semiconductor element (Ishiyama, 1, Fig. 20, para. 35) and the first sealing member seals the terminal cover, the semiconductor element and the lead terminal (Ishiyama, 3a, Fig. 20, para. 85) with the interface between the terminal cover and the sealing resin remaining entirely spaced apart from the semiconductor element.
Therefore it would have been obvious to ne having ordinary skill in the art before the filing date of the invention to combine the thermal cover of Ishiyama with the device of Murata in order to minimize the stress applied to the resin and cracks can be prevented (Ishiyama para. 86).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Murata as applied to claim 1 above, and further in view of Shiromizu et al. (JP 2015162645), hereinafter referred to as Shiromizu.
Regarding claim 12, Murata teaches the semiconductor device according to claim 1, but does not teach wherein a region of the semiconductor element immediately below the end portion of the extending portion in the extending direction is a non-conductive region.
However, Shiromizu teaches a semiconductor device wherein a region (Shiromizu, 15, Fig. 2, para. 19) of the semiconductor device (Shiromizu 10, Fig. 2, para. 17) underneath the end portion (Shiromizu, 28, Fig. 2, para. 14) of the extending portion in the extending direction is a non-conductive region (Shiromizu para. 40, states there is no clear interface between the oxygen containing layer, 15, and the semiconductor substrate, 3). Therefore it would have been obvious to one having ordinary skill in the art to combine the oxygen containing layer of Shiromizu into the device of Murata in order to improve the adhesion between the semiconductor substrate and the sealing member (Shiromizu para. 19).
Response to Arguments
Applicant’s arguments, see page 6 lines 4-26, filed 18 June 2026, with respect to the rejections of claim 1 under 35 U.S.C. § 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Murata as described above.
Applicant’s arguments, see page 6, line 4 -page 7, line 6, filed 6/18/2026, with respect to the rejection of claims 2-8 and 9-13 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Murata as described above.
Applicant’s arguments, see page 7, line 1- 21, filed 6/18/2018, with respect to claim 6 have been fully considered and are persuasive. The rejection of 6 has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Murata in view of Sasaki.
Applicant’s arguments with respect to claims 14-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lacap et al. (US 8710664) teaches a semiconductor device using a resin to provide shock-load tolerance.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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