Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to JP 2021089185.
Claim Rejections under U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, the phrase “a step of forming a wiring layer on a surface on the light incident side of the semiconductor substrate” is unclear because the specification and the drawings do not show the wiring layer on the light incident side of the semiconductor substrate. In all figures the wiring layer is formed in an interlayer insulating film opposite the light incident side of the semiconductor substrate. Additionally in para. 33 of the instant application the order of layers from the light incident side are an optical layer 40, a semiconductor layer 20, and a wiring layer 30. Examiner interprets this phrase as shown in the figures and specification.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 reads “a step of reducing impurity concentration of in a”. The word “of” after impurity concentration implies a following impurity type, however no specific type of impurity appears in the specification. For purposes of further investigation, examiner has interpreted this to read:
-- a step of reducing impurity concentration in a--.
Claim Rejections under U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 7 and 9 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hwangbo et. al. (US 20170373108)
Regarding claim 1, Hwangbo teaches a solid-state imaging element (Hwangbo, Fig 5A)
comprising: a semiconductor layer including a plurality of photoelectric conversion sections disposed in a matrix (Hwangbo, Fig. 5A, PD); and a separation region that separates the photoelectric conversion sections adjacent to each other in the semiconductor layer (Hwangbo, Fig. 5A, 40(41, 43) and 45)
wherein the separation region includes: a wall-like electrode disposed in a wall shape (Hwangbo, Fig. 5A, 43), a negative bias voltage being applied to the wall-like electrode (par 66); and a low absorption member (Hwangbo, Fig. 5A, 45) disposed further on a light incident side than the wall- like electrode (Hwangbo, Fig. 5A) and having a light absorption rate smaller than a light absorption rate of the wall-like electrode (para. 63, para.80).
Examiner’s Note: Para. 80 shows that 45 is made from silicon oxide, while para. 63 shows that 43 is made from doped polysilicon. Because the prior art teaches the same materials as claims 4 and 5, the light absorption rate of the low light absorption member is lower than the light absorption rate of the wall like electrode.
Regarding claim 4, Hwangbo teaches the solid-state imaging element according to claim 1. Hwangbo further teaches wherein the wall-like electrode is configured using one selected out of polysilicon, tungsten, and aluminum as a main component (Hwangbo, para. 63).
Regarding claim 5, Hwangbo teaches he solid-state imaging element according to claim 1. Hwangbo further teaches wherein the low absorption member is configured using one selected out of silicon oxide, hafnium oxide, aluminum oxide, and titanium oxide as a main component (Hwangbo, para. 80).
Regarding claim 7, a method of manufacturing a solid-state imaging element, comprising: a step of forming a trench on a surface on an opposite side of a light incident side of a semiconductor substrate (Hwangbo, Fig 7A, Td, para. 74); a step of filling the trench with a low absorption member up to given depth from a bottom of the trench (Hwangbo, Fig 7A/B, 45, para. 79-81); a step of forming an insulating film on a side surface of the trench from the given depth to an opening of the trench (Hwangbo, Fig 7C, 43, para. 82); a step of filling a remaining part of the trench with a conductive wall-like electrode (Hwangbo, Fig 7C, 41, para. 82); and a step of forming a wiring layer (Hwangbo, Fig. 7D, 50, 60) on a surface on the light incident side of the semiconductor substrate (Hwangbo, para. 83, examiner notes that the wiring layer of the incident application (32) is in the same location as the prior art) wherein a wire formed in the wiring layer is connected to the wall-like electrode (Hwangbo, Fig 7D, 36 Page 5, para. 83), and the low absorption member (Hwangbo, Fig 7D. 45, para. 80) has a light absorption rate smaller than a light absorption rate of the wall-like electrode (Hwangbo Fig. 7D, 43, para. 62-63).
Examiner’s Note: Para. 62 shows that 45 is made from silicon oxide, while para. 63 shows that 43 is made from doped polysilicon. Because the prior art teaches the same materials as claims 4 and 5, therefore the light absorption rate of the low light absorption member is lower than the light absorption rate of the wall like electrode.
Regarding claim 9, Hwangbo teaches electronic equipment, comprising: a solid-state imaging element (Hwangbo, Fig 8, 900, Page 5, para. 85-86); an optical system (Hwangbo, Fig. 8, 910) that captures incident light from a subject and forms an image on an imaging surface of the solid-state imaging element (Page 5, para. 86-87); and a signal processing circuit (Hwangbo, Fig. 8, 912) that performs processing on an output signal from the solid-state imaging element (Hwangbo, para. 86-87), wherein the solid-state imaging element includes(Hwangbo, Fig. 5A); a semiconductor layer including a plurality of photoelectric conversion (Hwangbo, Fig. 5A, PD) sections disposed in a matrix; and a separation region (Hwangbo, Fig. 5A, 40, 45) that separates the photoelectric conversion sections adjacent to each other in the semiconductor layer, and the separation region includes: a wall-like electrode disposed in a wall shape (Hwangbo, Fig. 5A, 43), a negative bias voltage being applied to the wall-like electrode (Hwangbo, para. 70); and a low absorption member (Hwangbo, Fig. 5A, 45) disposed further on a light incident side than the wall- like electrode (Hwangbo, fig. 5A), the low absorption member having a light absorption rate smaller than a light absorption rate of the wall-like electrode (paras. 62 and 80).
Examiner’s Note: Para. 62 shows that 45 is made from silicon oxide, while para. 63 shows that 43 is made from doped polysilicon. Because the prior art teaches the same materials as claims 4 and 5, therefore the light absorption rate of the low light absorption member is lower than the light absorption rate of the wall like electrode.
Claim Rejections under U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hwangbo in view of Roy et. al. (US 20210020675), hereinafter referred to as Roy.
Regarding claim 2, Hwangbo teaches the solid-state imaging element according to claim 1. Hwangbo does not teach wherein the photoelectric conversion sections include a first region adjacent to the wall- like electrode and a second region adjacent to the low absorption member, and impurity concentration of the second region is lower than impurity concentration of the first region.
However, Roy teaches wherein the photoelectric conversion sections include a first region (Roy, Fig 1B, 110) adjacent to the wall- like electrode (Fig 1B, 115 and a second region (Roy, Fig. 1B, 105) adjacent to the low absorption member(Fig 1B, 116), and impurity concentration of the second region is lower than impurity concentration of the first region (Roy, para. 67).
Therefore it would have been obvious to a person of ordinary skill in the art prior to the filing date of the application to combine the teachings of Hwangbo and Roy and create a charge collection region to collect photogenerated charges and prevent defects.
Regarding claim 6, Hwangbo teaches the solid-state imaging element according to claim 1. Hwangbo also teaches a plurality of on-chip lenses that make light incident on the photoelectric conversion sections corresponding thereto.
However, Hwangbo does not teach wherein the separation region includes: a first separation region that separates the plurality of photoelectric conversion sections on which light is made incident via different pieces of the on-chip lenses; and a second separation region that separates the plurality of photoelectric conversion sections on which light is made incident via a same piece of the on-chip lenses, and the low absorption member located in the second separation region is disposed to a position deeper than the low absorption member located in the first separation region.
Roy teaches wherein the separation region (Roy, Fig. 7B, 115 and 116/117) includes: a first separation region that separates the plurality of photoelectric conversion sections on which light is made incident via different pieces of the on-chip lenses; and a second separation region that separates the plurality of photoelectric conversion sections on which light is made incident via a same piece of the on-chip lenses (Roy, para. 104-105).
Roy does not teach the low absorption member located in the second separation region is disposed to a position deeper than the low absorption member located in the first separation region
In order to minimize cross-talk, optimization of the depth of the low absorption member disposed between the two photoelectric conversion sections on which light is made incident via a same piece of the on-chip lenses would have been necessary. Therefore it would have been obvious to a person of ordinary skill in the art prior to the filing date of the application to conduct routine experimentation to find the optimal depth of each low absorption member in order to minimize cross talk.
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Regarding claim 8, Hwangbo teaches The method of manufacturing a solid-state imaging element according to claim 7. Hwangbo does not teach further comprising a step of reducing impurity concentration of in a region from depth corresponding to the bottom of the trench to the given depth to be lower than impurity concentration in a region from the given depth to the surface on the opposite side of the light incident side of the semiconductor substrate.
However, Roy, when describing the creation of the image sensor in (Roy, para. 110) states: that the charge collection region (Roy fig. 1B, 110) may be formed before the steps illustrated and that region (110) is formed by carrying out a doping step carried out on the side of front surface of the semiconductor substrate, above photosensitive region (105). Roy further states in para. 141 that the steps of forming 110 are within the abilities of those skilled in the art and are not detailed. Therefore it would have been within the knowledge of a person having ordinary skill in the art before the filing date of the application to combine the teachings of Hwangbo and Roy to suppress the occurrence of white spots in the photodiode.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hwangbo
Hwangbo teaches the solid-state imaging element according to claim 1, but does not specifically teach wherein the low absorption member is disposed up to a depth of 800 (nm) or more from a light incident surface of the semiconductor layer.
Hwangbo acknowledges the utility of a gap fill insulator filling a portion of each of the deep trenches. In order to prevent cross-talk between photoelectric conversion sections it would have been obvious to a person of ordinary skill in the art prior to the filing date of the application to have conducted routing experimentation to determine the optimal depth to dispose the gap-fill insulator and still allow for the proper function of the gate electrode.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Hiramatsu et. al. (US Pub. 20220238590) teaches a ratio of the lengths of the embedded electrode and the pixel isolation portion at about 3:7.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 08:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893