DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claim(s) 1, 10 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP11-284192.
Re claims 1 and 14, JP11-284192 discloses (Figs. 1-4) a substrate 8 constituted by a glass plate; the lower layer-side semiconductor film (201) + the polycrystalline semiconductor film (301) + the upper layer-side semiconductor film (401) constituting the channel formation region (3), which are provided in a stack, are provided on the substrate (8); wherein the lower layer-side semiconductor film (201) comprises an LDD region (203) and a first source/drain region (2), the LDD region (203) being connected with the polycrystalline semiconductor film (301), the first source/drain region (2), and a doping ion concentration within the LDD region (203) (approximately 1015 cm-3 ~ approximately 1018 cm-3) being less than a doping ion concentration within the first source/drain region 2 (approximately 1018 cm-3 ~ approximately 1020 cm-3). With respect to claim 14, JP11-284192 discloses an electronic device such as a liquid crystal display device.
Re claim 10, JP11-284192 discloses the polycrystalline semiconductor film (301) comprises dopant ions, and the upper side semiconductor film (401) above the polycrystalline semiconductor film (301) also needs to be doped, part of the doping ions penetrate into the polycrystalline semiconductor film (301) during the doping process of the upper layer side semiconductor film (401), so that the doping ion concentration on the side of the polycrystalline semiconductor film (301) facing away from the substrate (8) is greater than the doping ion concentration on the side of the polycrystalline semiconductor film (301) close to the substrate (8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-9, 11, 12 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over JP11-284192 as applied to claims 1, 10 and 14 above, and further in view of the following comments.
Re claims 2-4 and 15-17, JP11-284192 does not clearly disclose a ratio of the concentration of the dopant ions in the first doped portion to the concentration of the dopants ions in the second doped portion is in a range of 1/10 to 1/5; a thickness direction of the insulating substrate, a thickness of the second doped portion is less than or equal to a thickness of the first doped portion; and wherein in the thickness direction of the insulating substrate, a ratio of the thickness of the second doped portion to the thickness of the first doped portion is in a range of 1/4 to 1.
One of ordinary skill in the art would have been led to the recited concentration ratio, thickness and ratio of thickness through routine experimentation to achieve a desired transistor performance.
In addition, the selection of concentration ratio, thickness and ratio of thickness, it's obvious because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996)(claimed ranges or a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill or art) and In re Aller, 105 USPQ 233 (CCPA 1995) (selection of optimum ranges within prior art general conditions is obvious).
Note that the specification contains no disclosure of either the critical nature of the claimed concentration ratio, thickness and ratio of thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen concentration ratio, thickness and ratio of thickness or upon another variable recited in a claim, the Applicant must show that the chosen concentration ratio, thickness and ratio of thickness are critical. In re Woodruf, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Re claims 5 and 18, JP11-284192 discloses that in a direction perpendicular to the substrate (8), the polycrystalline semiconductor film (301) corresponds to the LDD region (203); therein, an orthographic projection of the polycrystalline semiconductor film (301) on the underlying-side semiconductor film (201) partially overlaps with the LDD region (203). With respect to the orthographic projection of the channel layer on the first active layer partially overlapping with the second doping, is a routine design choice for one of ordinary skill in the art.
It would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Re claims 6 and 19, JP11-284192 discloses wherein in a direction perpendicular to the substrate (8), the polycrystalline semiconductor film (301) corresponds to the LDD region (203); therein, an orthographic projection of the polycrystalline semiconductor film (301) onto the underlying-side semiconductor film (201) is located within the LDD region (203), and the orthographic projection of the polycrystalline semiconductor film (301) onto the underlying-side semiconductor film (201) does not overlap with the first source/drain region (2).
Re claims 7-9 and 20, JP11-284192 discloses that the TFT further comprises a gate electrode (7) on which an orthographic projection of the polycrystalline semiconductor film (301) partially overlaps; the gate electrode (7) is insulative disposed over the first source/drain region (2); an orthographic projection of the first source/drain region (2) onto the substrate (8) partially overlaps with an orthographic projection of the polycrystalline semiconductor film (301) onto the substrate (8).
With respect to wherein the thin film transistor further comprises a gate electrode layer, the gate electrode layer is insulated from and annularly arranged at a periphery of the channel layer; wherein the gate electrode layer comprises a first gate electrode portion and a second gate electrode portion that are integrally connected, the first gate electrode portion is disposed above the insulating substrate, and the second gate electrode portion is insulated from and disposed above the second doped portion; and wherein an orthographic projection of the channel layer on the first gate electrode portion is located in the first gate electrode portion, these are a conventional design choice for one of ordinary skill in the art.
It would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose this particular dimensions/location because applicant has not disclosed that the dimensions/location are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension/location. Indeed, it has been held that mere dimensional/location limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Re claim 11, JP11-284192 discloses that the TFT further comprises a gate insulating film (6) disposed between the active layer and a gate electrode (7), the gate insulating film (6) covering a surface of the first source/drain region (2) and a surface of a partial substrate (8).
Re claim 12, JP11-284192 discloses that the TFT further includes an interlayer insulating film (11) covering the gate insulating film (6) and the gate electrode (7), and a first source drain electrode (12) + a second source drain electrode (13) disposed on the interlayer insulating film (11); therein, contact holes (111) and (112) are provided on the gate insulating film (6) and the interlayer insulating film (11), a first source drain electrode (12) being connected with the first source/drain region (2) through the contact hole (111), and a second source drain electrode (13) being connected with the second source/drain region (4) through the contact hole (112).
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over JP11-284192 and comments as applied to claims2-9, 11, 12 and 15-20 above, and further in view of CN 110085678.
JP11-284192 does not disclose wherein the thin film transistor further comprises a light-shielding layer disposed in the insulating substrate, and an orthographic projection of the active layer on the light- shielding layer is located in the light-shielding layer; and wherein the gate electrode layer and the light-shielding layer are connected through a third via hole.
CN 110085678 discloses a thin film transistor ([0051-0057], Figures 2-3): the thin film transistor further comprises a light-shielding metal layer (30) disposed between the substrate (10) and the buffer layer (20), an orthographic projection of the active area (40) onto the light-shielding metal layer (30) being located within the light-shielding metal layer (30); therein, the gate metal layer (60) and the light-shielding metal layer (30) are connected by a first via A.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine JP11-284192 and CN 110085678 to add a light shielding metal layer of CN 110085678 into the device taught by JP11-284192 in order to protect the device from exposure.
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2024/0276772 A1, US 2022/0384550 A1 disclose a similar configuration for a thin film transistor with first and second doped portions.
Conclusion
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/MICHELLE MANDALA/Primary Examiner, Art Unit 2893 January 15, 2026