DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Star Sung et al. (US 2006/0120133).
Claim 13, Star discloses a semiconductor device (Figs. 3, 7-8, 10) comprising:
a plurality of first circuits (memory cells in a memory array, Fig. 8 and see example Fig. 10) arranged in a matrix of M rows and N columns (M and N are each an integer greater than or equal to 2, Memory Array comprises array of memory cells, Fig. 8); M second circuits (Row Decoder and Word Line Driver, Fig. 8); N third circuits (multiple sense amplifier 84, 88, 89, Fig. 8); and
M first wirings (word lines connected to the memory cells in the Memory Array, Fig. 8) and N second wirings (bit lines connected to the memory cells in the Memory Array, Fig. 8), wherein each of the plurality of first circuits comprises a transistor (transistor 72, Fig. 7 and see P[0041]… NMOS device which comprises the ROM cell…), wherein an i-th (i is an integer greater than or equal to 1 and less than or equal to M) first wiring is electrically connected to an i-th second circuit and a gate of the transistor included in each of the first circuits in an i-th row (word lines WL are connected to gate of the transistor, see Figs. 7 and 10),
wherein a j-th (j is an integer greater than or equal to 1 and less than or equal to N) second wiring is electrically connected to a j-th third circuit and one of a source and a drain of the transistor included in each of the first circuits in aj-th column (bit lines BL are connected to drain of transistor cells, see Fig. 7 and 10),
wherein the third circuit (sense amplifiers 84, 88, 89, Fig. 8) is configured to output voltage corresponding to a difference between current flowing through the second wiring (bit line, see Fig. 8) and reference current (reference voltages 85, 86, and 87, Fig. 8 and see P[0047]… reference voltages 85,86,87…), and
wherein a channel length varies randomly among the plurality of transistors electrically connected to the j-th second wiring (see P[0035] and [0041]).
Claim 14 is rejected as above since the elements and limitations are similar.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 2015/0029778) in view of Star Sung et al. (US 2006/0120133).
Claim 1, Yoon discloses a semiconductor device (100, Fig. 1) comprising:
a first circuit (circuit 101, 102), and a third circuit (sense amplifier 140); and
a first wiring, a second wiring, and a third wiring,
wherein the first circuit comprises a first transistor (transistors 112, 122) and a second transistor (transistors 114, 124),
wherein the first wiring (word line WL) is electrically connected to a gate of the first transistor (gate 115 of transistor 112, Fig. 1), and a gate (gate 115 of transistor 114, Fig. 1) of the second transistor,
wherein the second wiring (bit line BL) is electrically connected to the third circuit and one of a source and a drain of the first transistor (drain of transistor 112 connected to BL),
wherein the third wiring (bit line BLB) is electrically connected to the third circuit and one of a source and a drain of the second transistor (drain of transistor 112 connected to BL),
wherein the third circuit is configured to output voltage (1 bit Data) corresponding to a difference between current flowing through the second wiring and current flowing through the third wiring (see P[0018]… A sense amplifier 140 is configured to make a bit decision by sensing a voltage difference across the column line pair…), and
wherein threshold voltage of the first transistor and threshold voltage of the second transistor are different from each other (see P[0018]-[0019]…. Their threshold voltages are complementary in that one of the transistors in the transistor pair is a low Vt transistor and a remaining one of the transistors is a high Vt transistor…).
Thus, Yoon discloses the invention substantially as claimed, but does not disclose a second circuit connected to a word line (WL).
In the same field of endeavor, Star discloses a Mask ROM device (Fig. 1) comprises a word line decoder and a word line driver 7, Fig. 1 connected to word lines (WL) and to a gate of a transistor in the memory cell.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to provide a word line decoder and a word line driver connected to the word lines (WL) of Yoon, as taught by Star in order to provide decoder circuit in order to select a memory cell for reading or writing operation.
Claim 2, Yoon and Star discloses the claimed invention except for wherein the threshold voltage of the second transistor is less than or equal to 0.9 times or greater than or equal to 1.1 times the threshold voltage of the first transistor. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to implement the threshold voltage of the second transistor is less than or equal to 0.9 times or greater than or equal to 1.1 times the threshold voltage of the first transistor, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Claim 3, Yoon and Star discloses the claimed invention, star further teaches the threshold voltage of an MOS transistor can widely change within a certain range of device length of both channel length, L and width, W (see P[0041] of Star). Therefore, Yoon and Star discloses the claimed invention except for wherein a channel length of the second transistor is less than or equal to 0.9 times or greater than or equal to 1.1 times a channel length of the first transistor. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to implement a channel length of the second transistor is less than or equal to 0.9 times or greater than or equal to 1.1 times a channel length of the first transistor, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Claim 4, Yoon and Star discloses the semiconductor device according to claim 1, wherein the first transistor comprises an oxide semiconductor (see P[0017]… NMOS transistor…).
Claim 5, Yoon and Star discloses the semiconductor device according to claim 1, wherein the second transistor comprises an oxide semiconductor (see P[0017]… NMOS transistor…).
Claim 6, Yoon and Star discloses the claimed invention except for wherein the oxide semiconductor comprises at least one of indium and zinc. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to provide the oxide semiconductor comprises at least one of indium and zinc, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice.
Claim 7, Yoon discloses a semiconductor device (100, Fig. 1) comprising:
a plurality of first circuits (circuits 101, 102, Fig. 1) arranged in a matrix of M rows and N columns (M and N are each an integer greater than 2, see Fig. 1 and P[0021]… The word lines extend across multiple column line pairs--only a single column line pair is shown in. FIG. 1 for illustration clarity…);
N third circuits (sense amplifier 140, Fig. 1, connected to each pair of column lines); and M first wirings (word lines WL), N second wirings (bit lines BL), and N third wirings (complement bit lines BLB),
wherein each of the plurality of first circuits comprises a first transistor (transistor 112, 122) and a second transistor (transistor 114, 124),
wherein an i-th (i is an integer greater than or equal to 1 and less than or equal to M) first wiring (word lines WL) is electrically connected to a gate of the first transistor (gate 115 of transistor 112) included in each of the first circuits in an i-th row, and a gate of the second transistor (gate 115 of transistor 114) included in each of the first circuits in the i-th row,
wherein a j-th (j is an integer greater than or equal to 1 and less than or equal to N) second wiring (bit line BL) is electrically connected to a j-th third circuit (sense amplifier 140) and one of a source and a drain of the first transistor included in each of the first circuits in aj-th column (drain of transistor 112 connected to BL),
wherein a j-th third wiring (complement bit line BLB) is electrically connected to the j-th third circuit and one of a source and a drain of the second transistor included in each of the first circuits in the j-th column (drain of transistor 112 connected to BL),
wherein the third circuits are configured to output voltage (output 1 bit data) corresponding to a difference between current flowing through the second wiring (bit line BL) and current flowing through the third wiring (complement bit line BLB), and
wherein a difference between threshold voltage of the first transistor and threshold voltage of the second transistor varies randomly among the plurality of first circuits (see P[0018]-[0019]…. Their threshold voltages are complementary in that one of the transistors in the transistor pair is a low Vt transistor and a remaining one of the transistors is a high Vt transistor…).
Thus, Yoon discloses the invention substantially as claimed, but does not disclose M second circuit connected to M word line (WL).
In the same field of endeavor, Star discloses a Mask ROM device (Fig. 1) comprises a M word line decoder and a M word line driver 7, Fig. 1 connected to M word lines (WL) and to a gate of a transistor in the memory cell.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to provide a word line decoder and a word line driver connected to each word lines (WL) of Yoon, as taught by Star in order to provide decoder circuit in order to select a memory cell for reading or writing operation.
Claim 8, Yoon and Star discloses the claimed invention except for wherein the threshold voltage of the second transistor is less than or equal to 0.9 times or greater than or equal to 1.1 times the threshold voltage of the first transistor. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to implement the threshold voltage of the second transistor is less than or equal to 0.9 times or greater than or equal to 1.1 times the threshold voltage of the first transistor, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Claim 9, Yoon and Star discloses the claimed invention, star further teaches the threshold voltage of an MOS transistor can widely change within a certain range of device length of both channel length, L and width, W (see P[0041] of Star). Therefore, Yoon and Star discloses the claimed invention except for wherein a channel length of the second transistor is less than or equal to 0.9 times or greater than or equal to 1.1 times a channel length of the first transistor. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to implement a channel length of the second transistor is less than or equal to 0.9 times or greater than or equal to 1.1 times a channel length of the first transistor, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Claim 10, Yoon and Star discloses the semiconductor device according to claim 1, wherein the first transistor comprises an oxide semiconductor (see P[0017]… NMOS transistor…).
Claim 11, Yoon and Star discloses the semiconductor device according to claim 1, wherein the second transistor comprises an oxide semiconductor (see P[0017]… NMOS transistor…).
Claim 12, Yoon and Star discloses the claimed invention except for wherein the oxide semiconductor comprises at least one of indium and zinc. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to provide the oxide semiconductor comprises at least one of indium and zinc, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH Q TRAN whose telephone number is (571)272-1813. The examiner can normally be reached M-F: 9AM - 5PM.
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/ANH Q TRAN/Primary Examiner, Art Unit 2844 2/19/26