DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 15 November 2023 by the applicant has been considered and is included in the file.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “S1, S2, S3, S4” has been used to designate both “signals 1-4” (as seen in Figure 3) and “method steps” (as seen in Fig. 11). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 4 is objected to because of the following informalities:
Claim 4, includes references to “the rise of the calibration signal”, but it is unclear if this is separate from the rising edge of the calibration signal introduced in claim 2. For examination purposes, and based on information in the specification, this will be interpreted to read as “where
h
i
is a detection count in which the rising edge of the calibration signal is detected….and N is a total detection count in which the rising edge of the calibration signal…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5 and 7 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Ohnaka et al. (hereinafter Ohnaka, US 20200209395 A1).
Regarding claims 1 and 7, Ohnaka anticipates a TDC apparatus and a method of correction in a TDC apparatus, comprising:
a TDC circuit having ([0043]; Fig. 4, TDC delay line measurement unit (33)):
a delay circuit including a plurality of stages of delay elements configured to sequentially delay a measurement signal ([0043] - [0050]; Fig. 4, first delay line includes components (6-1) to (6-n) which delay signal RT);
and a plurality of storage elements provided in correspondence with the plurality of stages of delay elements, and configured to respectively hold outputs of the plurality of stages of delay elements in response to a measurement clock input thereto ([0043] - [0050]; Fig. 4, flip flop circuits (7-1) to (7-n) correspond to delay elements and intake delay signals (Q1...Qn));
an edge detection unit configured to detect a detection stage of a delay element, among the plurality of delay elements, that detects at least a rising edge of the measurement signal, based on switching of the outputs of the plurality of storage elements ([0077] - [0083]; Fig. 9, where delay signals (Q1-Q4) are determined based on a reference signal (Ref_Str) and whether the individual delay signal has had a rise to a high level or not);
and a delay amount correction unit configured to output a delay time of the measurement signal whose delay amount has been corrected by adding or subtracting a correction delay amount to or from a delay amount corresponding to the detection stage of the delay element in a delay conversion table relating to the detection stage of the delay element and a delay amount of the plurality of delay elements ([0043] - [0050]; Figs. 3, 4 where delay line output signal (D1a...D4a) are created and sent to buffer (315) which integrates delay line output signals and outputs signals such as (Dr), which are sent to a distance conversion unit (38) to correct distance calculations based on the number of steps of the delay circuit).
Regarding claim 5, Ohnaka anticipates a distance measuring apparatus comprising the TDC apparatus according to claim 1;
a light projecting unit configured to emit measurement light in synchronization with the measurement clock ([0035] - [0038]; Fig. 3, light projection element (14), circuit (24) and oscillator (31) work with clock generation unit (46) for emission);
a light receiving unit configured to receive reflected light of the measurement light reflected by an object, and output a measurement signal related to the reflected light to the TDC apparatus ([0035] - [0038]; Figs. 2,3, light emitted by projection element (14), is reflected off object (101) and collected by light reception element (15) and light reception circuit (25) to output light reception signal (RT));
and a distance calculation unit configured to calculate a distance to the object from a time difference between the measurement light and the reflected light after a delay amount is corrected in the TDC apparatus ([0040] - [0042]; Fig. 3, distance conversion unit (38) and register (39) determine distances to object (101) and includes correction from line measurement unit (33)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohnaka et al. (hereinafter Ohnaka, US 20200209395 A1) in view of Liu et al. (hereinafter Liu, US 20190064329 A1).
Regarding claims 2 and 3, Ohnaka teaches the TDC apparatus according to claim 1, but does not explicitly discuss a delay conversion table generator, used to determine a conversion (calibration/correction) set of values, or that the delay amount is based on a cumulative delay amount.
Liu teaches a device for measuring distance to an object, where a TDC includes a series of sequentially coupled delay elements, and where a delay conversion table generation unit configured to input a calibration signal whose period differs from the measurement clock to the delay circuit of the TDC circuit, and generate the delay conversion table relating to the detection stage of a delay element, among the plurality of delay elements, that detects a rising edge of the calibration signal and the delay amount of the plurality of delay elements ([0059], [0067] - [0070], [0108] - [0110], [0117]; Fig. 3, where timing signal (228) is separate from clock signal (230), which is input to latch unit (224) and counter(226), and a clock signal relates to a number of delay units based on the latch signals "1" and "0", where specific delay times are determined to calibrate the FPGA);
wherein the delay amount of the delay conversion table generation unit is a cumulative delay amount of the delay elements up to each detection stage from an initial stage of the plurality of stages of delay elements ([0080], [0108]; where a fine time value may correspond to a sum of individual delay times).
Therefore, to one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Ohnaka to incorporate the teachings of Liu to utilize a reference clock signal, which is separate from the clock signal, to form a table of correction values to apply to the series of delay elements with a reasonable expectation of success. As Liu notes, it is important in systems which require centimeter-level accuracy, such as for autonomous driving systems, to calibrate individual delay times associated with individual delay units ([0019]). Liu further describes that tracking a cumulative delay over time used in calibration allows the system to differentiate points where a delay time exceeds or does not exceed a clock period ([0072]).
Regarding claim 6, Ohnaka teaches the distance measuring apparatus according to claim 5 but is silent on the scanning components associated with the system.
Liu teaches a device for measuring distance to an object, where a TDC includes a series of sequentially coupled delay elements, and further teaches at least one of a light deflection unit configured to cause the measurement light emitted from the light projecting unit to be deflected in a predetermined direction and a light scanning unit configured to cause the measurement light to be scanned in a predetermined direction ([0037]; Fig. 1B beam steering device (158) can comprise various optical elements for steering the outgoing beam (162)).
Therefore, to one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Ohnaka to incorporate the beam steering mechanism of Liu to scan an environment with a reasonable expectation of success. Beam steering, directing and scanning is well known in the art of object detection and tracking (LiDAR) systems, and incorporation of the beam steering device of Liu would have a predictable result in the system of Ohnaka to facilitate environmental scanning.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Ohnaka as modified by Liu teaches a system where a delay correction unit is capable of correcting a delay time of specific delay components based on a delay conversion table, which includes a cumulative delay amount in the calibration/correction steps for individual delay elements.
Chujo et al. (hereinafter Chujo, “Experimental verification of timing measurement circuit with self-calibration”, IEEE, 2014) teaches architecture, implementation and measurement results for a Time-to-Digital Converter (TDC), with histogram-method self-calibration. The flash-type TDC includes multiple elements where each buffer delay can vary and be different. Further, the system looks at riding edges and determines a relative delay value by histogram measurement in calibration mode, to obtain delay values
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Where the TDC digital outputs incorporate variables such as histogram information (
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Song et al. (hereinafter Song, “An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction”, MDPI, Sensors, 2020) teaches a non-uniform multiphase TDC within a field-programmable gate array (FPGA), where the propagation delays in the delay chain vary significantly as the temperature changes. A lookup table (LUT) correction module corrects edge values according to a position of the cell within the delay chain and based on a threshold.
Torres et al. (hereinafter Torres, “Time-to-Digital Converter Based on FPGA With Multiple Channel Capability”, IEEE, 2013) teaches an FPGA with a TDC array where a device calibration process minimizes the effect of temperature and voltage fluctuations may be determined for each element within a delay line based on histogram information. Individual delays are found as
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Where the number of hits for an nth tap (H) and a total number of pulses (C) are used, and ultimately the delays are accumulated and stored in a LUT.
Ohnaka, Liu, Chujo, Song and Torres all teach differing aspects and ways that a system with a delay line, which includes multiple delay elements, may compensate or correct for individual delay irregularities. Each introduces variables which should be taken into account for determining the correction delay amount including histogram counts, a maximum tap/bin number, and rising edge locations within a delay element chain. However, Ohnaka as modified by Liu in view of Chujo, Song and Torres does not teach, or render obvious, a combination where the specific correction delay amount is found as follows:
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kara Richter whose telephone number is (571)272-2763. The examiner can normally be reached Monday - Thursday, 8A-5P EST, Fridays are variable.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helal Algahaim can be reached at (571) 270-5227. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.M.R./Examiner, Art Unit 3645
/HELAL A ALGAHAIM/SPE , Art Unit 3645
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