DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “DISPLAY PANEL AND ELECTRONIC TERMINAL WITH DRAIN AND SOURCE INCLUDING TRANSPARENT CONDUCTIVE MATERIAL”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 7 (line 6) and claim 17 (line 6), “the second gate insulating layer” lacks antecedent basis, and subsequently, in lines 9 of both claims, “a second gate insulating layer disposed on the second gate…” is recited; and
In lines 10 (of each claim 7 and 17), “the third gate insulating layer” lacks antecedent basis, and subsequently, in line 12 (of each claim), “a third gate insulating layer disposed on the second gate and the buffer layer” is recited.
Claims 7 and 17 are indefinite because it is not clear what “the second gate insulating layer” (in line 9) and “the third gate insulating layer” (in line 10) refer to in any prior claim(s). Therefore, for the purpose of examination, claims 7 and 17 will be interpreted without the limitations in lines 6-11 (of each claim).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9-13 and 20 are rejected under 35 U.S.C. 102(a) as being anticipated by Yun et al. (US 2016/0141349 A1; hereinafter, “Yun”).
Regarding claims 1-3, 9-13 and 20:
re claim 1, Yun discloses a display panel, comprising:
a substrate SUB (Fig. 6 and [0014]);
a first thin film transistor (TFT) DT (Fig. 6 and [0039]) disposed on the substrate and comprising a first active portion DA (Fig. 6 and [0041]), a first source DS [0041], and a first drain DD [0041], the first source and the first drain disposed on the first active portion, wherein the first source DS is electrically connected to a first end of the first active portion DA (Fig. 6), and the first drain DD is electrically connected to a second end of the first active portion DA; and
a pixel electrode layer ANO (Fig. 6 and [0046]) disposed on the first TFT DT and electrically connected to the first drain DD;
wherein a material of the first drain DD comprises a transparent conductive material ITO (Fig. 6 and [0054]);
wherein the first TFT DT further comprises a first gate DG (Fig. 6 and [0053]) disposed corresponding to the first active portion DA;
wherein the display panel further comprises:
a first planarization layer OC (Fig. 6 and [0016]) disposed between the first drain DD and the pixel electrode layer ANO and comprising a first opening, wherein the pixel electrode layer ANO is connected to the first drain DD through the first opening,
wherein the first opening (for ANO to connect to SG2/DD in Fig. 6) is arranged corresponding to the first gate DG (Fig. 6), and
wherein the first source DS is made of a material (ITO [0054]) same as the material of the first drain DD, and the first source DS and the first drain DD are disposed in a same layer IN2 (Fig. 6 and [0042]);
re claim 2, the display panel according to claim 1, further comprising:
an insulating layer GI (Fig. 6 and [0014]) disposed between the first source DS and the first drain DD which are arranged in different layers (e.g., GI is arranged in IN1 and the source/drain is arranged in IN2, Fig. 6),
wherein a projection of the first source DS projected on the substrate SUB at least partially overlaps with a projection of the first gate DG projected on the substrate SUB (i.e., the currently claim projections need not be orthographic projections on the substrate, therefore, if a projection is made from about 140 degrees counterclockwise from the substrate surface, the projections of DS and DG will overlap);
re claim 3, the display panel according to claim 1, further comprising:
a passivation layer BN (Fig. 6 and [0018]) disposed on the pixel electrode layer ANO, wherein a portion of the passivation layer BN, corresponding to the first opening, is provided with a second opening (for the “V” groove in ANO combined with opening for OLED in Fig. 6, i.e., prior filling the “V” groove with a portion of BN, an opening exists while forming BN) recessed downward;
a second planarization layer (portion of BN filling the “V” shaped region of ANO in Fig. 6) filled in the second opening (at least a portion of the opening, e.g., above “V”, is filled by a portion of BN—Note: the current claim does not require the second planarization layer to be different/distinct from the passivation layer BN), wherein an upper surface of the
second planarization layer (portion of BN above “V” groove) is flush with an upper surface of a portion of the passivation layer BN corresponding to the first planarization layer OC; and
a common electrode layer CAT (Fig. 6 and [0019]) disposed on the passivation layer BN and the second planarization layer (portion of BN in the “V” groove in Fig. 6);
re claim 9, Yun discloses a display panel, comprising:
a substrate SUB (Fig. 6 and [0014]);
a first thin film transistor (TFT) DT (Fig. 6 and [0039]) disposed on the substrate and comprising a first active portion DA (Fig. 6 and [0041]), a first source DS [0041], and a first drain DD [0041], the first source and the first drain disposed on the first active portion, wherein the first source DS is electrically connected to a first end of the first active portion DA (Fig. 6), and the first drain DD is electrically connected to a second end of the first active portion DA; and
a pixel electrode layer ANO (Fig. 6 and [0046]) disposed on the first TFT DT and electrically connected to the first drain DD;
wherein a material of the first drain DD comprises a transparent conductive material ITO (Fig. 6 and [0054]);
re claim 10, the display panel according to claim 9, wherein the first TFT DT further comprises a first gate DG (Fig. 6 and [0053]) disposed corresponding to the first active portion DA;
wherein the display panel further comprises:
a first planarization layer OC (Fig. 6 and [0016]) disposed between the first drain DD and the pixel electrode layer ANO and comprising a first opening, wherein the pixel electrode layer ANO is connected to the first drain DD through the first opening,
wherein the first opening (for ANO to connect to SG2/DD in Fig. 6) is arranged corresponding to the first gate DG (Fig. 6);
re claim 11, the display panel according to claim 10, further comprising:
an insulating layer GI (Fig. 6 and [0014]) disposed between the first source DS and the first drain DD which are arranged in different layers (e.g., GI is arranged in IN1 and the source/drain is arranged in IN2, Fig. 6),
wherein a projection of the first source DS projected on the substrate SUB at least partially overlaps with a projection of the first gate DG projected on the substrate SUB (i.e., the currently claim projections need not be orthographic projections on the substrate, therefore, if a projection is made from about 140 degrees counterclockwise from the substrate surface, the projections of DS and DG will overlap);
re claim 12, the display panel according to claim 9, wherein the first source DS is made of a material (ITO [0054]) same as the material of the first drain DD, and the first source DS and the first drain DD are disposed in a same layer IN2 (Fig. 6 and [0042]);
re claim 13, the display panel according to claim 10, further comprising:
a passivation layer BN (Fig. 6 and [0018]) disposed on the pixel electrode layer ANO, wherein a portion of the passivation layer BN, corresponding to the first opening, is provided with a second opening (for the “V” groove in ANO combined with opening for OLED in Fig. 6, i.e., prior filling the “V” groove with a portion of BN, an opening exists while forming BN) recessed downward;
a second planarization layer (portion of BN filling the “V” shaped region of ANO in Fig. 6) filled in the second opening (at least a portion of the opening, e.g., above “V”, is filled by a portion of BN—Note: the current claim does not require the second planarization layer to be different/distinct from the passivation layer BN), wherein an upper surface of the
second planarization layer (portion of BN above “V” groove) is flush with an upper surface of a portion of the passivation layer BN corresponding to the first planarization layer OC; and
a common electrode layer CAT (Fig. 6 and [0019]) disposed on the passivation layer BN and the second planarization layer (portion of BN in the “V” groove in Fig. 6); and
re claim 20, Yun discloses an electronic terminal, comprising a display panel, the display panel, comprising:
a substrate SUB (Fig. 6 and [0014]);
a first thin film transistor (TFT) DT (Fig. 6 and [0039]) disposed on the substrate and comprising a first active portion DA (Fig. 6 and [0041]), a first source DS [0041], and a first drain DD [0041], the first source and the first drain disposed on the first active portion, wherein the first source DS is electrically connected to a first end of the first active portion DA (Fig. 6), and the first drain DD is electrically connected to a second end of the first active portion DA; and
a pixel electrode layer ANO (Fig. 6 and [0046]) disposed on the first TFT DT and electrically connected to the first drain DD;
wherein a material of the first drain DD comprises a transparent conductive material ITO (Fig. 6 and [0054]);
Therefore, Yun anticipates claims 1-3, 9-13 and 20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4-8 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Kobayashi et al. (US 2022/0352279 A1; hereinafter, “Kobayashi”).
Regarding claims 4 and 14:
Yun anticipates claims 1 and 9 and further discloses:
a second thin film transistor (TFT) ST (Fig. 6 and [0012]) disposed on the substrate SUB and comprising a second gate SG (Fig. 6 and [0013]) and a second active portion SA (Fig. 6 and [0013]) which are disposed in different layers (Fig. 6, wherein SG and SA are in different layers) and arranged corresponding to each other,
wherein the second TFT ST is electrically connected to the first TFT (Fig. 2, wherein a switching TFT ST is typically electrically connected to a driving TFT DT), a material of the first active portion DA (Fig. 6 and [0015]) of the first TFT DT comprises metal oxide, and a material of the second active portion SA [0015] of the second TFT ST comprises metal oxide
Yun does not disclose the second transistor comprises an active portion made of low-temperature polysilicon.
Kobayashi discloses it was well known in the art to incorporate both OS transistor and Si transistor into a display device (e.g., see [0146-0147], and although incorporating OS transistors increases production costs, capital investment could be reduced by incorporating polysilicon transistors with OS transistors [0004].
It would have been obvious to one of ordinary skill in the art to modify Yun by incorporating a second transistor comprising polysilicon (instead of metal oxide) because the modification could reduce manufacturing costs (as shown by Kobayashi).
Regarding claims 5, 6, 7(as interpreted), 8, 15, 16, 17(as interpreted), 18 and 19:
re claims 5 and 15, Yun discloses a first light-shielding layer LS (Fig. 6 and [0049]) disposed between the substrate SUB and the first active portion DA, wherein the first light-shielding layer LS is disposed corresponding to the first active portion DA and arranged in a same layer OC as the second gate SG;
re claims 6 and 16, Yun discloses (according to claim 4) a second light-shielding layer LS (Fig. 6 and [0049]) comprising a first light-shielding portion (under DT) and a second light-shielding portion (under ST) disposed in a same layer BF,
wherein the first light-shielding portion (under DT) is disposed corresponding to the first active portion DA and arranged between the substrate SUB and the first TFT DT, and
wherein the second light-shielding portion (under ST) is disposed corresponding to the second active portion SA and arranged between the substrate SUB and the second TFT ST;
re claim 7 and 17 (both as interpreted), Yun discloses (according to claim 5), wherein the second TFT ST (Fig. 6) further comprises a second source SS and a second drain SD arranged in a same layer IN2;
the display panel further comprising:
a buffer layer BF (Fig. 6) disposed on the substrate, wherein the second gate SG is disposed on the buffer layer;
[the following limitations are not considered because they are indefinite]
a third gate insulating layer IN1 (Fig. 6) disposed on the second gate SG and the buffer layer BF, wherein the second gate SG and the first light-shielding layer LS are disposed on the third gate insulating layer IN1;
an interlayer insulating layer IN2 disposed on [a top side of] the first gate DG, the second source SS, the second drain SD, and the first gate insulating layer GI, wherein the first source DS is disposed on [a bottom side of] the interlayer insulating layer IN2; and
an insulating layer OC (Fig. 6) disposed on [a top side of] the first source DS and the interlayer insulating layer IN2, wherein the first drain DD is disposed on [on a bottom side of] the insulating layer OC;
re claims 8 and 18, Yun discloses wherein the first gate DG (Fig. 6) of the first TFT DT is disposed on the first active portion DA, and the second gate SG of the second TFT ST is disposed on the second active portion SA; and
re claim 19, Yun discloses a display part (in Fig. 6, a display part is considered to be region “AA” and half of region “NA” located on the left-side of “AA”, i.e., the display part is considered to the “AA” plus the portion of “NA” including “DT”) and a non-display part (in Fig. 6, a portion of “NA” that includes only ST) disposed on at least one side of the display part, wherein the first TFT DT is included in the display part, and the second TFT ST is included in the non-display part.
Therefore, claims 5-8 and 14-19 are rendered obvious by Yun (in view of Kobayashi).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The references listed on the attached PTO-892 disclose display panels with TFT comprising source/drains with transparent conductive material and/or transistors comprising metal oxide and polysilicon active layers, wherein the display panels have some similarity to current invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892