DETAILED ACTION
This Office Action is responsive to the Applicant’s communication filed 15 November 2023. In view of this communication, claims 1-15 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 4-5, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 20200243598 A1), hereinafter referred to as Chiu et al., in view of Seo Won Cheol et al. (KR 20110080952 A), hereinafter referred to as Seo Won Cheol et al.
Regarding claim 1, Chiu et al. teaches a circuit board, comprising at least one substrate (10) (Fig. 1, paragraph 26: substrate 10), and a metal layer (18) (Fig. 2A, paragraph 34: metal conductive layer 18) provided on a front surface and/or a back surface of the substrate (10), wherein the metal layer (18) is provided with a region array (22a-22f), the region array (22a-22f) comprises at least two first regions (22a, 22c) and at least two second regions (22b, 22d) formed by division through a first slit (36), and the first regions (22a, 22c) and the second regions (22b, 22d) are alternately distributed and mutually insulated in both a row direction (Fig. 1, axis X) and a column (Fig. 1, axis Y) direction of the region array (22a-22f) (Fig. 1, paragraphs 35-36: the light emitting units 22a-22f form an array and are separated by the trenches 36);
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Chiu et al. does not teach of the first regions and the second regions is provided with at least two mutually insulated metal sheets formed by division through a second slit, and the two adjacent metal sheets within each of the first regions and the second regions are correspondingly provided with solder pads for connecting with an electronic component; the solder pads within each of the first regions and the second regions are arranged in a multi-row and multi-column array on the substrate to form a solder pad array; at least a portion of the metal sheets within each of the first regions are provided with a first extension portion that extends along a column direction of the solder pad array, and in each row direction of the solder pad array within each of the first regions, the second slit is interrupted by the first extension portion; at least a portion of the metal sheets within each of the second regions are provided with a second extension portion that extends along a row direction of the solder pad array, and in each column direction of the solder pad array within each of the second regions, the second slit is interrupted by the second extension portion.
Seo Won Cheol et al. does teach the first regions and the second regions is provided with at least two mutually insulated metal sheets (LE1, LE2) formed by division through a second slit (35) (Fig. 1 and page 2, last paragraph: light emitting regions LE1, LE2 separated by electrode pad 35), and the two adjacent metal sheets (LE1, LE2) within each of the first regions and the second regions are correspondingly provided with solder pads (33a) (page 2, last paragraph: pad extensions 33a) for connecting with an electronic component; the solder pads (33a) within each of the first regions and the second regions are arranged in a multi-row and multi-column array on the substrate to form a solder pad array (each LED in the array is provided with pads 33a);
at least a portion of the metal sheets (LE1, LE2) within each of the first regions are provided with a first extension portion that extends along a column direction of the solder pad array, and in each row direction of the solder pad array within each of the first regions, the second slit (35) is interrupted by the first extension portion; at least a portion of the metal sheets (LE1, LE2) within each of the second regions are provided with a second extension portion that extends along a row direction of the solder pad array, and in each column direction of the solder pad array within each of the second regions, the second slit (35) is interrupted by the second extension portion (see Fig. 1: the extending pad 35a is constricted on the left and right by protruding portions of pads LE1 and LE2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace the LED regions of Chiu et al. with the LEDs of Seo Won Cheol et al. because the LEDs of Seo Won Cheo et al. provides improved light emitting efficiency (Seo Won Cheo et al. page 2, paragraphs 2-3).
Regarding claim 2, Chiu et al. in view of Seo Won Cheol et al. teaches the circuit board according to claim 1, wherein an extension direction of the first slit (Chiu et al. 36) and/or the second slit is the same as the row direction and the column direction of the solder pad array (Fig. 1, paragraphs 35-36: trenches 36 extend in the X and Y direction).
Regarding claim 4, Chiu et al. in view of Seo Won Cheol et al. teaches the circuit board according to claim 1, wherein a number of the solder pads (33a) within the first regions (LE1) and the second regions (LE2) is equal (Seo Won Cheo et al. Fig. 1: there is one pad 33a in each of the light emitting regions LE1 and LE2).
Regarding claim 5, Chiu et al. in view of Seo Won Cheol et al. teaches the circuit board according to claim 1, wherein the first slit (36) and/or the second slit extends in a meandering manner (Fig. 1, paragraphs 35-36: trenches 36 extend in multiple directions, creating a meandering path).
Regarding claim 12, Chiu et al. in view of Seo Won Cheol et al. teaches the circuit board according to claim 1, wherein a supporting region (36) is provided between the adjacent first region and second region (22a, 22b) (Fig. 1, paragraphs 35-36: trenches 36 between each adjacent area 22a, 22b).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. in view of Seo Won Cheol et al., in further view of Ito et al. (US 20110096045 A1), hereinafter referred to as Ito.
Regarding claim 6, Chiu et al. in view of Seo Won Cheol et al. teaches the circuit board according to claim 1, but does not teach that the first slit and the second slit are filled with a solder resist layer, and in a direction perpendicular to the substrate, a height of the solder resist layer is less than a height of the metal sheet.
Ito does teach that the first slit and the second slit are filled with a solder resist layer (20d), and in a direction perpendicular to the substrate, a height of the solder resist layer is less than a height of the metal sheet (Ito paragraph 116: the space between devices 10 is filled by a solder resist 20d).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a solder resist between the devices of Chiu et al. in view of Seo Won Cheol et al. because the solder resist provides additional insulation between adjacent devices.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. in view of Seo Won Cheol et al., in further view of Li et al. (US 20190280163 A1), hereinafter referred to as Li et al.
Regarding claim 7, Chiu et al. in view of Seo Won Cheol et al. teaches the circuit board according to claim 1, but does not teach that both the front surface and the back surface of the substrate are provided with the metal layers.
Li et al. does teach that both the front surface and the back surface of the substrate are provided with the metal layers (Li et al. paragraph 64: metal layers are provided on either side of the substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the substrate of Chiu et al. in view of Seo Won Cheol et al. with metal layers on the front and back surface of the substrate because additional metal layers would enable further wiring connections and an increased package density.
Regarding claim 8, Chiu et al. in view of Seo Won Cheol et al. teaches the circuit board according to claim 7, but does not teach a via hole that extends through the front surface and the back surface of the substrate is formed on the substrate to electrically connect the metal layers on the front surface and the back surface.
Li et al. does teach a via hole (5) that extends through the front surface and the back surface of the substrate is formed on the substrate to electrically connect the metal layers on the front surface and the back surface (Li et al. paragraph 64: via hole 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a via hole between the upper and lower metal layers as taught in the rejection of claim 7, above, because a via hole would enable electrical connections between the aforementioned metal layers on the upper and lower sides of the substrate (Li et al. paragraph 64).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. in view of Seo Won Cheol et al., in further view of Thacker et al. (US 9082808 B2), hereinafter referred to as Thacker et al.
Regarding claim 9, Chiu et al. in view of Seo Won Cheol et al. teaches the circuit board according to claim 1, but does not teach at least two of the substrates provided in a stacked manner, each of the substrates being provided with the metal layer.
Thacker et al. does teach at least two of the substrates provided in a stacked manner, each of the substrates being provided with the metal layer (Fig. 8A and column 7, lines 8-14: layers 1-3 are stacked).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide multiple substrates in a stacked manner as taught by Thacker et al. because the stacking method of Thacker et al. enables higher package density without sacrificing accuracy in positioning chips (Thacker et al. column 1, lines 35-45).
Regarding claim 10, Chiu et al. in view of Seo Won Cheol et al., in further view of Thacker et al. teaches the circuit board according to claim 9, comprising two of the substrates but does not teach an adhesive layer that bonds the two substrates together, both of the two substrates being provided with the metal layers on a side away from the adhesive layer.
Thacker et al. does teach an adhesive layer that bonds the two substrates together, both of the two substrates being provided with the metal layers on a side away from the adhesive layer (Fig. 10 and column 2, lines 8-13: underfill material may be an epoxy).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an adhesive layer between the substrates as taught by Thacker et al. because the adhesive layer would promote bonding strength between substrates and the reliability of the package (Thacker et al. column 2, lines 8-13).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. in view of Seo Won Cheol et al., in further view of Thacker et al., in further view of Li et al.
Regarding claim 11, Chiu et al. in view of Seo Won Cheol et al., in further view of Thacker et al. teaches the circuit board according to claim 10, but does not teach a via hole that extends through the two substrates and the adhesive layer, the metal layers on the two substrates being electrically connected through the via hole.
Li et al. does teach a via hole (5) that extends through the two substrates and the adhesive layer, the metal layers on the two substrates being electrically connected through the via hole (Li et al. paragraph 64: via hole 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a via hole that extends through the two substrates and the adhesive layer, the metal layers on the two substrates being electrically connected through the via hole because a via hole would enable electrical connections between the metal layers on the upper and lower substrates (Li et al. paragraph 64).
Allowable Subject Matter
Claims 3 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in the claim that a width of the first slit is less than a width of the second slit.
Regarding claim 13, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in the claim that the second slits within the first regions and the second regions comprise main slits and branch slits, wherein the main slits extend along the row direction or the column direction of the solder pad array, and the branch slits separate the solder pads between the adjacent metal sheets and are connected to the main slits, with one main slit connected to a plurality of the branch slits; extension directions of the main slits within the first regions are perpendicular to extension directions of the main slits within the second regions.
Regarding claim 14, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in the claim that the electronic components are provided on the circuit board and soldered to the corresponding solder pads.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John B Freal whose telephone number is (571)272-4056. The examiner can normally be reached Mon-Fri 7:00-3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN B FREAL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847