DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because: reference characters “24” and “25” have both been used to designate both the insulation layer and the first supporting layer, reference characters “29” and “33” are used in FIG. 10 to label the same layer, reference character “37” is used in FIG. 10 to label a single element of a layer which is not commensurate with the features labeled in FIG. 3-5 or the description of a “display substrate” given in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the plurality of input pins" in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 2 also recites the limitation “a plurality of the second output pins” in both lines 6 and 11. It is unclear from the structure of the claim and the continued use of this phrase whether each recitation of this phrase is a new plurality of the second output pins, or if each recitation refers to the limitation “a plurality of second output pins” from line 4 of the claim.
Claim 3 recites the limitation “the first region” in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 3 further recites the limitation “a plurality of the pins further comprise” in line 3 of the claim. It is unclear whether this phrase refers to a new plurality of the pins or if it refers to “the plurality of the pins” from claim 1. The meets and bounds of the scope of this limitation are unclear because of the conflict between the terms “a plurality” and “further comprise”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jian et al. (US PGPub 20200355972 A1; hereinafter referred to as “Jian’972”).
Re claim 1: Jian’972 teaches a display panel (FIG. 3: el. 100; para. 41), wherein the display panel comprises:
a display substrate (FIG. 3: el. 101), comprising a display region (FIG. 3: el. 20; para. 41) and a peripheral region (FIG. 3: el. 10; para 41) located outside the display region; wherein the peripheral region comprises a bonding region (FIG. 3: el. 40; para. 41); the display substrate specifically comprises: a base substrate (FIG. 3: el. 101), a plurality of fanout lines (FIG. 3: el. 30311; para. 41) which are located on one side of the base substrate in the peripheral region and extend to the bonding region (FIG. 3: el. 30311, 303, 10, 40; para. 41), and a plurality of first bonding electrodes (FIG. 3, 4: el. 611, 621; para. 41) which are electrically connected with the fanout lines in one-to-one correspondence in the bonding region (FIG. 4: el. 30311, 621; para. 41);
a drive chip (FIG. 5: el. 400; para. 41), comprising a drive chip body and a plurality of pins located on one side of the drive chip body facing the display substrate (FIG. 5: el. 400, 411, 412; para. 41); wherein the plurality of the pins comprise a plurality of output pins (FIG. 5: el. 421; para. 47) bonded with the first bonding electrodes in one-to-one correspondence (FIG. 5: el. 421; para. 45: sent. 5);
a supporting structure (FIG. 21: el. 631; para. 93) located between the drive chip body and the base substrate and in contact with both the drive chip body and the base substrate (para. 93); wherein an orthographic projection of the supporting structure on the base substrate and an orthographic projection of a fanout line on the base substrate are not overlapped with each other (FIG. 21: el. 631, 30311; para. 93); an orthographic projection of the supporting structure on the drive chip body and an orthographic projection of a pin on the drive chip body are not overlapped with each other (FIG. 3, 4; FIG. 21: el. 631, 611, 621).
Re claim 2: Jian’972 teaches the display panel according to claim 1, wherein the drive chip body comprises: a first region (FIG. 5: el. 4202; FIG. 21: el. 6202) and a second region located on both sides of the first region (FIG. 5: el. 4201, 4203; FIG. 21: el. 6201, 6203|second regions formed in the area to the left of central regions 4202 or 6202 and to the right of the central regions 4202 or 6202);
the plurality of input pins comprise a plurality of first output pins located in the first region (para. 47: sent. 1; FIG. 5: el. 421, 4202; FIG. 21: el. 6202|output terminals 421 in region 4202) and a plurality of second output pins located in the second region (para. 47: sent. 1; FIG. 5: el. 421, 4201, 4203; FIG. 21: el. 6201, 6203|output terminals 421 in region containing 4201, 4203);
in each first region, a plurality of the first output pins are arranged in at least one row of first output pin rows extending along a first direction (FIG. 21: el. 6202); in each second region, a plurality of the second output pins are arranged into at least one row of second output pin rows (FIG. 21: el. 6201, 6203); the second output pin rows located on both sides of the first region respectively extend along a second direction and a third direction, and the second direction and the third direction are deflected to a side away from the display region relative to the first direction (FIG. 5: el. 4201, 4203; FIG. 21: el. 6201, 6203); in each of the second output pin rows, a plurality of the second output pins are arranged along the second direction or the third direction and toward the side away from the display region (FIG. 5: el. 4201, 4203, 421; FIG. 21: el. 6201, 6203, 621);
an orthographic projection of at least part of the supporting structure on the drive chip body falls into the second region (FIG. 21: el. 631|supporting structure located in orthographic projection of the second region, formed to the sides of the central region 6202).
Re claim 16: Jian’972 teaches a display device (para. 7), wherein the display device comprises a display panel according to claim 1 (para. 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jian’972 in view of Chen et al. (US PGPub 20190148327 A1; hereinafter referred to as “Chen”).
Re claim 3: Jian’972 teaches the display panel according to claim 1, wherein the drive chip body further comprises: a third region located on one side of the first region (FIG. 5; FIG. 21|third region formed in the area below the central regions 4202 and 6202); a plurality of the pins further comprise a plurality of input pins located in the third region (para. 47: sent. 1; FIG. 5: el. 411; FIG. 21|input terminals 411). Jian’972 fails to teach an orthographic projection of at least part of the supporting structure on the drive chip body falls into the third region between an input pin and a first output pin.
In a similar field of endeavor, Chen teaches a drive chip body comprising a third region (FIG. 1|third region formed in the area below the region 120) on one side of the first region (FIG. 1: el. 120|first region formed of central portion of region 120); a plurality of the pins further comprise a plurality of input pins located in the third region (FIG. 1: el. 111, 110; para. 36: sent. 1-2); an orthographic projection of at least part of the supporting structure on the drive chip body falls into the third region between an input pin and a first output pin (FIG. 1: el. 162; para. 53). Chen also teaches that a benefit of including support pins in the region between an input area and an output area is to improve yield by preventing deformation damage of the drive chip during bonding (para. 37, 53).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jian’972 and Chen, to enable using an orthographic projection of at least part of the supporting structure on the drive chip body falling in the third region between an input pin and a first output pin in the display panel of Jian’972 according to the teaching of Chen, for the benefit of improved post-bond drive chip yield.
Re claim 4: The combination of Jian’972 and Chen teaches the display panel according to claim 3. Chen further teaches a region between the input pin and the first output pin comprises a plurality of supporting structure rows (Chen - FIG. 1: el. 162; para. 53); an extension direction of a supporting structure row is the same as that of a first output pin row (Chen - FIG. 1: el. 120, 122, 162|rows of output pins 122 are parallel to rows of supporting structures 162); supporting structures in two adjacent supporting structure rows are arranged in a dislocation manner in the extension direction of the supporting structure row (Chen - FIG. 1: el. 162; para. 53).
Re claim 14: Jian’972 teaches the display panel according to claim 2. Jian’972 fails to teach the display panel wherein a distance between the supporting structure located in the second region and an adjacent fanout line is greater than or equal to 10 microns.
In a similar field of endeavor, Chen teaches a distance between supporting structures and adjacent bond electrodes ranging from 30 μm to 40 μm to ensure adequate support while not leading to a difficulty in alignment (Chen - para. 45-46). Chen also teaches that a lack of adequate support causes deformation in the display substrate which results in breakage of signal lines (Chen - FIG. 6; para. 68). Chen further teaches fan-out signal lines which do not overlap the supporting structures (Chen - FIG. 2: el. 122, 220), fan-out signal lines formed between supporting structures and adjacent bond electrodes (Chen - FIG. 2: el. 122, 220, 121; para. 65: sent. 3|fan-out signal lines 220 between supporting structures 122 and the set of neighboring bond electrodes 121), and that signal lines are prone to break near the edge of supporting structures (Chen - FIG. 5; para. 68). The claimed distance is a result effective variable to reduce the breakage of fan-out signal lines (Chen – para. 46, 68).
In the absence of an indication that the claimed range produces unexpected results or has criticality, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the disclosed distance of greater than 0 μm and less than or equal to 40 μm between the supporting structure and an adjacent fanout line of Chen to achieve the claimed range of greater than 10 μm as a matter of routine optimization.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Jian’972 in view of Dai et al. (CN 111883039 A; hereinafter referred to as “Dai”).
Re claim 5: Jian’972 teaches the display panel according to claim 2. Jian’972 fails to teach the display panel wherein for each second region, a distance between two adjacent supporting structures close to the first region is greater than a distance between two adjacent supporting structures away from the first region.
In a similar field of endeavor, Dai teaches a drive chip of a display panel with output pins (FIG. 9: el. 141; para. 70) in both a central region (FIG. 9: el. 120) of the chip and on both sides of the central region along the exterior of the chip (FIG. 9: el. 110, 130). Dai further teaches a drive chip wherein for each second region (FIG. 9: el. 110, 130) a distance between two adjacent supporting structures close to the first region (FIG. 9: el. 120) is greater than a distance between two adjacent supporting structures away from the first region (FIG. 9: el. 310; para. 72|distance (along x-direction) between adjacent support structures separated by the gap between the 2x2 grid of support structures and the 2x4 grid of support structures is larger than the distance (along the x-direction) between adjacent support structures within the 2x2 grid of support structures). Dai further teaches that this spacing of support structures increases the ease of manufacturing by providing strength to the drive chip with the use of only a few support structures (para. 71).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jian’972 and Dai to enable using the arrangement of supporting structures of Dai in the display panel of Jian’972, for the benefit of increased ease of manufacturing due to a reduction in the number of necessary support structures.
Claims 6, 7, 8, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jian’972 in view of Jian et al. (CN 112037649 A; hereinafter referred to as “Jian’649”).
Re claim 6: Jian’972 teaches the display panel according to claim 1. Jian’972 fails to disclose specific details of the layers which form the features of the bonding region.
In a similar field of endeavor, Jian’649 teaches a display panel with support structures in a bonding region. Jian’649 further teaches a display panel wherein the supporting structure comprises: a first supporting layer (FIG. 19: el. 1101; para. 94); an insulation layer located on a side of the first supporting layer (FIG. 19; para. 94, 95|insulating layer between first support layer 1101 (of metal layer 30) and second support layer 1103 (of transparent conductive layer 50)) facing away from the base substrate (FIG. 19: el. 10); a second supporting layer (FIG. 19: el. 1103; para. 95) located on a side of the insulation layer facing away from the first supporting layer. Jian’649 also teaches that the supporting layers can be formed of the same layers as adjacent fan-out lines and that the structure of the support provided by Jian’649 supplies sufficient support during bonding (para. 94).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jian’972 and Jian’649 to enable using the layered structure of the supporting structure of Jian’649 in the display panel of Jian’972, for the benefit of simplifying the manufacturing process by using a known film stack for forming a support structure which can be processed alongside other bonding region layers and has adequate strength.
Re claim 7: The combination of Jian’972 and Jian’649 teaches the display panel according to claim 6, wherein the supporting structure further comprises: a dummy pin (Jian’649 - FIG. 8: el. 21) located between the drive chip body and the second supporting layer (Jian’649 - FIG. 8: el. 21; para. 65|once bonded, the support structure includes a dummy pin 21 located between the second supporting layer of the support structure 11 and the drive chip body 20).
Re claim 8: The combination of Jian’972 and Jian’649 teaches the display panel according to claim 6, wherein the first supporting layer (Jian’649 - FIG. 19: el. 1101; para. 94) is disposed in a same layer as a fanout line (Jian’649 - FIG. 19: el. 30, 15, 1101; para. 94). The combination of Jian’972 and Jian’649 fails to directly disclose the layered structure of the output bonding pads.
However, Jian’649 teaches the layered structure of the supporting structure (Jian’649 - FIG. 19: el. 11; para 94-95) including an outmost surface (Jian’649 - the surface which contacts the dummy pin 21) being a transparent conductive layer to improve the strength of the pad (Jian’649 - para. 95). Jian’649 further teaches that the support structure (Jian’649 - virtual bonding pads 11) and output bond pads (Jian’649 – output pads 13) can be the same (Jian’649 - para. 63). Therefore, by utilizing the same structure for both the support structure and the output pads, Jian’649 teaches that the second supporting layer (Jian’649 - FIG. 19: el. 1103; para. 95) is disposed in a same layer as a first bonding electrode (outmost layer of the output bond pads 13 of Jian’649 being the first bonding electrode). Jian’649 also teaches that the structure of the supporting structure provided by Jian’649 supplies sufficient support during bonding (para. 94).
It would have been obvious at the time of the effective filling date of the claimed invention to use the layered structure of the embodiment of the supporting structure of Jian’649 as the layered structure of output bonding pad of Jian’649, to enable using the same layer for both the second support structure and the first bonding electrode as taught by Jian’649, and for the benefit of simplifying the manufacturing process by using a known film stack for forming a bond pad with sufficient strength for bonding.
Re claim 12: Jian’972 teaches the display panel according to claim 1. Jian’972 fails to disclose specific details of the layers which form the features of the bonding region.
In a similar field of endeavor, Jian’649 teaches a display panel with support structures in a bonding region. Jian’649 further teaches a display panel wherein the supporting structure comprises: an insulation layer (FIG. 19; para. 94|insulating layer between first support layer 1101 (of metal layer 30) and second support layer 1103 (of transparent conductive layer 50)); and a dummy pin located between the drive chip body and the insulation layer (FIG. 8: el. 21; para. 65|once bonded, the support structure includes a dummy pin 21 located between the insulation layer of the support structure 11 and the drive chip body 20). Jian’649 also teaches that the insulation layer acts to insulate conductive layers in the structure and that the structure of the support provided by Jian’649 supplies sufficient support during bonding (para. 75, 94).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jian’972 and Jian’649 to enable using the layered structure of the supporting structure of Jian’649 in the display panel of Jian’972, for the benefit of simplifying the manufacturing process by using a known film stack for forming a support structure which provides an insulating function and has adequate strength.
Claims 9, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Jian’972 in view of Jian’649 as applied to claim 8 above, and further in view of Li et al. (US PGPub 20190235331 A1; hereinafter referred to as “Li”) and Park et al. (US PGPub 20170336680 A1; hereinafter referred to as “Park”).
Re claim 9: The combination of Jian’972 and Jian’649 teaches the display panel according to claim 8, wherein the display region comprises: a first conductive layer comprising a plurality of scan signal lines (Jian’649 - FIG. 18: el. 14) electrically connected with the fanout lines in one-to-one correspondence (Jian’649 - FIG. 9, 18: el. 14, 15; para. 69). The combination of Jian’972 and Jian’649 fails to disclose the film layers of the display region.
In a similar field of endeavor, Li teaches a display device wherein the display region comprises: a first conductive layer (FIG. 13: el. 11; para. 52) comprising a plurality of scan signal lines (FIG. 13: el. 11; para. 56); a gate insulation layer (FIG. 13: el. 3; para. 52) located on a side of the scan signal lines facing away from the base substrate (FIG. 13: el. 1; para. 52); a pixel electrode layer (FIG. 13: el. 12; para. 69) located on a side of the gate insulation layer facing away from the scan signal lines; a second conductive layer (FIG. 12: el. 8; para. 52) located on a side of the pixel electrode layer facing away from the gate insulation layer and comprising a plurality of data signal lines (para. 52); a protective layer (FIG. 12, 13: el. 16; para. 52) located on a side of the second conductive layer facing away from the pixel electrode layer; a common electrode layer (FIG. 13: el. 17; para. 52) located on a side of the protective layer facing away from the second conductive layer. Li also teaches that the layered structure of the display region disclosed by Li allows for a display panel with a low off-state current (para. 45-49, 75).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jian’972 and Jian’649 with the teachings of Li to enable using the layered structure of the display region of Li in the display panel of the combination of Jian’649 and Jian’972, for the benefit of simplifying the manufacturing process by using a known film stack for forming a display region of a display panel with an improved off-state current.
The combination of Jian’972, Jian’649, and Li fails to directly disclose that the common electrode layer is disposed in a same layer as the second supporting layer and the first bonding electrode.
However, the combination of Jian’972 and Jian’649 teaches that the second supporting layer (Jian’649 - FIG. 19: el. 1103) is formed of indium tin oxide and is formed as an uppermost conductive layer of the bonding region (Jian’649 - FIG. 19: el. 1103; para. 95). Li teaches the common electrode layer as an uppermost conductive layer of the display region (Li - FIG. 13: el. 17; para. 52). Indium tin oxide is well known as a material utilized for common electrodes due to its transparent and conductive properties (Jian’694 - para. 95|properties of ITO given by Jian’649).
Therefore, it would have been obvious to one skilled in the art, absent unexpected results to combine the teachings of the combination of Jian’972 and Jian’649 with the teachings of Li to enable disposing the common electrode in the same layer as the second supporting layer and the first bonding electrode for the benefit of simplifying the manufacturing process by forming an upper layer of the bonding region of the display panel and an upper layer of the display region of the display panel from a same transparent, conductive indium tin oxide layer.
The combination of Jian’972, Jian’649, and Li fails to directly disclose that the insulation layer at least comprises the protective layer extending to the peripheral region.
In a similar field of endeavor, Park teaches a display panel with a display region and a periphery region containing bonding support structures (FIG. 1: el. 129; para. 67). Park further teaches a display panel wherein the insulation layer at least comprises the protective layer (FIG. 87: el. 180; para. 107|portion of FIG. 87 showing A1-A1’ cross-section) extending to the peripheral region (FIG. 1: el. 129; FIG. 87: el. 180). Park also teaches that a purpose of extending the protective layer to the peripheral region is that it functions to protect the data lines and data pad in addition to protecting the transistor (para. 107).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jian’972, Jian’649, and Li with the teachings of Park to enable using the insulation layer comprising the protective layer extended to the periphery region of Park in the display panel of the combination of Jian’972, Jian’649, and Li, for the benefit of protecting signal and/or data lines extending to the peripheral region.
Re claim 10: The combination of Jian’972, Jian’649, Li, and Park teaches the display panel according to claim 9, wherein the fanout lines are disposed in a same layer as the first conductive layer (Jian’649 - FIG. 19: el. 15, 30|fan-out lines 15 in same layer as first conductive layer 30); the insulation layer further comprises the gate insulation layer extending to the peripheral region (Park – FIG. 87: el. 130; para. 248).
Re claim 11: The combination of Jian’972, Jian’649, Li, and Park teaches the display panel according to claim 9, wherein the fanout lines are disposed in a same layer as the second conductive layer (Jian’649 - FIG. 19: el. 15, 40|fan-out lines 15 in same layer as second conductive layer 40); the supporting structure further comprises the gate insulation layer extending to the peripheral region (Park – FIG. 87: el. 130; para. 248).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jian’972 in view of Iwai et al. (US PGPub 20170221934 A1; hereinafter referred to as “Iwai”).
Re claim 13: Jian’972 teaches the display panel according to claim 2. Jian’972 fails to teach the distance between support structures and other features.
In a similar field of endeavor, Iwai teaches a display panel, wherein a distance between an orthographic projection of the supporting structure (FIG. 20: el. 13) located in the second region on the drive chip body and an edge of the drive chip body is less than or equal to 200 microns (FIG. 20: el. 13|supporting structures 13 are 123 μm from the drive chip edge). Iwai also teaches that the use of supporting structures with the disclosed placement allows for known improvements in the uniformity of bonding pressure on features of the drive chip (para. 93-96).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jian’972 with the teachings of Iwai to enable using the placement of support structures close to the drive chip edge of Iwai in the display panel of Jian’972, for the benefit of improving bonding uniformity of the drive chip.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jian’972 in view of Chen as applied to claim 3 above, and further in view of Iwai.
Re claim 15: The combination of Jian’972 and Chen teaches the display panel according to claim 3, wherein the display panel further comprises: a plurality of second bonding electrodes (Chen - para. 67; FIG. 1: el. 111; para. 36: sent. 1-2 |input pins 111 of the drive chip are correspondingly connected to second bonding electrodes 211 of the display substrate), which are located on a same side of the base substrate as the first bonding electrodes (Chen - FIG. 1-2: el. 121, 210; para. 28; para. 36: sent. 1-2; para. 38|output pins 121 of the drive chip are correspondingly connected to first bonding electrodes 210 of the display substrate) in the bonding region; wherein the second bonding electrodes are bonded with the input pins in one-to-one correspondence (Chen - para. 18, 36, 67| input pins 111 of the drive chip are correspondingly electrically connected to second bonding electrodes 211 of the display substrate); a length of a second bonding electrode in an extension direction of a fanout line is larger than a length of an input pin in the extension direction of the fanout line (Chen - para. 20|second bonding electrode 211 is larger than input pin 111 in the manner depicted by the first bonding electrode 210 and the output pin 121 in FIG. 2). Chen also teaches a benefit of the larger dimension of the bonding electrode with respect to the bonding pin is an improved electrical connection due to an increased and reliable contact area (Chen - para. 64). The combination of Jian’972 and Chen fails to disclose the length of the second bonding electrode in the extension direction of the fanout line is greater than or equal to 100 microns and less than or equal to 150 microns.
In a similar field of endeavor, Iwai teaches a display panel with input pins (FIG. 3, 20, 37: el. 11) and output pins (FIG. 3, 20, 37: el. 12) of the drive chip connected to bonding electrodes of the (FIG. 3, 37: el. 160) of the display substrate. Iwai further teaches a display panel, wherein the length of the second bonding electrode (FIG. 37: el. 160) in the extension direction of the fanout line is greater than or equal to 100 microns and less than or equal to 150 microns (FIG. 20: el. 11; FIG. 37: el. 11, 160|input pin 11 has a length of 134 microns in the direction of a fan-out extending from the periphery region to the display region; the cross-section of FIG. 37 shows input pin 11 and the corresponding second bonding electrode 160 with the same dimension). Iwai also teaches that the use of bonding features with the disclosed dimensions and locations allows for known improvements in bonding pressure uniformity of the drive chip bonding features (para. 93-98).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Jian’972 and Chen with the teachings of Iwai, to enable using second bonding electrodes with the dimensions disclosed by Iwai in combination with an input pin having smaller dimensions than the second bonding electrode as disclosed by Chen in the display panel of the combination of Jian’972 and Chen, for the benefit of improving bond uniformity and bond contact area, by using a known pad dimension for improving uniformity in conjunction with a known relation of input pin and bonding electrode dimensions for improving contact area.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898