DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 20 June 2026 have been fully considered but they are not persuasive. Applicant argues that the prior art does not teach, “a distance between an orthographic projection of the supporting structure, which is located in the second region and located between an edge of the drive chip body and the plurality of output pins, on the drive chip body and the edge of the drive chip body is less than or equal to 200 microns,” because the support structure of the prior art is a component of a collection of dummy bumps, wherein the collection of dummy bumps is located between the input bumps and output bumps. This is unpersuasive, as Iwai discloses a support structure which is located between an edge of the drive chip body and the plurality of output pins, in addition to being a component of a collection of dummy bumps which are located between the input bumps and the output bumps, and a distance between an orthographic projection of the supporting structure on the drive chip body and the edge of the drive chip is less than or equal to 200 microns. Further support is found in the § 103 section of this office action.
The prior drawing objection is withdrawn in view of amendments to the drawings. The prior 112(b) rejection is withdrawn in view of amendments to the claims.
Claim Rejections - 35 USC § 112
Claims 3, 4, and 16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation, "an orthographic projection of at least part of the supporting structure on the drive chip body falls into the third region between the plurality of input pins and the plurality of first output pins," in lines 5-7 of the claim. The meets and bounds of this limitation are unclear, as this limitation conflicts with the limitation, “an orthographic projection of the supporting structure, which is located in the second region and located between an edge of the drive chip body and the plurality of output pins, on the drive chip body,” in lines 21-23 of claim 1 on which claim 3 depends. The meets and bounds of the scope of the above limitation of claim 3 are unclear, as the limitation of claim 1 recites the supporting structure is located in the second region, while the limitation of claim 3 recites that part of the supporting structure is located in third region as opposed to the second region. For the purpose of this office action, the above limitation of claim 3 is interpreted to have the following meaning: an orthographic projection of at least part of an additional supporting structure on the drive chip body falls into the third region between the plurality of input pins and the plurality of first output pins.
Claim 4 recites the limitation, "wherein the third region between the plurality of input pins and the plurality of first output pins," in lines 1-2 of the claim. The meets and bounds of this limitation are unclear, as this limitation conflicts with the manner in which the third region was defined in claim 3. Claim 3 defines the third region as including the plurality of input pins, while the above limitation of claim 4 defines the third region as being located between the plurality of input pins and the plurality of first output pins. The meets and bounds of the scope of the limitation are indefinite because of the conflict between the definition of the third region in claim 3 and the definition of the third region in the above limitation of claim 4. For the purpose of this office action, the limitation is interpreted to have the following meaning: wherein the third region.
Claim 16 recites the limitation, “a display panel according to claim 1,” in lines 1-2 of the claim. The meets and bounds of the scope of this limitation are unclear, as it is unclear whether this limitation draws antecedent basis from claim 1. The meets and bounds of the scope of this limitation unclear, due to the apparent conflict between the phrase “a display panel” and the phrase “according to claim 1”. For the purpose of this office action, the limitation is interpreted to have the following meaning: the display panel according to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jian et al. (US PGPub 20200355972 A1; hereinafter referred to as “Jian’972”) in view of Iwai et al. (US PGPub 20170221934 A1; hereinafter referred to as “Iwai”).
Re claim 1: Jian’972 teaches a display panel (FIG. 3: el. 100; para. 41), wherein the display panel comprises:
a display substrate (FIG. 3: el. 101), comprising a display region (FIG. 3: el. 20; para. 41) and a peripheral region (FIG. 3: el. 10; para 41) located outside the display region; wherein the peripheral region comprises a bonding region (FIG. 3: el. 40; para. 41); the display substrate specifically comprises: a base substrate (FIG. 3: el. 101), a plurality of fanout lines (FIG. 3: el. 30311; para. 41) which are located on one side of the base substrate in the peripheral region and extend to the bonding region (FIG. 3: el. 30311, 303, 10, 40; para. 41), and a plurality of first bonding electrodes (FIG. 3, 4: el. 611, 621; para. 41) which are electrically connected with the plurality of fanout lines in one-to-one correspondence in the bonding region (FIG. 4: el. 30311, 621; para. 41); a drive chip (FIG. 5: el. 400; para. 41), comprising a drive chip body and a plurality of pins located on one side of the drive chip body facing the display substrate (FIG. 5: el. 400, 411, 412; para. 41); wherein the plurality of pins comprise a plurality of output pins (FIG. 5: el. 421; para. 47) bonded with the plurality of first bonding electrodes in one-to-one correspondence (FIG. 5: el. 421; para. 45: sent. 5); and a supporting structure (FIG. 21: el. 631; para. 93) located between the drive chip body and the base substrate and in contact with both the drive chip body and the base substrate (para. 93); wherein an orthographic projection of the supporting structure on the base substrate and an orthographic projection of the plurality of fanout lines on the base substrate are not overlapped with each other (FIG. 21: el. 631, 30311; para. 93); an orthographic projection of the supporting structure on the drive chip body and an orthographic projection of the plurality of pins on the drive chip body are not overlapped with each other (FIG. 3, 4; FIG. 21: el. 631, 611, 621); wherein the drive chip body comprises: a first region (FIG. 5: el. 4202; FIG. 21: el. 6202) and a second region located on each of two sides of the first region (FIG. 5: el. 4201, 4203; FIG. 21: el. 6201, 6203|second regions formed in the area to the left of central regions 4202 or 6202 and to the right of the central regions 4202 or 6202). Jian’972 fails to teach a distance between an orthographic projection of the supporting structure, which is located in the second region and located between an edge of the drive chip body and the plurality of output pins, on the drive chip body and the edge of the drive chip body is less than or equal to 200 microns.
In a similar field of endeavor, Iwai teaches a display panel (para. abstract), wherein a distance between an orthographic projection of the supporting structure, which is located in the second region and located between an edge of the drive chip body and the plurality of output pins (annotated FIG. 20: el. supporting structure, edge| annotated FIG. 20, provided below, labels the supporting structure, which is one of the dummy bumps 13 and which, as shown by the dotted line connecting the relevant elements, is located in a second region and is located between an edge of the drive chip body and the output pins 12), on the drive chip body and the edge of the drive chip body is less than or equal to 200 microns (annotated FIG. 20: el. supporting structure, edge| annotated FIG. 20, provided below, labels the supporting structure which is 123 μm from the drive chip edge; Iwai specifically discloses that the distance is 123 μm, and as per MPEP 2131.03(i), "if the prior art discloses a point within the claimed range, the prior art anticipates the claim"). Iwai also teaches that the use of dummy bumps and supporting structure with the disclosed placement allows for known improvements in the uniformity of bonding pressure on features of the drive chip (para. 93-96).
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Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jian’972 with the teachings of Iwai to enable using the placement of support structures close to the drive chip edge of Iwai in the display panel of Jian’972, for the benefit of improving bonding uniformity of the drive chip.
Re claim 2: The combination of Jian’972 and Iwai teaches the display panel according to claim 1, wherein the plurality of output pins comprise a plurality of first output pins located in the first region (Jian’927 - para. 47: sent. 1; FIG. 5: el. 421, 4202; FIG. 21: el. 6202|output terminals 421 in region 4202) and a plurality of second output pins located in the second region (Jian’927 - para. 47: sent. 1; FIG. 5: el. 421, 4201, 4203; FIG. 21: el. 6201, 6203|output terminals 421 in region containing 4201, 4203);
in the first region, the plurality of first output pins are arranged in at least one row of first output pin rows extending along a first direction (Jian’927 - FIG. 21: el. 6202); in the second region, the plurality of second output pins are arranged into at least one row of second output pin rows (Jian’927 - FIG. 21: el. 6201, 6203); the second output pin rows located on both sides of the first region respectively extend along a second direction and a third direction, and the second direction and the third direction are deflected to a side away from the display region relative to the first direction (Jian’927 - FIG. 5: el. 4201, 4203; FIG. 21: el. 6201, 6203); in each of the second output pin rows, the plurality of second output pins are arranged along the second direction or the third direction and toward the side away from the display region (Jian’927 - FIG. 5: el. 4201, 4203, 421; FIG. 21: el. 6201, 6203, 621);
an orthographic projection of at least part of the supporting structure on the drive chip body falls into the second region (Jian’927 - FIG. 21: el. 631|supporting structure located in orthographic projection of the second region, formed to the sides of the central region 6202).
Re claim 3: The combination of Jian’972 and Iwai teaches the display panel according to claim 2, wherein the drive chip body further comprises: a third region located on one side of the first region (Jian’972 - FIG. 5; FIG. 21|third region formed in the area below the central regions 4202 and 6202); the plurality of pins further comprise a plurality of input pins located in the third region (Jian’972 - para. 47: sent. 1; FIG. 5: el. 411; FIG. 21|input terminals 411); an orthographic projection of at least part of an additional supporting structure on the drive chip body falls into the third region between the plurality of input pins and the plurality of first output pins (Iwai – annotated FIG. 20: el. additional supporting structure| annotated FIG. 20, provided below, labels the additional supporting structure between plurality of input pins and plurality of first output pins of the first region).
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Re claim 16: The combination of Jian’972 and Iwai teaches a display device (Jian’972 - para. 7), wherein the display device comprises the display panel according to claim 1 (Jian’972 - para. 7).
Claims 4, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Jian’972 in view of Iwai as applied to claims 2 and 3 above, and further in view of Chen et al. (US PGPub 20190148327 A1; hereinafter referred to as “Chen”).
Re claim 4: The combination of Jian’972 and Iwai fails to teach the display panel according to claim 3, wherein the third region comprises a plurality of supporting structure rows; an extension direction of the plurality of supporting structure rows is the same as that of the first output pin rows; supporting structures in two adjacent supporting structure rows are arranged in a dislocation manner in the extension direction of the plurality of supporting structure rows.
In a similar field of endeavor, Chen teaches a drive chip body comprising a third region (FIG. 1|third region formed in the area below the region 120) on one side of the first region (FIG. 1: el. 120|first region formed of central portion of region 120); a plurality of the pins further comprise a plurality of input pins located in the third region (FIG. 1: el. 111, 110; para. 36: sent. 1-2); wherein the third region comprises a plurality of supporting structure rows (Chen - FIG. 1: el. 162; para. 53); an extension direction of the plurality of supporting structure rows is the same as that of the first output pin rows (Chen - FIG. 1: el. 120, 122, 162|rows of output pins 122 in a first central region are parallel to rows of supporting structures 162); supporting structures in two adjacent supporting structure rows are arranged in a dislocation manner in the extension direction of the plurality of supporting structure rows (Chen - FIG. 1: el. 162; para. 53). Chen also teaches that a benefit of evenly spacing supporting structures in supporting structure rows in a region between output pins and input pins is to make the force on the drive chip balanced, in order to prevent the drive chip from being deformed and damaged (para. 53).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Jian’972 and Iwai with the teachings of Chen, to enable using a plurality of supporting structure rows in the third region as taught by Chen in the display panel of the combination of Jian’972 and Iwai, for the benefit of preventing damage and deformation of a drive chip by balancing force applied to the drive chip.
Re claim 14: The combination of Jian’972 and Iwai fails to teach the display panel according to claim 2, wherein a distance between the supporting structure located in the second region and an adjacent fanout line is greater than or equal to 10 microns.
In a similar field of endeavor, Chen teaches a distance between supporting structures and adjacent bond electrodes ranging from 30 μm to 40 μm to ensure adequate support while not leading to a difficulty in alignment (Chen - para. 45-46). Chen also teaches that a lack of adequate support causes deformation in the display substrate which results in breakage of signal lines (Chen - FIG. 6; para. 68). Chen further teaches fan-out signal lines which do not overlap the supporting structures (Chen - FIG. 2: el. 122, 220), fan-out signal lines formed between supporting structures and adjacent bond electrodes (Chen - FIG. 2: el. 122, 220, 121; para. 65: sent. 3|fan-out signal lines 220 between supporting structures 122 and the set of neighboring bond electrodes 121), and that signal lines are prone to break near the edge of supporting structures (Chen - FIG. 5; para. 68). The claimed distance between the supporting structure of the second region and an adjacent fanout line is a result effective variable to reduce the breakage of fan-out signal lines (Chen – para. 46, 68).
In the absence of an indication that the claimed range produces unexpected results or has criticality, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the disclosed distance of greater than 0 μm and less than or equal to 40 μm between the supporting structure and an adjacent fanout line of Chen to achieve the claimed range of greater than 10 μm as a matter of routine optimization. Furthermore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Jian’972 and Iwai with the teachings of Chen, to enable using the distance between supporting structures and adjacent fanout lines of Chen in the display panel of the combination of Jian’972 and Iwai, for the benefit of providing adequate support while not leading to a difficulty in alignment and the benefit of reducing signal line breakage.
Re claim 15: The combination of Jian’972 and Iwai teaches the display panel according to claim 3, wherein the display panel further comprises: a plurality of second bonding electrodes (Iwai – FIG. 3: el. 160: para. 60|second bonding electrodes formed of the collection of terminals 160 connected to input pins 11), which are located on a same side of the base substrate as the plurality of first bonding electrodes in the bonding region (Iwai – FIG. 3: el. 160; para. 60| first bonding electrodes 160 (connected to output pins 12) formed on same side of base substrate 100 as second bonding electrodes 160 (connected to input pins 11)); wherein the plurality of second bonding electrodes are bonded with the plurality of input pins in one-to- one correspondence (Iwai – FIG. 3: el. 160: para. 60|second bonding electrodes formed of the collection of terminals 160 connected to input pins 11); the length of the second bonding electrode (Iwai - FIG. 37: el. 160) in the extension direction of the fanout line is greater than or equal to 100 microns and less than or equal to 150 microns (Iwai - FIG. 20: el. 11; FIG. 3: el. 11, 160|input pin 11 has a length of 134 microns in the direction of a fan-out extending from the periphery region to the display region; the cross-section of FIG. 3 shows second bonding electrode 160 with the same dimension as corresponding input pin 11; Iwai also teaches that the use of bonding features with the disclosed dimensions and locations allows for known improvements in bonding pressure uniformity of the drive chip bonding features (Iwai - para. 93-98)). The combination of Jian’972 and Iwai fails to teach a length of a second bonding electrode of the plurality of second bonding electrodes in an extension direction of a fanout line of the plurality of fanout lines is larger than a length of an input pin of the plurality of input pins in the extension direction of the fanout line.
In a similar field of endeavor, Chen teaches a length of a second bonding electrode of the plurality of second bonding electrodes in an extension direction of a fanout line of the plurality of fanout lines is larger than a length of an input pin of the plurality of input pins in the extension direction of the fanout line (Chen - para. 20|second bonding electrode 211 is larger than input pin 111 in the manner depicted by the first bonding electrode 210 and the output pin 121 in FIG. 2). Chen also teaches a benefit of the larger dimension of the bonding electrode with respect to the bonding pin is an improved electrical connection due to an increased and reliable contact area (Chen - para. 64).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Jian’972 and Iwai with the teachings of Chen, to enable using second bonding electrodes with the dimensions disclosed by Iwai in combination with an input pin having smaller dimensions than the second bonding electrode as disclosed by Chen in the display panel of the combination of Jian’972 and Iwai, for the benefit of improving bond uniformity and bond contact area, by using a known pad dimension for improving drive chip bond uniformity in conjunction with a known relation of input pin and bonding electrode dimensions for improving alignment and contact area.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Jian’972 in view of Iwai as applied to claim 2 above, and further in view of Dai et al. (CN 111883039 A; hereinafter referred to as “Dai”).
Re claim 5: The combination of Jian’972 and Iwai fails to teach the display panel according to claim 2, wherein for the second region, a distance between two adjacent supporting structures close to the first region is greater than a distance between two adjacent supporting structures away from the first region.
In a similar field of endeavor, Dai teaches a drive chip of a display panel with output pins (FIG. 9: el. 141; para. 70) in both a central region (FIG. 9: el. 120) of the chip and on both sides of the central region along the exterior of the chip (FIG. 9: el. 110, 130). Dai further teaches a drive chip wherein for the second region (FIG. 9: el. 110, 130) a distance between two adjacent supporting structures close to the first region (FIG. 9: el. 120) is greater than a distance between two adjacent supporting structures away from the first region (FIG. 9: el. 310; para. 72|distance (along x-direction) between adjacent support structures separated by the gap between the 2x2 grid of support structures and the 2x4 grid of support structures is larger than the distance (along the x-direction) between adjacent support structures within the 2x2 grid of support structures). Dai further teaches that this spacing of support structures increases the ease of manufacturing by providing strength to the drive chip with the use of only a few support structures (para. 71).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Jian’972 and Iwai with the teachings of Dai to enable using the arrangement of supporting structures of Dai in the display panel of the combination of Jian’972 and Iwai, for the benefit of increased ease of manufacturing due to a reduction in the number of necessary support structures.
Claims 6, 7, 8, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jian’972 in view of Iwai as applied to claim 1 above, and further in view of Jian et al. (CN 112037649 A; hereinafter referred to as “Jian’649”).
Re claim 6: The combination Jian’972 and Iwai teaches the display panel according to claim 1. The combination of Jian’972 and Iwai fails to disclose specific details of the layers which form the supporting structures of the bonding region.
In a similar field of endeavor, Jian’649 teaches a display panel with support structures in a bonding region. Jian’649 further teaches a display panel wherein the supporting structure comprises: a first supporting layer (FIG. 19: el. 1101; para. 94); an insulation layer located on a side of the first supporting layer (FIG. 19; para. 94, 95|insulating layer between first support layer 1101 (of metal layer 30) and second support layer 1103 (of transparent conductive layer 50)) facing away from the base substrate (FIG. 19: el. 10); a second supporting layer (FIG. 19: el. 1103; para. 95) located on a side of the insulation layer facing away from the first supporting layer. Jian’649 also teaches that the supporting layers can be formed of the same layers as adjacent fan-out lines and that the structure of the support provided by Jian’649 supplies sufficient support during bonding (para. 94).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Jian’972 and Iwai with the teachings of Jian’649 to enable using the layered structure of the supporting structure of Jian’649 in the display panel of the combination of Jian’972 and Iwai, for the benefit of simplifying the manufacturing process by using a known film stack for forming a support structure which can be processed alongside other bonding region layers and has adequate strength.
Re claim 7: The combination of Jian’972, Iwai, and Jian’649 teaches the display panel according to claim 6, wherein the supporting structure further comprises: a dummy pin (Jian’649 - FIG. 8: el. 21) located between the drive chip body and the second supporting layer (Jian’649 - FIG. 8: el. 21; para. 65|once bonded, the support structure includes a dummy pin 21 located between the second supporting layer of the support structure 11 and the drive chip body 20).
Re claim 8: The combination of Jian’972, Iwai, and Jian’649 teaches the display panel according to claim 6, wherein the first supporting layer (Jian’649 - FIG. 19: el. 1101; para. 94) is disposed in a same layer as the plurality of fanout lines (Jian’649 - FIG. 19: el. 30, 15, 1101; para. 94). The combination of Jian’972, Iwai, and Jian’649 fails to directly disclose the layered structure of the output bonding pads.
However, Jian’649 teaches the layered structure of the supporting structure (Jian’649 - FIG. 19: el. 11; para 94-95) including an outmost surface (Jian’649 - the surface which contacts the dummy pin 21) being a transparent conductive layer to improve the strength of the pad (Jian’649 - para. 95). Jian’649 further teaches that the support structure (Jian’649 - virtual bonding pads 11) and output bond pads (Jian’649 – output pads 13) can be the same (Jian’649 - para. 63). Therefore, by utilizing the same structure for both the support structure and the output pads, Jian’649 teaches that the second supporting layer (Jian’649 - FIG. 19: el. 1103; para. 95) is disposed in a same layer as the plurality of first bonding electrodes (outmost layer of the output bond pads 13 of Jian’649 being the first bonding electrodes). Jian’649 also teaches that the structure of the supporting structure provided by Jian’649 supplies sufficient support during bonding (Jian’649 - para. 94).
It would have been obvious at the time of the effective filling date of the claimed invention to use the layered structure of the embodiment of the supporting structure of Jian’649 as the layered structure of output bonding pad of Jian’649, to enable using the same layer for both the second support structure and the first bonding electrodes as taught by the combination of Jian’972, Iwai, and Jian’649, and for the benefit of simplifying the manufacturing process by using a known film stack for forming a bond pad with sufficient strength for bonding.
Re claim 12: The combination of Jian’972 and Iwai teaches the display panel according to claim 1. The combination of Jian’972 and Iwai fails to disclose specific details of the layers which form the features of the bonding region.
In a similar field of endeavor, Jian’649 teaches a display panel with support structures in a bonding region. Jian’649 further teaches a display panel wherein the supporting structure comprises: an insulation layer (FIG. 19; para. 94|insulating layer between first support layer 1101 (of metal layer 30) and second support layer 1103 (of transparent conductive layer 50)); and a dummy pin located between the drive chip body and the insulation layer (FIG. 8: el. 21; para. 65|once bonded, the support structure includes a dummy pin 21 located between the insulation layer of the support structure 11 and the drive chip body 20). Jian’649 also teaches that the insulation layer acts to insulate conductive layers in the structure and that the structure of the support provided by Jian’649 supplies sufficient support during bonding (para. 75, 94).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Jian’972 and Iwai with the teachings of Jian’649 to enable using the layered structure of the supporting structure of Jian’649 in the display panel of the combination of Jian’972 and Iwai, for the benefit of simplifying the manufacturing process by using a known film stack for forming a support structure which provides an insulating function and has adequate strength.
Claims 9, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Jian’972 in view of Iwai and Jian’649 as applied to claim 8 above, and further in view of Li et al. (US PGPub 20190235331 A1; hereinafter referred to as “Li”) and Park et al. (US PGPub 20170336680 A1; hereinafter referred to as “Park”).
Re claim 9: The combination of Jian’972, Iwai, and Jian’649 teaches the display panel according to claim 8, wherein the display region comprises: a first conductive layer comprising a plurality of scan signal lines (Jian’649 - FIG. 18: el. 14) electrically connected with the plurality of fanout lines in one-to-one correspondence (Jian’649 - FIG. 9, 18: el. 14, 15; para. 69). The combination of Jian’972 and Jian’649 fails to disclose the film layers and arrangement of layers of the display region.
In a similar field of endeavor, Li teaches a display device wherein the display region comprises: a first conductive layer (FIG. 13: el. 11; para. 52) comprising a plurality of scan signal lines (FIG. 13: el. 11; para. 56); a gate insulation layer (FIG. 13: el. 3; para. 52) located on a side of the plurality of scan signal lines facing away from the base substrate (FIG. 13: el. 1; para. 52); a pixel electrode layer (FIG. 13: el. 12; para. 69) located on a side of the gate insulation layer facing away from the plurality of scan signal lines; a second conductive layer (FIG. 12: el. 8; para. 52) located on a side of the pixel electrode layer facing away from the gate insulation layer and comprising a plurality of data signal lines (para. 52); a protective layer (FIG. 12, 13: el. 16; para. 52) located on a side of the second conductive layer facing away from the pixel electrode layer; a common electrode layer (FIG. 13: el. 17; para. 52) located on a side of the protective layer facing away from the second conductive layer. Li also teaches that the layered structure of the display region disclosed by Li allows for a display panel with a low off-state current (para. 45-49, 75).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Jian’972, Iwai, and Jian’649 with the teachings of Li to enable using the layered structure of the display region of Li in the display panel of the combination of Jian’972, Iwai, and Jian’649, for the benefit of simplifying the manufacturing process by using a known film stack for forming a display region of a display panel with an improved off-state current.
The combination of Jian’972, Iwai, Jian’649, and Li fails to directly disclose that the common electrode layer is disposed in a same layer as the second supporting layer and the plurality of first bonding electrodes.
However, the combination of Jian’972, Iwai, and Jian’649 teaches that the second supporting layer (Jian’649 - FIG. 19: el. 1103) is formed of indium tin oxide and is formed as an uppermost conductive layer of the bonding region (Jian’649 - FIG. 19: el. 1103; para. 95). Li teaches the common electrode layer as an uppermost conductive layer of the display region (Li - FIG. 13: el. 17; para. 52). Indium tin oxide is well known as a material utilized for common electrodes due to its transparent and conductive properties (Jian’694 - para. 95|properties of ITO given by Jian’649).
Therefore, it would have been obvious to one skilled in the art, absent unexpected results to combine the teachings of the combination of Jian’972, Iwai, and Jian’649 with the teachings of Li to enable disposing the common electrode in the same layer as the second supporting layer and the plurality of first bonding electrodes for the benefit of simplifying the manufacturing process by forming an upper layer of the bonding region of the display panel and an upper layer of the display region of the display panel from a same transparent, conductive indium tin oxide layer.
The combination of Jian’972, Iwai, Jian’649, and Li fails to directly disclose that the insulation layer at least comprises the protective layer extending to the peripheral region.
In a similar field of endeavor, Park teaches a display panel with a display region and a periphery region containing bonding support structures (FIG. 1: el. 129; para. 67). Park further teaches a display panel wherein the insulation layer at least comprises the protective layer (FIG. 87: el. 180; para. 107|portion of FIG. 87 showing A1-A1’ cross-section) extending to the peripheral region (FIG. 1: el. 129; FIG. 87: el. 180). Park also teaches that a purpose of extending the protective layer to the peripheral region is that it functions to protect the data lines and data pad in addition to protecting the transistor (para. 107).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jian’972, Iwai, Jian’649, and Li with the teachings of Park to enable using the insulation layer comprising the protective layer extended to the periphery region of Park in the display panel of the combination of Jian’972, Iwai, Jian’649, and Li, for the benefit of protecting signal and/or data lines extending to the peripheral region.
Re claim 10: The combination of Jian’972, Iwai, Jian’649, Li, and Park teaches the display panel according to claim 9, wherein the plurality of fanout lines are disposed in a same layer as the first conductive layer (Jian’649 - FIG. 19: el. 15, 30|fan-out lines 15 in same layer as first conductive layer 30); the insulation layer further comprises the gate insulation layer extending to the peripheral region (Park – FIG. 87: el. 130; para. 248).
Re claim 11: The combination of Jian’972, Iwai, Jian’649, Li, and Park teaches the display panel according to claim 9, wherein the plurality of fanout lines are disposed in a same layer as the second conductive layer (Jian’649 - FIG. 19: el. 15, 40|fan-out lines 15 in same layer as second conductive layer 40); the supporting structure further comprises the gate insulation layer extending to the peripheral region (Park – FIG. 87: el. 130; para. 248).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.G./ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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