Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding claims 1-3, 5-13 rejected under 35 U.S.C. 112(b), applicant amendment has been fully considered. However, the amendment introduces new indefiniteness. Hence the 35 U.S.C. 112(b) rejection is maintained for claims 1-3, 5-13.
Applicant's arguments filed on 06/01/2026 have been fully considered but they are not persuasive. Applicant argues that Akimoto discloses only a single opening for each electrode. However, claim 1 does not limit the recited semiconductor element to a single light-emitting chip or require only one semiconductor layer or electrode pair. Under broadest reasonable interpretation, Akimoto’s structure shown in Fig. 3B, including substrate 10, the plurality of semiconductor layers 15, repeated second openings 18b, and corresponding vertical portions extending through the respective openings, teaches the claimed plural-opening arrangement. Akimoto expressly describes a plurality of openings 18a and 18b formed in insulating layer 18.
Applicant’s reliance on the disclosed adhesion advantage is not persuasive because claim 1 does not require improved adhesion or require that the plurality of conduction portions be provided for that purpose. The prior art need not recognize the same advantage identified by applicant where the claimed structure is otherwise disclosed or suggested.
The office agrees that Akimoto’s figures are not drawn to scale and does not rely on measuring the drawing to establish a precise numerical area. The rejection, however, was made under 35 U.S.C. 103, and the office action provided a rationale explaining why it would have been obvious to provide at least one second opening having a smaller plan-view area than first opening 18a. Merely pointing out that the drawings are not drawn to scale does not address that obviousness rationale. Further, claim 1 does not require a particular numerical area, shape, or degree by which the second opening must be smaller. Akimoto teaches than n-side electrode 17 and second region 15c are smaller than p-side electrode 16 and first region 15b. Accordingly, selecting at least one second opening smaller than first opening 18a would have been an obvious contact-opening design consistent with the respective available contact regions.
Applicant’s argument regarding the height relationship between openings 18a and 18b is not commensurate with the claim, which compares the heights of the first and second thick-film electrodes. Akimoto teaches that n-side electrode 17 is lower than p-side electrode 16, while the mounting-side surfaces of pillars 23 and 24 are at substantially the same level. The n-side conductive structure therefore extends farther to reach lower electrode 17 and has a greater height under the measurement recited in amended claim 1.
Claim Objections
Claim 5 is objected to because of the following informalities:
Claim 5 recites “…a total area of all of the plurality second through-holes…”. The claim should recite “…a total area of all of the plurality of second through-holes…”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “…the height of the second thick-film electrode is measured from a surface of the second thick-film electrode opposite to the substrate to a surface of the plurality of second conduction portions adjacent to the substrate…”. This is unclear because the second thick-film electrode includes a plurality of second conduction portions, each of which may have a respective substrate-adjacent surface. However, the claim does not require the respective substrate-adjacent surfaces to be coplanar or specify whether the height is measured to the surface of each second conduction portion, a selected one of the second conduction portions, etc. For the purpose of examination, this limitation is interpretated as requiring the height of the second thick-film electrode to be measured from its uppermost substrate-opposing surface to the substrate-adjacent surface of each of the plurality of second conduction portions.
Claim 2 recites “…wherein 2d>w2 holds when d is a dimension of the plurality of second conduction portions in the direction perpendicular to the main surface of the substrate and w2 is a dimension of the plurality of second conduction portions in a direction parallel to the main surface of the substrate”. This is indefinite because the claim assigns dimension a single dimension d and a single dimension w2 to the “plurality of second conduction portions”, but does not specify whether d and w2 refer to the respective dimensions of each of the plurality of second conduction portions, or the dimensions of at least one selected second conduction portion, or the minimum, maximum or average dimensions of the plurality, or collective dimensions measured across the plurality of second conduction portions. For the purpose of examination, claim 2 is interpretated as requiring that the relationship 2d>w2 is satisfied by each of the plurality of second conduction portions.
Claim 6 recites “…the height of the second thick-film electrode is measured from a surface of the second thick-film electrode opposite to the substrate to a surface of the plurality of second conduction portions adjacent to the substrate…”. This is unclear because the second thick-film electrode includes a plurality of second conduction portions, each of which may have a respective substrate-adjacent surface. However, the claim does not require the respective substrate-adjacent surfaces to be coplanar or specify whether the height is measured to the surface of each second conduction portion, a selected one of the second conduction portions, etc. For the purpose of examination, this limitation is interpretated as requiring the height of the second thick-film electrode to be measured from its uppermost substrate-opposing surface to the substrate-adjacent surface of each of the plurality of second conduction portions.
Claim 7 recites “…the height of the second thick-film electrode is measured from a surface of the second thick-film electrode opposite to the substrate to a surface of the plurality of second conduction portions adjacent to the substrate…”. This is unclear because the second thick-film electrode includes a plurality of second conduction portions, each of which may have a respective substrate-adjacent surface. However, the claim does not require the respective substrate-adjacent surfaces to be coplanar or specify whether the height is measured to the surface of each second conduction portion, a selected one of the second conduction portions, etc. For the purpose of examination, this limitation is interpretated as requiring the height of the second thick-film electrode to be measured from its uppermost substrate-opposing surface to the substrate-adjacent surface of each of the plurality of second conduction portions.
Dependent Claims 2-3, 5 and 8-13 are rejected under 35 U.S.C. 112(b) since they inherit the indefiniteness of the claims from which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-8, 10, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Akimoto (US 20110300644 A1) in view of Miki (US 20200044128 A1).
Re: Independent Claim 1 (Currently amended), Akimoto discloses a semiconductor element comprising:
a substrate having a laminated structure including a semiconductor layer (Akimoto teaches, in Fig 3A-3B and ¶ [0017], substrate 10 and has stacked/laminated semiconductor structure i.e., semiconductor layer 15 (layers 11/12/13/16/17 stacked)), the substrate having a first region (Akimoto teaches, in Figs. 2A-2C and 3A-3B, light-emitting region, i.e., first region 15b) and a second region lower than the first region on a main surface (Akimoto teaches, in Fig 3A-3B and ¶ [0017], non-light emitting region i.e., second region 15c is at lower level than first region 15b on main surface 15);
an insulating film (Fig 3A-3B, insulating layer 18) covering the first region and the second region, the insulating film having a first through-hole provided in the first region (Figs. 2A-2C and 3A-3B, first through hole 18a in first region 15b) and a plurality of second through- holes provided in the second region (Figs. 2A-2C and 3A-3B, second through hole 18b in second region 15c. Akimoto, in Fig. 3A, teaches repeated second through holes 18b are provided in the insulating film 18 in the second region, hence teaches plurality of second through holes 18b);
a first thick-film electrode provided in the first region and extending in a normal direction of the main surface (Figs. 3A-3B and ¶ [0020], p-side interconnect layer 21 is the corresponding first thick-film electrode in the first region 15b, which extends in the normal (vertical) direction of the main surface), the first thick-film electrode including a first conduction portion extending through the first through-hole and reaching the substrate (Figs. 3A-3B and ¶ [0020], the portion of 21 formed inside opening 18a extends through the opening 18a and reaches the substrate, since the p-side electrode 16 is provided on the stacked body/semiconductor layer 15 (i.e., the claimed substrate having a laminated structure including semiconductor layers); and
a second thick-film electrode provided in the second region and extending in the normal direction of the main surface (Figs. 3A-3B and ¶ [0020], n-side interconnect layer 22 is the corresponding second thick-film electrode in the second region 15c, which extends in the normal (vertical) direction of the main surface), the second thick-film electrode including a plurality of second conduction portions extending through a respective one of the plurality of second through-holes and reaching the substrate (Figs. 3A-3B and ¶ [0020], the portion of 22 formed inside opening 18b extends through the opening 18b and reaches the substrate, since the n-side electrode 17 is provided on the stacked body/semiconductor layer 15 (i.e., the claimed substrate having a laminated structure including semiconductor layers). In the repeated second through-holes form the repeated second conductor portions, i.e., each second thick-film electrode 22 includes a horizontal portion and a vertical portion extending through 18b as shown in Akimoto’s Fig. 3A, where the repeated vertical portions is the claimed plurality of second conductive portions),
a height of the second thick-film electrode is greater than a height of the first thick-film electrode, the height of the second thick-film electrode is measured from a surface of the second thick-film electrode opposite to the substrate to a surface of the plurality of second conduction portions adjacent to the substrate, and the height of the first thick-film electrode is measured from a surface of the first thick-film electrode opposite to the substrate to a surface of the first conduction portion adjacent to the substrate (Figs. 3B, the substrate-opposing surfaces of p-side metal pillar 23 and n-side metal pillar 24 are exposed at substantially the same mounting-side level, while the lower surface of interconnect layer 21 contacts p-side electrode 16 and the lower surface of the interconnect layer 22 contacts n-side electrode 17. Because n-side electrode 17 is positioned lower than p-side electrode 16, the distance measured from the upper surface of n-side metal pillar 24 to the lower surface of the interconnect layer 22 is greater than the corresponding distance measured from the upper surface of p-side metal pillar 23 to the lower surface of interconnect layer 21).
Akimoto doesn’t explicitly disclose
an area of at least one of the plurality of second through-holes is smaller than an area of the first through-hole when viewed from a direction perpendicular to the main surface of the substrate.
However, Akimoto teaches, in Fig. 3A, that an area of second through-hole 18b measured from its base up to an intermediate level (e.g., level of layer 16) is an area of 18b that is smaller than the area of first through-hole 18a. The claim does not specify which elevation/portion of the through-hole defines the "area", thus "an area of the through-hole" reasonably encompasses the area of the void at a portion of the through-hole (e.g., from the hole base up to an intermediate region). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to realize an area of second through-hole smaller than an area of first through-hole as impliedly taught by Akimoto in order to promote more favorable Cu plating on the sidewalls (Akimoto, 1 [0047]).
Re: Claim 2 (Currently amended), Akimoto discloses all the limitations of claim 1 on which this claim depends.
Akimoto further teach
wherein 2d>w2 holds when d is a dimension of the plurality of second conduction portions in the direction perpendicular to the main surface of the substrate and w2 is a dimension of the plurality of second conduction portions in a direction parallel to the main surface of the substrate (Akimoto teaches, in Figs. 3A-3B, dimension of the plurality of second conductive portions 22 inside the openings 18b has narrow width and longer height (width corresponds to the claimed w2 and height corresponds to the claimed d). Thus, in Fig. 3A, height of 18b (claimed d)>width of 18b (claimed w2), which make its obvious that 2d>w2).
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Re: Claim 5 (Currently amended), Akimoto discloses all the limitations of claim 1 on which this claim depends.
Akimoto further teaches
Wherein a total area of all of the plurality second through-holes is smaller than the area of the first through-hole when viewed from the direction perpendicular to the main surface of the substrate (As shown in Akimoto’s Fig. 3A (annotated) above, total areas for the portion A1 of second through holes is smaller than the area of the first through hole 18a when viewed from the direction perpendicular to the main surface of the substrate).
Re: Independent Claim 6 (Currently amended), Akimoto discloses a method for manufacturing a semiconductor element including steps of:
preparing a substrate having a laminated structure including a semiconductor layer (Akimoto teaches, in Fig 3A-3B and ¶ [0017], substrate 10 and has stacked/laminated semiconductor structure i.e., semiconductor layer 15 (layers 11/12/13/16/17 stacked)), the substrate having a first region (Akimoto teaches, in Fig 3A-3B, light-emitting region, i.e., first region 15b) and a second region lower than the first region on a main surface (Akimoto teaches, in Fig 3A-3B and ¶ [0017], non-light emitting region i.e., second region 15c is at lower level than first region 15b on main surface 15);
forming an insulating film (Fig 3A-3B, insulating layer 18) covering the first region and the second region, the insulating film having a first through-hole provided in the first region (Fig 3A-3B, first through hole 18a in first region 15b) and a plurality of second through- holes provided in the second region (Figs. 2A-2C and 3A-3B, second through hole 18b in second region 15c. Akimoto, in Fig. 3A, teaches repeated second through holes 18b are provided in the insulating film 18 in the second region, hence teaches plurality of second through holes 18b);
forming simultaneously a first thick-film electrode and a second thick-film electrode (Fig 3A-3B and ¶ [0048], the p-side interconnect layer 21 (first thick-film electrode) and the n-side interconnect layer 22 (second thick-film electrode) are formed simultaneously with Cu material by plating), the first thick-film electrode including a first conduction portion extending in a normal direction of the main surface in the first region (Fig 3A-3B and ¶ [0020], p-side interconnect layer 21 is the corresponding first thick-film electrode in the first region 15b, which extends in the normal (vertical) direction of the main surface), extending through the first through- hole, and reaching the substrate (Fig 3A-3B and ¶ [0020], the portion of 21 formed inside opening 18a extends through the opening 18a and reaches the substrate, since the p-side electrode 16 is provided on the stacked body/semiconductor layer 15 (i.e., the claimed substrate having a laminated structure including semiconductor layers), and a second thick-film electrode including a plurality of second conduction portions extending in the normal direction of the main surface in the second region (Fig 3A-3B and ¶ [0020], n-side interconnect layer 22 is the corresponding second thick-film electrode in the second region 15c, which extends in the normal (vertical) direction of the main surface. In the repeated second through-holes form the repeated second conductor portions, i.e., each second thick-film electrode 22 includes a horizontal portion and a vertical portion extending through 18b as shown in Akimoto’s Fig. 3A, where the repeated vertical portions is the claimed plurality of second conductive portions),
a height of the second thick-film electrode is greater than a height of the first thick-film electrode, the height of the second thick-film electrode is measured from a surface of the second thick-film electrode opposite to the substrate to a surface of the plurality of second conduction portions adjacent to the substrate, and the height of the first thick-film electrode is measured from a surface of the first thick-film electrode opposite to the substrate to a surface of the first conduction portion adjacent to the substrate (Figs. 3B, the substrate-opposing surfaces of p-side metal pillar 23 and n-side metal pillar 24 are exposed at substantially the same mounting-side level, while the lower surface of interconnect layer 21 contacts p-side electrode 16 and the lower surface of the interconnect layer 22 contacts n-side electrode 17. Because n-side electrode 17 is positioned lower than p-side electrode 16, the distance measured from the upper surface of n-side metal pillar 24 to the lower surface of the interconnect layer 22 is greater than the corresponding distance measured from the upper surface of p-side metal pillar 23 to the lower surface of interconnect layer 21).
Akimoto doesn’t explicitly disclose
wherein an area of at least one of the plurality of second through-holes is smaller than an area of the first through-hole when viewed from a direction perpendicular to the main surface of the substrate.
However, Akimoto teaches, in Fig. 3A, that an area of second through-hole 18b measured from its base up to an intermediate level (e.g., as shown in fig. 3A (annotated) above, A1 can be the portion of 18b) and this area is smaller than the area of first through-hole 18a. The claim does not specify which elevation/portion of the through-hole defines the “area”, thus “an area of the through-hole” reasonably encompasses the area of the void at a portion of the through-hole (e.g., from the hole base up to an intermediate region)). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to realize an area of second through-hole smaller than an area of first through-hole as impliedly taught by Akimoto in order to promote more favorable Cu plating on the sidewalls (Akimoto, ¶ [0047]).
Re: Independent Claim 7 (Currently amended), Akimoto discloses a semiconductor element comprising:
a substrate having a laminated structure including a semiconductor layer (Akimoto teaches, in Fig 3A-3B and ¶ [0017], substrate 10 and has stacked/laminated semiconductor structure i.e., semiconductor layer 15 (layers 11/12/13/16/17 stacked)), the substrate having a first region (Akimoto teaches, in Fig 3A-3B, light-emitting region, i.e., first region 15b) and a second region lower than the first region on a main surface (Akimoto teaches, in Fig 3A-3B and ¶ [0017], non-light emitting region i.e., second region 15c is at lower level than first region 15b on main surface 15);
an insulating film (Fig 3A-3B, insulating layer 18) covering the first region and the second region, the insulating film having a first through-hole provided in the first region (Fig 3A-3B, first through hole 18a in first region 15b) and a plurality of second through- holes provided in the second region (Fig 3A-3B, second through hole 18b in second region 15c. Akimoto, in Fig. 3A, teaches repeated second through holes 18b are provided in the insulating film 18 in the second region, hence teaches plurality of second through holes 18b);
a first thick-film electrode provided in the first region and extending in a normal direction of the main surface (Fig 3A-3B and ¶ [0020], p-side interconnect layer 21 is the corresponding first thick-film electrode in the first region 15b, which extends in the normal (vertical) direction of the main surface), the first thick-film electrode including a first conduction portion extending through the first through-hole and reaching the substrate (Fig 3A-3B and ¶ [0020], the portion of 21 formed inside opening 18a extends through the opening 18a and reaches the substrate, since the p-side electrode 16 is provided on the stacked body/semiconductor layer 15 (i.e., the claimed substrate having a laminated structure including semiconductor layers); and
a second thick-film electrode provided in the second region and extending in the normal direction of the main surface (Fig 3A-3B and ¶ [0020], n-side interconnect layer 22 is the corresponding second thick-film electrode in the second region 15c, which extends in the normal (vertical) direction of the main surface), the second thick-film electrode including a plurality of second conduction portions extending through a respective one of the plurality of second through-holes and reaching the substrate (Figs. 3A-3B and ¶ [0020], the portion of 22 formed inside opening 18b extends through the opening 18b and reaches the substrate, since the n-side electrode 17 is provided on the stacked body/semiconductor layer 15 (i.e., the claimed substrate having a laminated structure including semiconductor layers). In the repeated second through-holes form the repeated second conductor portions, i.e., each second thick-film electrode 22 includes a horizontal portion and a vertical portion extending through 18b as shown in Akimoto’s Fig. 3A, where the repeated vertical portions is the claimed plurality of second conductive portions),
wherein the first through-hole has a substantially circular shape, a substantially polygonal shape or a substantially elliptical shape when viewed from a direction perpendicular to the main surface of the substrate (Fig. 3A, Akimoto’s first opening 18a have substantially polygonal shape (e.g., rectangular), and the plurality of second through-holes have a substantially circular shape, a substantially polygonal shape or a substantially elliptical shape when viewed from the direction perpendicular to the main surface of the substrate (Fig. 3A, Akimoto’s each of the second openings 18b has substantially polygonal shape (e.g., rectangular), and
a height of the second thick-film electrode is greater than a height of the first thick-film electrode, the height of the second thick-film electrode is measured from a surface of the second thick-film electrode opposite to the substrate to a surface of the plurality of second conduction portions adjacent to the substrate, and the height of the first thick-film electrode is measured from a surface of the first thick-film electrode opposite to the substrate to a surface of the first conduction portion adjacent to the substrate (Figs. 3B, the substrate-opposing surfaces of p-side metal pillar 23 and n-side metal pillar 24 are exposed at substantially the same mounting-side level, while the lower surface of interconnect layer 21 contacts p-side electrode 16 and the lower surface of the interconnect layer 22 contacts n-side electrode 17. Because n-side electrode 17 is positioned lower than p-side electrode 16, the distance measured from the upper surface of n-side metal pillar 24 to the lower surface of the interconnect layer 22 is greater than the corresponding distance measured from the upper surface of p-side metal pillar 23 to the lower surface of interconnect layer 21).
Akimoto doesn’t explicitly disclose
wherein an area of at least one of the plurality of second through-holes is smaller than an area of the first through-hole when viewed in a cross-section including the center of each of the first through-hole and the plurality of second through-holes.
However, Akimoto teaches, in Fig. 3A, that an area of second through-hole 18b measured from its base up to an intermediate level (e.g., level of layer 16) is an area of 18b that is smaller than the area of first through-hole 18a when viewed in a cross-section including the center of each of the first through-hole and the second through-hole. The claim does not specify which elevation/portion of the through-hole defines the “area”, thus “an area of the through-hole” reasonably encompasses the area of the void at a portion of the through-hole (e.g., from the hole base up to an intermediate region)). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to realize an area of second through-hole smaller than an area of first through-hole as impliedly taught by Akimoto in order to promote more favorable Cu plating on the sidewalls (Akimoto, ¶ [0047]).
Re: Claim 8 (Previously presented), Akimoto discloses all the limitations of claim 1 on which this claim depends.
Akimoto further discloses,
wherein the insulating film is made of an oxide or a nitride containing at least one element selected from the group consisting of Si, Al, Zr, Mg, Ta, Ti, and Y, or a resin (Akimoto teaches, in ¶ [0019], the insulating layer 18 includes, for example, a resin such as a polyimide or the like, which is superior in patterning a fine opening. Alternatively, the insulating layer 18 may be also based on silicon oxide).
Re: Claim 10 (Previously presented), Akimoto discloses all the limitations of claim 7 on which this claim depends.
Akimoto further discloses,
wherein the insulating film is made of an oxide or a nitride containing at least one element selected from the group consisting of Si, Al, Zr, Mg, Ta, Ti, and Y, or a resin (Akimoto teaches, in ¶ [0019], the insulating layer 18 includes, for example, a resin such as a polyimide or the like, which is superior in patterning a fine opening. Alternatively, the insulating layer 18 may be also based on silicon oxide).
Re: Claim 12 (Previously presented), Akimoto discloses all the limitations of claim 6 on which this claim depends.
Akimoto further discloses,
wherein the insulating film is made of an oxide or a nitride containing at least one element selected from the group consisting of Si, Al, Zr, Mg, Ta, Ti, and Y, or a resin (Akimoto teaches, in ¶ [0019], the insulating layer 18 includes, for example, a resin such as a polyimide or the like, which is superior in patterning a fine opening. Alternatively, the insulating layer 18 may be also based on silicon oxide).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Akimoto (US 20110300644 A1) in view of Kawamura (US 20070096327 A1).
Re: Claim 3 (Previously presented), Akimoto discloses all the limitations of claim 1 on which this claim depends.
Akimoto is silent regarding,
wherein w1>2T1 holds when w1 is a dimension of the first through-hole in a direction parallel to the main surface of the substrate and T1 is a dimension of the first thick- film electrode in the direction perpendicular to the main surface of the substrate.
However, Kawamura teaches
wherein w1>2T1 holds when w1 is a dimension of the first through-hole in a direction parallel to the main surface of the substrate and T1 is a dimension of the first thick- film electrode in the direction perpendicular to the main surface of the substrate (Kawamura teaches, in Fig. 9 and ¶ [0141], selecting the geometry of an opening in an insulating (solder resist) layer relative to the resulting bump height, and provides explicit examples where an opening diameter (parallel dimension) is greater than twice the resulting bump height (perpendicular dimension). For example, Comparative Example 12 shows an opening/ball diameter of 80 micrometers and a bump height of 24-26 micrometers, which satisfies 80 micrometers > 2x (24-26) micrometers = 48-52 micrometers. In Akimoto, the claimed w1 reads on lateral (plan-view) dimension of the first opening 18a, and claimed T1 reads on the perpendicular (vertical) dimension/height of the corresponding first thick-film electrode 21. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to dimension Akimoto’s first opening 18a and the corresponding first thick-film electrode 21 height such that w1>2T1, as taught by Kawamura’s opening-diameter/bump-height relationship, in order to achieve a reliable, manufacturable pillar/bump geometry).
Claims 9, 11, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Akimoto (US 20110300644 A1) in view of Godo (US 20120104385 A1).
Re: Claim 9 (Previously presented), Akimoto discloses all the limitations of claim 1 on which this claim depends.
Akimoto is silent regarding
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate.
However, Godo teaches
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate (Godo, in Fig. 1B and ¶ [0105], teaches insulating layer 111 having uniform coverage; since the insulating layer formed using a high-density plasma-enhanced CVD method can have a uniform thickness, the insulating layer has excellent step coverage; further, as for the insulating layer formed using a high-density plasma-enhanced CVD method, the thickness can be controlled precisely).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Akimoto’s insulating layer 18 (covering both the higher and lower regions and the step portion) with a substantially uniform thickness in the first and second regions, by using the insulating forming approach taught by Godo in order to provide insulating layer that has excellent step coverage (Godo, ¶ [0105]).
Re: Claim 11 (Previously presented), Akimoto discloses all the limitations of claim 7 on which this claim depends.
Akimoto is silent regarding
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate.
However, Godo teaches
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate (Godo, in Fig. 1B and ¶ [0105], teaches insulating layer 111 having uniform coverage; since the insulating layer formed using a high-density plasma-enhanced CVD method can have a uniform thickness, the insulating layer has excellent step coverage; further, as for the insulating layer formed using a high-density plasma-enhanced CVD method, the thickness can be controlled precisely).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Akimoto’s insulating layer 18 (covering both the higher and lower regions and the step portion) with a substantially uniform thickness in the first and second regions, by using the insulating forming approach taught by Godo in order to provide insulating layer that has excellent step coverage (Godo, ¶ [0105]).
Re: Claim 13 (Previously presented), Akimoto discloses all the limitations of claim 6 on which this claim depends.
Akimoto is silent regarding
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate.
However, Godo teaches
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate (Godo, in Fig. 1B and ¶ [0105], teaches insulating layer 111 having uniform coverage; since the insulating layer formed using a high-density plasma-enhanced CVD method can have a uniform thickness, the insulating layer has excellent step coverage; further, as for the insulating layer formed using a high-density plasma-enhanced CVD method, the thickness can be controlled precisely).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Akimoto’s insulating layer 18 (covering both the higher and lower regions and the step portion) with a substantially uniform thickness in the first and second regions, by using the insulating forming approach taught by Godo in order to provide insulating layer that has excellent step coverage (Godo, ¶ [0105]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm.
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
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