Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Claim 1 (and its dependent claims) recites “…an area of the second through-hole…an area of the first through-hole…”. “Area of the first through-hole and second-through-hole” is interpretated as the area from the top view, which is aligned with the specification of the instant application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1- 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites, “…the second thick-film electrode is higher than the first thick-film electrode”. It is unclear if this means height measured from main surface, from the insulating film top surface, etc. or if it means overall pillar height, top elevation, or vertical extent from local region. For the purpose of examination, “…the second thick-film electrode is higher than the first thick-film electrode” is interpretated as “…the second thick-film electrode has overall height more than the first thick-film electrode”.
Claim 4 recites, “…a plurality of the second through-holes… respectively extending through the second through-hole…”. That’s a number inconsistent/antecedent issue, needed to be fix. For the purpose of examination this portion of claim 4 is interpretated as “…a plurality of the second through-holes… respectively extending through the respective ones of the second through-holes”.
Claim 6 recites, “…the second thick-film electrode is higher than the first thick-film electrode”. It is unclear if this means height measured from main surface, from the insulating film top surface, etc. or if it means overall pillar height, top elevation, or vertical extent from local region. For the purpose of examination, “…the second thick-film electrode is higher than the first thick-film electrode” is interpretated as “…the second thick-film electrode has overall height more than the first thick-film electrode”.
Claim 7 recites, “…the second thick-film electrode is higher than the first thick-film electrode”. It is unclear if this means height measured from main surface, from the insulating film top surface, etc. or if it means overall pillar height, top elevation, or vertical extent from local region. For the purpose of examination, “…the second thick-film electrode is higher than the first thick-film electrode” is interpretated as “…the second thick-film electrode has overall height more than the first thick-film electrode”.
Dependent Claims 2-5 and 8-13 are rejected under 35 U.S.C. 112(b) since they inherit the indefiniteness of the claims from which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-8, 10, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Akimoto (US 20110300644 A1).
Re: Independent Claim 1, Akimoto discloses a semiconductor element comprising:
a substrate having a laminated structure including a semiconductor layer (Akimoto teaches, in Fig 3A-3B and ¶ [0017], substrate 10 and has stacked/laminated semiconductor structure i.e., semiconductor layer 15 (layers 11/12/13/16/17 stacked)), the substrate having a first region (Akimoto teaches, in Figs. 2A-2C and 3A-3B, light-emitting region, i.e., first region 15b) and a second region lower than the first region on a main surface (Akimoto teaches, in Fig 3A-3B and ¶ [0017], non-light emitting region i.e., second region 15c is at lower level than first region 15b on main surface 15);
an insulating film (Fig 3A-3B, insulating layer 18) covering the first region and the second region, the insulating film having a first through-hole provided in the first region (Figs. 2A-2C and 3A-3B, first through hole 18a in first region 15b) and a second through- hole provided in the second region (Figs. 2A-2C and 3A-3B, second through hole 18b in second region 15c);
a first thick-film electrode provided in the first region and extending in a normal direction of the main surface (Figs. 3A-3B and ¶ [0020], p-side interconnect layer 21 is the corresponding first thick-film electrode in the first region 15b, which extends in the normal (vertical) direction of the main surface), the first thick-film electrode including a first conduction portion extending through the first through-hole and reaching the substrate (Figs. 3A-3B and ¶ [0020], the portion of 21 formed inside opening 18a extends through the opening 18a and reaches the substrate, since the p-side electrode 16 is provided on the stacked body/semiconductor layer 15 (i.e., the claimed substrate having a laminated structure including semiconductor layers); and
a second thick-film electrode provided in the second region and extending in the normal direction of the main surface (Figs. 3A-3B and ¶ [0020], n-side interconnect layer 22 is the corresponding second thick-film electrode in the second region 15c, which extends in the normal (vertical) direction of the main surface), the second thick-film electrode including a second conduction portion extending through the second through-hole and reaching the substrate (Figs. 3A-3B and ¶ [0020], the portion of 22 formed inside opening 18b extends through the opening 18b and reaches the substrate, since the n-side electrode 17 is provided on the stacked body/semiconductor layer 15 (i.e., the claimed substrate having a laminated structure including semiconductor layers),
the second thick-film electrode is higher than the first thick-film electrode (Figs. 3B, 22 extends a greater perpendicular distance (height) to reach the lower positioned electrode 17 than 21 which extends less perpendicular distance to reach the upper positioned electrode 16).
Akimoto doesn’t explicitly disclose
wherein an area of the second through-hole is smaller than an area of the first through-hole when viewed from a direction perpendicular to the main surface of the substrate.
However, Akimoto teaches, in Fig. 3A, that an area of second through-hole 18b measured from its base up to an intermediate level (e.g., level of layer 16) is an area of 18b that is smaller than the area of first through-hole 18a. The claim does not specify which elevation/portion of the through-hole defines the “area”, thus “an area of the through-hole” reasonably encompasses the area of the void at a portion of the through-hole (e.g., from the hole base up to an intermediate region). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to realize an area of second through-hole smaller than an area of first through-hole as impliedly taught by Akimoto in order to promote more favorable Cu plating on the sidewalls (Akimoto, ¶ [0047]).
Re: Claim 2, Akimoto discloses all the limitations of claim 1 on which this claim depends.
Akimoto further teaches
wherein 2d>w2 holds when d is a dimension of the second conduction portion in the direction perpendicular to the main surface of the substrate and w2 is a dimension of the second conduction portion in a direction parallel to the main surface of the substrate (Akimoto teaches, in Figs. 3A-3B, dimension of second conductive portion 22 inside the opening 18b has narrow width and longer height (width corresponds to the claimed w2 and height corresponds to the claimed d). Thus, in Fig. 3A, height of 18b (claimed d)>width of 18b (claimed w2), which make its obvious that 2d>w2).
Re: Claim 4, Akimoto discloses all the limitations of claim 1 on which this claim depends.
Akimoto further teaches
wherein a plurality of the second through-holes are provided in the insulating film in the second region (Akimoto, in Fig. 3A, teaches repeated second through holes 18b are provided in the insulating film 18 in the second region), and wherein the second thick-film electrode includes a plurality of the second conduction portions respectively extending through the second through-hole and reaching the substrate (second thick-film electrode 22 includes a horizontal portion and a vertical portion extending through 18b as shown in Akimoto’s Fig. 3A).
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Re: Claim 5, Akimoto discloses all the limitations of claim 4 on which this claim depends.
Akimoto further teaches
wherein the total areas of the second through-holes are smaller than the area of the first through-hole when viewed from the direction perpendicular to the main surface of the substrate (As shown in Akimoto’s Fig. 3A (annotated) above, total areas for the portion A1 of second through holes is smaller than the area of the first through hole 18a when viewed from the direction perpendicular to the main surface of the substrate).
Re: Independent Claim 6, Akimoto discloses a method for manufacturing a semiconductor element including steps of:
preparing a substrate having a laminated structure including a semiconductor layer (Akimoto teaches, in Fig 3A-3B and ¶ [0017], substrate 10 and has stacked/laminated semiconductor structure i.e., semiconductor layer 15 (layers 11/12/13/16/17 stacked)), the substrate having a first region (Akimoto teaches, in Fig 3A-3B, light-emitting region, i.e., first region 15b) and a second region lower than the first region on a main surface (Akimoto teaches, in Fig 3A-3B and ¶ [0017], non-light emitting region i.e., second region 15c is at lower level than first region 15b on main surface 15);
forming an insulating film (Fig 3A-3B, insulating layer 18) covering the first region and the second region, the insulating film having a first through-hole provided in the first region (Fig 3A-3B, first through hole 18a in first region 15b) and a second through- hole provided in the second region (Fig 3A-3B, second through hole 18b in second region 15c);
forming simultaneously a first thick-film electrode and a second thick-film electrode (Fig 3A-3B and ¶ [0048], the p-side interconnect layer 21 (first thick-film electrode) and the n-side interconnect layer 22 (second thick-film electrode) are formed simultaneously with Cu material by plating), the first thick-film electrode including a first conduction portion extending in a normal direction of the main surface in the first region (Fig 3A-3B and ¶ [0020], p-side interconnect layer 21 is the corresponding first thick-film electrode in the first region 15b, which extends in the normal (vertical) direction of the main surface), extending through the first through- hole, and reaching the substrate (Fig 3A-3B and ¶ [0020], the portion of 21 formed inside opening 18a extends through the opening 18a and reaches the substrate, since the p-side electrode 16 is provided on the stacked body/semiconductor layer 15 (i.e., the claimed substrate having a laminated structure including semiconductor layers), and a second thick-film electrode including a second conduction portion extending in the normal direction of the main surface in the second region (Fig 3A-3B and ¶ [0020], n-side interconnect layer 22 is the corresponding second thick-film electrode in the second region 15c, which extends in the normal (vertical) direction of the main surface), extending through the second through-hole, and reaching the substrate (Fig 3A-3B and ¶ [0020], the portion of 22 formed inside opening 18b extends through the opening 18b and reaches the substrate, since the n-side electrode 17 is provided on the stacked body/semiconductor layer 15 (i.e., the claimed substrate having a laminated structure including semiconductor layers),
the second thick-film electrode is higher than the first thick-film electrode (Fig. 3B, 22 extends a greater perpendicular distance (height) to reach the lower positioned electrode 17 than 21 which extends less perpendicular distance to reach the upper positioned electrode 16).
Akimoto doesn’t explicitly disclose
wherein an area of the second through-hole is smaller than an area of the first through-hole when viewed from a direction perpendicular to the main surface of the substrate.
However, Akimoto teaches, in Fig. 3A, that an area of second through-hole 18b measured from its base up to an intermediate level (e.g., as shown in fig. 3A (annotated) above, A1 can be the portion of 18b) and this area is smaller than the area of first through-hole 18a. The claim does not specify which elevation/portion of the through-hole defines the “area”, thus “an area of the through-hole” reasonably encompasses the area of the void at a portion of the through-hole (e.g., from the hole base up to an intermediate region)). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to realize an area of second through-hole smaller than an area of first through-hole as impliedly taught by Akimoto in order to promote more favorable Cu plating on the sidewalls (Akimoto, ¶ [0047]).
Re: Independent Claim 7, Akimoto discloses a semiconductor element comprising:
a substrate having a laminated structure including a semiconductor layer (Akimoto teaches, in Fig 3A-3B and ¶ [0017], substrate 10 and has stacked/laminated semiconductor structure i.e., semiconductor layer 15 (layers 11/12/13/16/17 stacked)), the substrate having a first region (Akimoto teaches, in Fig 3A-3B, light-emitting region, i.e., first region 15b) and a second region lower than the first region on a main surface (Akimoto teaches, in Fig 3A-3B and ¶ [0017], non-light emitting region i.e., second region 15c is at lower level than first region 15b on main surface 15);
an insulating film (Fig 3A-3B, insulating layer 18) covering the first region and the second region, the insulating film having a first through-hole provided in the first region (Fig 3A-3B, first through hole 18a in first region 15b) and a second through- hole provided in the second region (Fig 3A-3B, second through hole 18b in second region 15c);
a first thick-film electrode provided in the first region and extending in a normal direction of the main surface (Fig 3A-3B and ¶ [0020], p-side interconnect layer 21 is the corresponding first thick-film electrode in the first region 15b, which extends in the normal (vertical) direction of the main surface), the first thick-film electrode including a first conduction portion extending through the first through-hole and reaching the substrate (Fig 3A-3B and ¶ [0020], the portion of 21 formed inside opening 18a extends through the opening 18a and reaches the substrate, since the p-side electrode 16 is provided on the stacked body/semiconductor layer 15 (i.e., the claimed substrate having a laminated structure including semiconductor layers); and
a second thick-film electrode provided in the second region and extending in the normal direction of the main surface (Fig 3A-3B and ¶ [0020], n-side interconnect layer 22 is the corresponding second thick-film electrode in the second region 15c, which extends in the normal (vertical) direction of the main surface), the second thick-film electrode including a second conduction portion extending through the second through-hole and reaching the substrate (Fig 3A-3B and ¶ [0020], the portion of 22 formed inside opening 18b extends through the opening 18b and reaches the substrate, since the n-side electrode 17 is provided on the stacked body/semiconductor layer 15 (i.e., the claimed substrate having a laminated structure including semiconductor layers),
wherein the first through-hole has a substantially circular shape, a substantially polygonal shape or a substantially elliptical shape when viewed from a direction perpendicular to the main surface of the substrate (Fig. 3A, Akimoto’s first opening 18a have substantially polygonal shape (e.g., rectangular), and the second through-hole has a substantially circular shape, a substantially polygonal shape or a substantially elliptical shape when viewed from the direction perpendicular to the main surface of the substrate (Fig. 3A, Akimoto’s second opening 18b have substantially polygonal shape (e.g., rectangular), and
the second thick-film electrode is higher than the first thick-film electrode (Fig. 3B, 22 extends a greater perpendicular distance (height) to reach the lower positioned electrode 17 than 21 which extends less perpendicular distance to reach the upper positioned electrode 16).
Akimoto doesn’t explicitly disclose
wherein an area of the second through-hole is smaller than an area of the first through-hole when viewed in a cross-section including the center of each of the first through-hole and the second through-hole.
However, Akimoto teaches, in Fig. 3A, that an area of second through-hole 18b measured from its base up to an intermediate level (e.g., level of layer 16) is an area of 18b that is smaller than the area of first through-hole 18a when viewed in a cross-section including the center of each of the first through-hole and the second through-hole. The claim does not specify which elevation/portion of the through-hole defines the “area”, thus “an area of the through-hole” reasonably encompasses the area of the void at a portion of the through-hole (e.g., from the hole base up to an intermediate region)). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to realize an area of second through-hole smaller than an area of first through-hole as impliedly taught by Akimoto in order to promote more favorable Cu plating on the sidewalls (Akimoto, ¶ [0047]).
Re: Claim 8, Akimoto discloses all the limitations of claim 1 on which this claim depends.
Akimoto further discloses,
wherein the insulating film is made of an oxide or a nitride containing at least one element selected from the group consisting of Si, Al, Zr, Mg, Ta, Ti, and Y, or a resin (Akimoto teaches, in ¶ [0019], the insulating layer 18 includes, for example, a resin such as a polyimide or the like, which is superior in patterning a fine opening. Alternatively, the insulating layer 18 may be also based on silicon oxide).
Re: Claim 10, Akimoto discloses all the limitations of claim 7 on which this claim depends.
Akimoto further discloses,
wherein the insulating film is made of an oxide or a nitride containing at least one element selected from the group consisting of Si, Al, Zr, Mg, Ta, Ti, and Y, or a resin (Akimoto teaches, in ¶ [0019], the insulating layer 18 includes, for example, a resin such as a polyimide or the like, which is superior in patterning a fine opening. Alternatively, the insulating layer 18 may be also based on silicon oxide).
Re: Claim 12, Akimoto discloses all the limitations of claim 6 on which this claim depends.
Akimoto further discloses,
wherein the insulating film is made of an oxide or a nitride containing at least one element selected from the group consisting of Si, Al, Zr, Mg, Ta, Ti, and Y, or a resin (Akimoto teaches, in ¶ [0019], the insulating layer 18 includes, for example, a resin such as a polyimide or the like, which is superior in patterning a fine opening. Alternatively, the insulating layer 18 may be also based on silicon oxide).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Akimoto (US 20110300644 A1) in view of Kawamura (US 20070096327 A1).
Re: Claim 3, Akimoto discloses all the limitations of claim 1 on which this claim depends.
Akimoto is silent regarding,
wherein w1>2T1 holds when w1 is a dimension of the first through-hole in a direction parallel to the main surface of the substrate and T1 is a dimension of the first thick- film electrode in the direction perpendicular to the main surface of the substrate.
However, Kawamura teaches
wherein w1>2T1 holds when w1 is a dimension of the first through-hole in a direction parallel to the main surface of the substrate and T1 is a dimension of the first thick- film electrode in the direction perpendicular to the main surface of the substrate (Kawamura teaches, in Fig. 9 and ¶ [0141], selecting the geometry of an opening in an insulating (solder resist) layer relative to the resulting bump height, and provides explicit examples where an opening diameter (parallel dimension) is greater than twice the resulting bump height (perpendicular dimension). For example, Comparative Example 12 shows an opening/ball diameter of 80 micrometers and a bump height of 24-26 micrometers, which satisfies 80 micrometers > 2x (24-26) micrometers = 48-52 micrometers. In Akimoto, the claimed w1 reads on lateral (plan-view) dimension of the first opening 18a, and claimed T1 reads on the perpendicular (vertical) dimension/height of the corresponding first thick-film electrode 21. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to dimension Akimoto’s first opening 18a and the corresponding first thick-film electrode 21 height such that w1>2T1, as taught by Kawamura’s opening-diameter/bump-height relationship, in order to achieve a reliable, manufacturable pillar/bump geometry).
Claims 9, 11, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Akimoto (US 20110300644 A1) in view of Godo (US 20120104385 A1).
Re: Claim 9, Akimoto discloses all the limitations of claim 1 on which this claim depends.
Akimoto is silent regarding
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate.
However, Godo teaches
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate (Godo, in Fig. 1B and ¶ [0105], teaches insulating layer 111 having uniform coverage; since the insulating layer formed using a high-density plasma-enhanced CVD method can have a uniform thickness, the insulating layer has excellent step coverage; further, as for the insulating layer formed using a high-density plasma-enhanced CVD method, the thickness can be controlled precisely).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Akimoto’s insulating layer 18 (covering both the higher and lower regions and the step portion) with a substantially uniform thickness in the first and second regions, by using the insulating forming approach taught by Godo in order to provide insulating layer that has excellent step coverage (Godo, ¶ [0105]).
Re: Claim 11, Akimoto discloses all the limitations of claim 7 on which this claim depends.
Akimoto is silent regarding
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate.
However, Godo teaches
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate (Godo, in Fig. 1B and ¶ [0105], teaches insulating layer 111 having uniform coverage; since the insulating layer formed using a high-density plasma-enhanced CVD method can have a uniform thickness, the insulating layer has excellent step coverage; further, as for the insulating layer formed using a high-density plasma-enhanced CVD method, the thickness can be controlled precisely).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Akimoto’s insulating layer 18 (covering both the higher and lower regions and the step portion) with a substantially uniform thickness in the first and second regions, by using the insulating forming approach taught by Godo in order to provide insulating layer that has excellent step coverage (Godo, ¶ [0105]).
Re: Claim 13, Akimoto discloses all the limitations of claim 6 on which this claim depends.
Akimoto is silent regarding
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate.
However, Godo teaches
wherein the insulating film has a substantially uniform thickness in the first region and the second region of the main surface of the substrate (Godo, in Fig. 1B and ¶ [0105], teaches insulating layer 111 having uniform coverage; since the insulating layer formed using a high-density plasma-enhanced CVD method can have a uniform thickness, the insulating layer has excellent step coverage; further, as for the insulating layer formed using a high-density plasma-enhanced CVD method, the thickness can be controlled precisely).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Akimoto’s insulating layer 18 (covering both the higher and lower regions and the step portion) with a substantially uniform thickness in the first and second regions, by using the insulating forming approach taught by Godo in order to provide insulating layer that has excellent step coverage (Godo, ¶ [0105]).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
Jang (US 20180366613 A1) and Lee (US 20210225708 A1) disclose semiconductor structure with step portions on substrate and multiple openings.
Conclusion
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898