Attorney’s Docket Number: 909/309 UTIL
Filing Date: 11/17/2023
Claimed Foreign Priority Date: 5/20/2021 (EP21174900.7)
Inventors: Leitgeb et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application and preliminary amendment filed 11/17/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first
inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Interpretation
Claim 32 recites the line “Electronic device for power electronics comprising a compound semiconductor layered structure according to claim 17”, which will be interpreted as “The compound semiconductor layered structure accordingly to claim 17, wherein the compound semiconductor layered structure is further comprised within an electronic device for power electronics”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 recites the limitation "said silicon carbide compound semiconductor film" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, "said silicon carbide compound semiconductor film" will be construed to recite "said silicon carbide semiconductor film".
Claim 25 recites the limitation "said semiconductor film" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, "said semiconductor film" will be construed to recite "said silicon carbide semiconductor film".
Claim 26 recites the limitation “semiconductor substrate” in line 9. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, “semiconductor substrate” will be construed to recite “single crystalline compound semiconductor substrate”.
Claim 27 recites the limitation “obtained compound semiconductor layered structure” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, “obtained compound semiconductor layered structure” will be construed to recite “compound semiconductor layered structure”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17 and 22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Matsushima (US 20210384300 A1).
Regarding claim 17, Matsushima (see, e.g., fig. 1) shows all aspects of the instant invention including a compound semiconductor layered structure comprising:
A silicon carbide semiconductor substrate (e.g., SiC polycrystalline layer 14) having a bottom surface (e.g., lower surface of layer 14) and a top surface (e.g., top surface of layer 14 in contact with layer 12);
A silicon carbide semiconductor film (e.g., biaxially-oriented SiC layer 12) bonded (see, e.g., paragraph 35) on top of said silicon carbide semiconductor substrate (e.g., SiC polycrystalline layer 14), said silicon carbide semiconductor film (e.g., biaxially-oriented SiC layer 12) comprising a bottom layer (e.g., bottom portion of layer 12 in contact with layer 14) in direct contact with said top surface (e.g., top surface of layer 14 in contact with layer 12) of said silicon carbide semiconductor substrate (e.g., SiC polycrystalline layer 14), characterized in that said bottom layer is porous (see, e.g., paragraph 30 and fig. 5, noting that the interface between the two layers has pores) and polycrystalline (see, e.g., paragraph 26“…biaxially-oriented SiC layer 12 may be…polycrystalline…”).
Regarding claim 22, Matsushima (see, e.g., fig. 1) shows wherein said silicon carbide semiconductor substrate (e.g., SiC polycrystalline layer 14) comprises a polycrystalline material (see, e.g., paragraph 28 “The SiC polycrystalline layer 14 merely needs to be composed of a SiC polycrystalline body…”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Matsushima.
Regarding claim 18, Matsushima (see, e.g., fig. 1) shows wherein said silicon carbide semiconductor film (e.g., biaxially-oriented SiC layer 12) further comprises a top layer (e.g., top layer of biaxially-oriented SiC layer 12), and that the silicon carbide semiconductor film (e.g., biaxially-oriented SiC layer 12) can further comprise monocrystalline distinct from the polycrystalline (see, e.g., paragraph 26 “The biaxially-oriented SiC layer 12 is a layer in which SiC is oriented in both the c-axis direction and the a-axis direction, and may include both a polycrystalline layer containing a grain boundary and a single-crystalline layer containing no grain boundary”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the top layer comprising this single-crystalline layer, since only two configurations of these layer configurations are possible to try; i.e., monocrystalline in the bottom layer region and polycrystalline in the top layer region, or polycrystalline in the bottom layer region and monocrystalline in the top layer region, and since neither non-obvious nor unexpected results, i.e., results which are different in kind from the results of the prior art, will be obtained, as already suggested by Matsushima. See In re KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding claim 24, Matsushima (see, e.g., fig. 1) fails to show wherein said compound semiconductor layered structure has a diameter of 1 cm to 50 cm. However, ranges of length or diameter will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
CRITICALITY: The specification contains no disclosure of either the critical nature of the
claimed length ranges or any unexpected results arising therefrom. Where patentability is
said to be based upon particular chosen dimensions or upon another variable recited in a
claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919
F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Matsushima in view of Maekawa (US 20220157943 A1).
Regarding claim 19, Matsushima (see, e.g., fig. 1) fails to show wherein said polycrystalline bottom layer comprises a plurality of crystallites having an average crystallite size of 10 nm to 200 nm.
Maekawa (see, e.g., fig. 23A), in a similar device to Matsushima, teaches a polycrystalline layer (e.g., polycrystal silicon carbide ingot [310A]) comprises a crystallite of 10 nm to 200 nm (see, e.g., paragraph 212 “…the size of a crystal particle… may be 100 nm or less”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the crystallite size of Maekawa within the polycrystalline layer of Matsushima, in order to limit the crystallite size within the polycrystalline layer, increasing the amount of space available for a larger amount of individual crystallites, enhancing mechanical strength and stiffness within the device.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Matsushima in view of Schulze (US 20190362972 A1).
Regarding claim 20, Matsushima (see, e.g., fig. 1) fails to explicitly teach wherein said polycrystalline bottom layer has a porosity of .1% to 40%.
Schulze (see, e.g., fig. 4), in a similar device to Matsushima, teaches a porosity in a silicon carbide layer of between .1% to 40% (see, e.g., paragraph 50 “…the porous silicon carbide layer may have a porosity between 5% and 95%...”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the porosity ratio configuration of Schulze within the silicon carbide polycrystalline layer porosity profile of Matsushima, in order to decrease the potential cracking and delamination within the device.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Matsushima in view of Sinquin (US 20220270875 A1).
Regarding claim 21, Matsushima (see, e.g., fig. 1) fails to show wherein said bottom layer has a thickness of 50 nm to 2 μm.
Sinquin (see, e.g., paragraph 15), in a similar device to Matsushima, teaches a polycrystalline silicon carbide layer has a thickness of 1.5 μm (see, e.g., paragraph 15 “…intermediate layer of polycrystalline silicon carbide…the thickness of the intermediate layer being greater than or equal to 1.5 microns…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness of Sinquin within the bottom layer of Matsushima, in order to achieve the expected result of limiting the cost of manufacturing the polycrystalline layer while still maintaining a distinct polycrystalline structure within the device.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Matsushima in view of Akiyama (US 20180265360 A1).
Regarding claim 23, Matsushima (see, e.g., fig. 1) fails to teach wherein said silicon carbide semiconductor film has a thickness of at most 50 μm.
Akiyama (see, e.g., fig. 1), in a similar device to Matsushima, teaches a silicon carbide semiconductor film (e.g., silicon carbide thin film 11) has a thickness of at most 50 μm (see, e.g., paragraph 105 “thickness of the single-crystal silicon carbide thin film 11 to 1.04 μm…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness profile of Akiyama within the silicon carbide semiconductor film of Matsushima, in order to achieve the expected result of limiting the thickness of the layer, reducing the cost of manufacturing the device, while simultaneously maintaining the silicon carbide structure’s functionality within the configuration.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Matsushima in view of Shih (US 20220028977 A1).
Regarding claim 25, Matsushima (see, e.g., fig. 1) fails to teach a silicon carbide semiconductor overlayer having a bottom surface layer and a top surface layer, whereby said bottom surface layer of said silicon carbide semiconductor overlayer is in direct contact with said top layer of said silicon carbide semiconductor film.
Shih (see, e.g., fig. 2), in a similar device to Matsushima, teaches a silicon carbide semiconductor overlayer (e.g., epitaxy silicon carbide substrate 202) having a bottom surface layer (e.g., bottom surface region of epitaxy silicon carbide substrate 202) and a top surface layer (e.g., bottom surface region of epitaxy silicon carbide substrate 202), whereby said bottom surface layer (e.g., bottom surface region of epitaxy silicon carbide substrate 202) of said silicon carbide semiconductor overlayer (e.g., epitaxy silicon carbide substrate 202) is in direct contact with a top layer (e.g., top surface region of layer 106) of a silicon carbide semiconductor film (e.g., silicon carbide layer 106).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the silicon carbide overlayer of Shih over the silicon carbide semiconductor film of Matsushima, in order to achieve the expected result of providing additional bandgap and mechanically robust properties within the device.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Matsushima in view of Tak (US 20120074385 A1).
Regarding claim 32, Matsushima (see, e.g., fig. 1) fails to explicitly show the compound semiconductor layered structure is comprised within an electronic device for power electronics.
Tak (see, e.g., fig. 15C), in a similar device to Matsushima, teaches a compound semiconductor layer (see, e.g., paragraph 197 “The nitride stack 350 may include a GaN-based compound semiconductor layer…”) is comprised within an electronic device for power electronics (see, e.g., paragraph 205 “Therefore, semiconductor devices 300 and 302 according to at least some example embodiments may be used as templates for manufacturing various types of electronic devices, for example, high quality light-emitting devices, power devices, etc.”)
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the power electronics configuration of Tak comprising the compound semiconductor structure of Matsushima, in order to achieve the expected result of utilizing the compound semiconductor layered structure for an electronic device application, such as power electronics (see paragraph 205 of Tak).
Claims 26 and 28-31 are rejected under 35 U.S.C. 103 as being unpatentable over Leitgeb (Markus Leitgeb et al 2017 J. Electrochem. Soc. 164 E337) in view of Bedell (US 20100310775 A1) further in view of Matsushima.
Regarding claim 26, Leitgeb shows most aspects of the instant invention, including a process for preparing a compound semiconductor layered structure, including:
Porosifying a single crystalline, compound semiconductor substrate using metal-assisted photochemical etching (see, e.g., Abstract “Porous 4H-SiC layers were prepared from monocrystalline samples applying photo-electrochemical etching in hydrofluoric acid” + Supplementary data “A promising candidate is porous SiC prepared from single crystalline wafers because it shows a higher chemical stability than silicon. In contrast to electrochemical etching of Si, photo-electrochemical etching (PECE) of SiC in HF based etching solutions is a comparably challenging task and hence, only a limited number of publications exist. Some authors report a skin layer on top of the porous structure, which exhibits only a few pores with diameters in the nm range. This skin layer is followed by a cap layer which shows an irregular porous structure. This problem has been addressed recently by a combination of metal assisted photochemical etching with PECE.”), thereby obtaining a single crystalline compound semiconductor substrate (S-1) having a porous top surface (S-12, S-13).
Leitgeb, however, fails to show applying a stressor layer onto said porous top surface (S-12,S-13), thereby forming a stressor layer – substrate wafer, controlled spalling of a compound semiconductor thin film from said single crystalline semiconductor substrate using said stressor layer in said stressor layer – substrate wafer; thereby exfoliating a compound semiconductor thin film, removing said stressor layer from said compound semiconductor thin film, thereby obtaining an isolated compound semiconductor thin film, and bonding said isolated compound.
Bedell (see, e.g., fig. 1), in a similar device to Matsushima, teaches applying a stressor layer (e.g., metal layer of claim 1) onto a top surface of a single-crystalline semiconductor substrate (see, e.g., paragraph 17 “…semiconductor material comprising the ingot may comprise…single- or poly-crystalline silicon…”), thereby forming a stressor layer-substrate wafer (see, e.g., claim 1 “…forming a metal layer on the ingot of the semiconductor substrate…”), controlled spalling (see, e.g., spalling of claim 1 or paragraph 16), and removing said stressor layer (see, e.g., claim 1 “…removing the layer from the ingot…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the stressor layer applying, spalling, and stressor removal of Bedell within the method of Leitgeb, in order to form layers of semiconductor substrate material cost-effectively, as taught by Bedell (see, e.g., paragraph 16).
Leitgeb in view of Bedell, however, fails to teach bonding said isolated compound semiconductor thin film onto a polycrystalline semiconductor substrate, thereby obtaining a compound semiconductor layered structure.
Matsushima (see, e.g., fig. 1), in a method to Leitgeb in view of Bedell, teaches bonding (see, e.g., paragraph 35) an isolated compound semiconductor thin film (e.g., biaxially-oriented SiC layer 12) onto a polycrystalline semiconductor substrate (e.g., SiC polycrystalline layer 14), thereby obtaining a compound semiconductor layered structure (e.g., biaxially-oriented SiC layer 12 + SiC polycrystalline layer 14).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the bonding step of Matsushima within the method of Leitgeb in view of Bedell, in order to connect the isolated compound semiconductor thin film and achieve the expected result of including a multi-crystal interface with the semiconductor thin film, diversifying the makeup and increasing the durability within the device.
Regarding claim 28, Leitgeb shows whereby said single crystalline, compound semiconductor substrate comprises silicon carbide (see, e.g., Abstract “Porous 4H-SiC layers were prepared from monocrystalline samples applying photo-electrochemical etching in hydrofluoric acid” + Supplementary data “A promising candidate is porous SiC prepared from single crystalline wafers because it shows a higher chemical stability than silicon…”).
Regarding claim 29, Matsushima (see, e.g., fig. 1) teaches the polycrystalline semiconductor substrate (e.g., SiC polycrystalline layer 14) comprises silicon carbide.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the silicon carbide of Matsushima within the polycrystalline semiconductor substrate of Leitgeb in view of Bedell further in view of Matsushima, as silicon carbide was a well-known material to include in polycrystalline substrates at the time of filing the invention, as taught by Matsushima.
Regarding claim 30, Bedell teaches said stressor layer (e.g., metal layer layer of claim 1) comprises a metal.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the metal of Bedell within said stressor layer of Leitgeb in view of Bedell further in view of Matsushima, as metal was a well-known material to include in stressor layers at the time of filing the invention, as taught by Bedell.
Regarding claim 31, Leitgeb in view of Bedell further in view of Matsushima teaches the compound semiconductor layered structure obtained by a process according to claim 26 (see, e.g., rejection of claim 26, which is considered to be relevant here).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Leitgeb in view of Bedell further in view of Matsushima and Shih.
Shih (see, e.g., fig. 2), in a similar device to Leitgeb in view of Bedell further in view of Matsushima, teaches epitaxially growing (see, e.g., paragraphs 3-4 or 24) a semiconductor overlayer (e.g., epitaxy silicon carbide substrate 202) on top of a compound semiconductor layered structure (e.g., silicon carbide layer 106 + support substrate 102).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the silicon carbide overlayer growth step of Shih over the compound semiconductor layered structure of Leitgeb in view of Bedell further in view of Matsushima, in order to achieve the expected result of providing additional bandgap and mechanically robust properties within the device.
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814