Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed July 23rd, 2025 has been entered. Claims 21-40 are pending in this application. Applicant’s amendments to the claims have been fully considered, however the amendments do not overcome the 35 USC § 103 rejection set forth in the Non-Final Office Action mailed April 23rd, 2025. Accordingly, the rejections of claims 21-40 are maintained for the reasons set forth below.
Applicant argues that the cited references, Hong et al. (US 2022/0318087), hereinafter Hong, in view of Qiao et al. (US 2022/0148674), hereinafter Qiao, fail to disclose or suggest correlation of historical information with a hardware configuration. The Examiner respectfully disagrees. Qiao teaches the recording of historical fault information associated with memory cells and/or rows (Qiao, Fig. 1, block 101; para. [0094], lines 1-4, "Step 101: Start fault analysis for a memory at a first moment, where the fault analysis includes: obtaining a current fault analysis result of the memory by analyzing historical fault information”). Qiao also teaches analyzing the recorded fault information to determine a fault mode of a specific memory row (Qiao, para. [0052] -para. [0053], "Optionally, if the fault analysis result includes a fault mode, the handling module includes: a first recovery submodule, configured to start fault recovery for the memory when the fault mode is a memory row fault…"). A memory row constitutes a hardware element within the memory array, and a determination of a fault mode of a particular memory row reflects a correlation between the hardware configuration (the row/element) and the historical fault information (the recorded fault history).
Applicant also argues that the cited references, Hong and Qiao, fail to teach or suggest correlating hardware configuration where the hardware configuration includes hardware components of the memory device, components connected to the memory device, and settings of the hardware components. The Examiner respectfully disagrees. As noted above, Qiao teaches recording historical fault information associated with memory rows and determining a fault mode of the row. A memory row is a hardware component of the memory device , and the determination of its fault mode reflects a correlation between a hardware configuration element (the row as part of the memory array) and historical fault data. Oiao’s teaching of fault analysis involves not only the row itself but also the settings and operation of the row within the device configuration, such as identifying whether a row requires corrective action). Hong additionally teaches managing hardware configuration information of the memory device and adjusting operation of the device based on error conditions (Hong, para. [0019] – [0020] teaches comprehensive data about hardware errors being collected; the address information of the hardware error [i.e. the row of the hardware error] is mentioned), which encompasses hardware components connected to the device and their operational settings. Accordingly, the combination of Hong in view of Qiao teaches correlation of historical information with a hardware configuration, where the hardware configuration includes hardware components of the memory device and components connected to the memory device and settings of the hardware components.
The objection to the specification under 37 CFR 1.72(b) made in the Non-Final Office Action mailed April 23rd, 2025 is also maintained. The abstract currently appears as an image of the WIPO publication front page rather than a concise, clearly written abstract as required for a U.S. patent application. Applicant is reminded that the abstract must consist of a concise statement of the technical disclosure of the patent, as set forth in MPEP § 608.01(b).
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 21-22, 25, 28, and 30-40 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 2022/0318087; EFD: 04/30/2021), hereinafter Hong, in view of Qiao et al. (US 2022/0148674; Foreign Priority EFD: 06/20/2020), hereinafter Qiao.
Regarding claim 21, Hong teaches an apparatus to respond to a memory fault, comprising: a substrate; and a controller disposed on the substrate (Hong, para. [0006], lines 2-9, "a Baseboard Management Controller (BMC) configured on the motherboard of the server computer can monitor the error events in the microprocessor of the server computer, retrieve the error data from the MCA registers in response to a hardware error, and store the error data from MCA registers into a storage area of the Baseboard Management Controller (BMC) for subsequent error analysis, diagnosis, etc."; the motherboard equates to a substrate, and the BMC equates a controller), the controller to detect an uncorrectable error (UE) in data from a memory device (Hong, para. [0051], lines 1-4, "At block 161, a processor 101 of a computing system (e.g., as illustrated in FIG. detects an error in a memory module 113 [or in another hardware component of the computing system]"; para. [0016], lines 1-4, "At least some aspects of the present disclosure address the above and other deficiencies by implementing a set of instructions to capture and store comprehensive data about a hardware error, which can be an uncorrectable error"), and wherein the hardware configuration includes settings of the hardware components (Hong, para. [0019] – [0020] teaches comprehensive data about hardware errors being collected; the address information of the hardware error [i.e. the row of the hardware error] is mentioned).
Hong fails to teach correlate a hardware configuration of the memory device with historical data indicating memory faults for hardware elements of the hardware configuration to generate a determination of one of multiple specific hardware elements that likely caused the detected UE, issue a corrective action for one of the multiple specific hardware elements based on the determination, wherein the hardware configuration includes hardware components of the memory device and components connected to the memory device, and wherein to correlate the hardware configuration of the memory device with the historical data includes correlation to the multiple specific hardware elements of the memory device.
However, Qiao, in an analogous art, teaches correlate a hardware configuration of the memory device with historical data indicating memory faults for hardware elements of the hardware configuration (Qiao, Fig. 1, block 101; para. [0094], lines 1-4, "Step 101: Start fault analysis for a memory at a first moment, where the fault analysis includes: obtaining a current fault analysis result of the memory by analyzing historical fault information"; para. [0099], lines 1-2, "Optionally, the first moment is a moment before a UCE fault occurs in a computer system") to generate a determination of a specific hardware element that likely caused the detected UE (Qiao, para. [0052] -para. [0053], "Optionally, if the fault analysis result includes a fault mode, the handling module includes: a first recovery submodule, configured to start fault recovery for the memory when the fault mode is a memory row fault…"; the fault analysis result equates to a determination and the faulty memory row equates to a specific hardware element), issue a corrective action for the specific hardware element based on the determination (Qiao, Fig. 1, block 102, para. [0148] - para. [0149], lines 1-4, "Step 102: Start fault recovery for the memory based on the current fault analysis result of the memory. In this embodiment of this application, when the fault analysis result includes the fault mode, and the current fault mode of the memory is the memory row fault, the computer device starts fault recovery for the memory"; the fault recovery process equates to corrective action), wherein the hardware configuration includes hardware components of the memory device and components connected to the memory device (Qiao, para. [0003], lines 1-4, “A memory is an important part of a device. Generally, the memory includes a plurality of banks (also referred to as storage matrices), and each bank includes a plurality of memory rows”; the memory rows equate to hardware components), and wherein to correlate the hardware configuration of the memory device with the historical data includes correlation to the multiple specific hardware elements of the memory device (Qiao, Fig. 4 teaches recording historical fault information and then using the fault information to determine a fault mode of a memory row; the memory row equates to hardware elements and the fault mode determination equates to correlating hardware configuration).
Hong and Qiao are both considered to be analogous to the claimed invention because both are in the same field of memory systems that handle errors and/or faults that occur in memory.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Hong to incorporate the teachings of Qiao by including the functionality of correlating hardware configuration with historical data indicating memory faults for hardware elements, determining the specific hardware element that caused the uncorrectable error, and performing corrective action to mitigate the error.
The suggestion/motivation for doing so would be to analyze the error more accurately and to recover the fault or error to prevent system breakdown (Qiao, para. [0082], lines 1-9, “fault analysis result is obtained by analyzing historical fault information, and then memory fault recovery is performed based on the fault analysis result. In the solutions, a memory fault can be analyzed more accurately. In addition, in the solutions, memory fault recovery can be started without cold reset, and the memory fault can be recovered in time, thereby preventing system breakdown and reducing adverse impact on services”).
Regarding claim 22, the combination of Hong in view of Qiao teaches the apparatus of claim 21, wherein to correlate the hardware configuration with the historical data comprises the controller to monitor correctable errors (CEs) and uncorrectable errors (UEs) (Qiao, para. [0022], lines 1-4, "It should be noted that the historical fault information further includes a fault type and fault correction information of the memory fault that occurs in the historical time period. The fault type includes a CE type and a UCE type") for the hardware elements of the hardware configuration (Qiao, para. [0004], lines 5-7, "If a memory fault in a memory row is detected, it is considered that a memory row fault occurs, and the faulty memory row is referred to as a faulty row"; the memory row is the hardware element).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Hong to incorporate the teachings of Qiao by including the functionality of the correlation of the hardware configuration with historical data comprising monitoring both CEs and UEs.
The suggestion/motivation for doing so would be to predict the severity of the fault or error (Qiao, para. [0013], lines 1-4, “It should be noted that the computer device periodically analyzes the historical fault information, to predict severity of the memory fault in time and recover the memory fault in time”).
Regarding claim 25, the combination of Hong in view of Qiao teaches the apparatus of claim 21, wherein to issue the corrective action comprises the controller to trigger row sparing for the one of the multiple specific hardware elements (Qiao, para. [0016], lines 1-8, "In this embodiment of this application, if the fault analysis result includes a fault mode, the starting fault recovery for the memory by the computer device based on the current fault analysis result of the memory includes: when the fault mode is a memory row fault, starting fault recovery for the memory, where the fault recovery includes: replacing a faulty row with a redundant row, and recovering data in the redundant row"; the replacing of the faulty row with a redundant row equates to row sparing).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Hong to incorporate the teachings of Qiao by including the functionality of the corrective action triggered by the controller, to be row sparing for the hardware element.
The suggestion/motivation for doing so would be to recover data that may have been affected by the fault or error (Qiao, para. [0029], lines 9-12, “when determining that the fault mode is the memory row fault, the computer device replaces the faulty row with the redundant row in the memory, and recovers the faulty data”).
Regarding claim 28, the combination of Hong in view of Qiao teaches the apparatus of claim 21, wherein the one of the multiple specific hardware elements comprises one or more of a row of memory, a column of memory, or a bit of memory (Hong, para. [0019], lines 19-23, " the address information of the hardware error (e.g., the identification of a memory module, a group of memory bank in the memory module, a memory bank in the group, a row and a column in the memory bank in which the hardware error occur").
Regarding claim 30, the combination of Hong in view of Qiao teaches the apparatus of claim 21, wherein the substrate comprises a motherboard, wherein the controller comprises a controller on a motherboard (Hong, para. [0006], lines 2-9, "a Baseboard Management Controller (BMC) configured on the motherboard of the server computer can monitor the error events in the microprocessor of the server computer, retrieve the error data from the MCA registers in response to a hardware error, and store the error data from MCA registers into a storage area of the Baseboard Management Controller (BMC) for subsequent error analysis, diagnosis, etc."").
Regarding claim 31, the combination of Hong in view of Qiao teaches the apparatus of claim 21, wherein the memory device comprises a memory module with multiple dynamic random access memory (DRAM) devices (Hong, para. [0087], lines 1-7, "The memory modules 113 can include any combination of the different types of non-volatile memory components and/or volatile memory components. The volatile memory devices can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM)").
Regarding claim 32, the combination of Hong in view of Qiao teaches the apparatus of claim 21, wherein the memory device comprises a high bandwidth memory (HBM) device (Hong, para. [0075], lines 1-4, "The machine can be a server, a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a network router, a switch or bridge"; all of the devices taught in the reference can equate high bandwidth memory devices) with multiple dynamic random access memory (DRAM) chips (Hong, para. [0076], lines 1-4, "The example computer system 200 includes a processing device 202, a main memory 204 [e.g., read-only memory (ROM), flash memory, dynamic random access memory DRAM]"; the main memory of the computer system being DRAM implies that the device can be DRAM, and DRAM devices inherently contain DRAM chips").
Regarding claim 33, Hong teaches A system comprising:
a host hardware platform including a central processing unit (CPU) and multiple
memory devices (Hong, para. [0080], lines 1-7, "In general, a computing device to implement the techniques of FIGS. 2 and/or 3 can be a computing system having a host system and a memory sub-system. The memory sub-system can include media, such as one or more volatile memory devices, one or more non-volatile memory devices (e.g., memory module 113), or a combination of such"; para. [0084], lines 1-2, "The host system can include a processor chipset [e.g., processor 101]"); and
a controller coupled to the memory devices (Hong, para. [0024], lines 1-3, "The processor 101 includes a memory controller 105 that can load instructions 115 from the memory modules 113 for execution"), the controller to detect an uncorrectable error (UE) in data from a memory device (Hong, para. [0051], lines 1-4, "At block 161, a processor 101 of a computing system (e.g., as illustrated in FIG. detects an error in a memory module 113 [or in another hardware component of the computing system]"; para. [0016], lines 1-4, "At least some aspects of the present disclosure address the above and other deficiencies by implementing a set of instructions to capture and store comprehensive data about a hardware error, which can be an uncorrectable error"), and wherein the hardware configuration includes settings of the hardware components (Hong, para. [0019] – [0020] teaches comprehensive data about hardware errors being collected; the address information of the hardware error [i.e. the row of the hardware error] is mentioned).
Hong fails to teach correlate a hardware configuration of the memory device with historical data indicating memory faults for hardware elements of the hardware configuration to generate a determination of a specific hardware element that likely caused the detected UE, issue a corrective action for the specific hardware element based on the determination, wherein the hardware configuration includes hardware components of the memory device and components connected to the memory device, and wherein to correlate the hardware configuration of the memory device with the historical data includes correlation to the multiple specific hardware elements of the memory device.
However, Qiao, teaches correlate a hardware configuration of the memory device with historical data indicating memory faults for hardware elements of the hardware configuration (Qiao, Fig. 1, block 101; para. [0094], lines 1-4, "Step 101: Start fault analysis for a memory at a first moment, where the fault analysis includes: obtaining a current fault analysis result of the memory by analyzing historical fault information"; para. [0099], lines 1-2, "Optionally, the first moment is a moment before a UCE fault occurs in a computer system") to generate a determination of a specific hardware element that likely caused the detected UE (Qiao, para. [0052] -para. [0053], "Optionally, if the fault analysis result includes a fault mode, the handling module includes: a first recovery submodule, configured to start fault recovery for the memory when the fault mode is a memory row fault…"; the fault analysis result equates to a determination), issue a corrective action for the specific hardware element based on the determination (Qiao, Fig. 1, block 102, para. [0148] - para. [0149], lines 1-4, "Step 102: Start fault recovery for the memory based on the current fault analysis result of the memory. In this embodiment of this application, when the fault analysis result includes the fault mode, and the current fault mode of the memory is the memory row fault, the computer device starts fault recovery for the memory"; the fault recovery process equates to corrective action), wherein the hardware configuration includes hardware components of the memory device and components connected to the memory device (Qiao, para. [0003], lines 1-4, “A memory is an important part of a device. Generally, the memory includes a plurality of banks (also referred to as storage matrices), and each bank includes a plurality of memory rows”; the memory rows equate to hardware components), and wherein to correlate the hardware configuration of the memory device with the historical data includes correlation to the multiple specific hardware elements of the memory device (Qiao, Fig. 4 teaches recording historical fault information and then using the fault information to determine a fault mode of a memory row; the memory row equates to hardware elements and the fault mode determination equates to correlating hardware configuration).
Hong and Qiao are both considered to be analogous to the claimed invention because both are in the same field of memory systems that handle errors and/or faults that occur in memory.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Hong to incorporate the teachings of Qiao by including the functionality of correlating hardware configuration with historical data indicating memory faults for hardware elements, determining the specific hardware element that caused the uncorrectable error, and performing corrective action to mitigate the error.
The suggestion/motivation for doing so would be to analyze the error more accurately and to recover the fault or error to prevent system breakdown (Qiao, para. [0082], lines 1-9, “fault analysis result is obtained by analyzing historical fault information, and then memory fault recovery is performed based on the fault analysis result. In the solutions, a memory fault can be analyzed more accurately. In addition, in the solutions, memory fault recovery can be started without cold reset, and the memory fault can be recovered in time, thereby preventing system breakdown and reducing adverse impact on services”).
Claim 34 is a system with limitations similar to the apparatus of claim 22, and is rejected under the same rationale.
Claim 35 is a system with limitations similar to the apparatus of claim 25, and is rejected under the same rationale.
Claim 36 is a system with limitations similar to the apparatus of claim 26, and is rejected under the same rationale.
Regarding claim 37, the combination of Hong in view of Qiao teaches the system of claim 33, further comprising one or more of:
a display communicatively coupled to the CPU; a network interface communicatively coupled to a host processor (Hong, para. [0074], lines 5-7, “the computer system 200 can correspond to a host system that includes, is coupled to, or utilizes a memory sub-system”; para. [0077], lines 15-17, "The computer system 200 can further include a network interface device 208 to communicate over the network 220"); or a battery to power the system.
Claim 38 is a method with limitations similar to the apparatus of claim 21, and is rejected under the same rationale.
Claim 39 is a method with limitations similar to the apparatus of claim 22, and is rejected under the same rationale.
Claim 40 is a method with limitations similar to the apparatus of claim 25, and is rejected under the same rationale.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Qiao, as applied to claim 21 above, and further in view of ComputeExperts. “The Unique Set of RAS Features in HPE Superdome Flex: How They Work and Why They Matter.” Community.Hpe.Com, 17 May 2018., hereinafter ComputeExperts.
Regarding claim 23, the combination of Hong in view of Qiao, teaches the apparatus of claim 21, but fails to teach wherein to issue the corrective action comprises the controller to trigger an application of adaptive double device data correction (ADDDC) to correct for the one of the multiple specific hardware elements.
However, ComputeExperts, in an analogous art, teaches the apparatus of claim 21, but fails to teach wherein to issue the corrective action comprises the controller to trigger an application of adaptive double device data correction (ADDDC) to correct for the one of the multiple specific hardware elements (ComputeExperts, para. 11, lines 2-3, " ADDDC determines when the first DRAM in a rank has failed, corrects the data, and maps that DRAM out of use by moving its data to spare bits in the rank”).
Hong, Qiao and ComputeExperts are considered to be analogous to the claimed invention because all three references are in the same field of improving the reliability of memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Hong in view of Qiao to incorporate the teachings of ComputeExperts by including the functionality of the corrective action ADDDC.
The suggestion/motivation for doing so would be to reduce the changes of memory-related crashes (ComputeExperts, para. 12, lines 1-2, “ADDDC drastically improves system uptime, as fewer failed DIMMs need to be replaced, and significantly reduces the chances of memory-related crashes”).
Claims 24 and 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Qiao, as applied to claim 21 above, and further in view of Williams et al. (US 6,823,476), hereinafter Williams.
Regarding claim 24, the combination of Hong in view of Qiao, teaches the apparatus of claim 21, but fails to teach wherein to issue the corrective action comprises the controller to trigger page offlining of the one of the multiple specific hardware elements, or to trigger cache line sparing for the one of the multiple specific hardware elements.
However, Williams, in an analogous art, teaches wherein to issue the corrective action comprises the controller to trigger page offlining of the one of the multiple specific hardware elements, or to trigger cache line sparing for the one of the multiple specific hardware elements (Williams, col. 1, lines 52-55, "fault in cache 12 may cause an error in a data value stored in the cache. If the data in cache 12 is in a modified or "dirty" state, it may have to be copied out of the cache so that other processors can use it"; copying the data out of the cache equates to cache-line sparing).
Hong, Qiao and Williams are considered to be analogous to the claimed invention because all three references are in the same field of memory systems that handle errors and/or faults that occur in memory.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Hong in view of Qiao to incorporate the teachings of Williams by including the functionality of the corrective action being page offlining or cache line sparing.
The suggestion/motivation for doing so would be to allow the system to continue operating despite the error (Williams, col. 1, lines 52-55, "fault in cache 12 may cause an error in a data value stored in the cache. If the data in cache 12 is in a modified or "dirty" state, it may have to be copied out of the cache so that other processors can use it”).
Regarding claim 26, the combination of Hong in view of Qiao, teaches the apparatus of claim 21, but fails to teach wherein the controller is to store the determination in a nonvolatile memory with memory health information for the memory device.
However, Williams teaches wherein the controller is to store the determination in a nonvolatile memory with memory health information for the memory device (Williams, col. 5, lines 49-53, "If the error is not correctable, several actions are taken by the status/diagnosis unit, regardless of whether or not the flag indicates that the data is unusable. These actions include: storing status information…"; Fig. 2a teaches the status/diagnosis unit being located in a memory subsystem).
Hong, Qiao and Williams are considered to be analogous to the claimed invention for the reasoning discussed in claim 24’s rejection.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Hong in view of Qiao to incorporate the teachings of Williams by including the functionality of storing memory health information for the memory device in a nonvolatile memory.
The suggestion/motivation for doing so would be to make the memory health information available to the memory in order for the memory to use any information useful to the diagnosis of the error or fault. (Williams, col. 10, lines 14-17, "FIG. 7 also depicts an input for additional information to show that any information which might be useful in diagnosis of hardware faults may be included in the status information”).
Regarding claim 27, the combination of Hong in view of Qiao, teaches the apparatus of claim 21, wherein the controller is to generate memory health information that includes a determination that the detected UE has an indeterminate cause (Hong, para. [0035], lines 10-11, "the error log 127 in the Baseboard Management Controller (BMC)"; para. [0036], lines 1-5, "The error handler 121 in the Basic Input/Output System (BIOS) 117 can pass the error log 127 about the current hardware error to the operating system 119 after the execution of the operating system 119 is restarted following an uncorrectable error"; the error log equates to memory health information), but fails to teach wherein the controller is to identify more than one specific component as the likely cause of the detected UE.
However, Williams teaches wherein the controller is to identify more than one specific component as the likely cause of the detected UE (Williams, col. 6, lines 58-63, "after detection of uncorrectable errors, a new error detection/correction code is generated for the unusable data and the corresponding flag. Because a new error detection/correction code is generated, additional errors can be detected and diagnosis of the hardware faults that caused the additional errors can be initiated"; the detecting of uncorrectable errors and the diagnosis of hardware faults that caused additional errors equates to identifying more than one component as the likely cause of the detected UE ).
Hong, Qiao and Williams are considered to be analogous to the claimed invention for the reasoning discussed in claim 24’s rejection.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Hong in view of Qiao to incorporate the teachings of Williams by including the functionality of having the controller identifying more than one specific component that may have caused a detected UE.
The suggestion/motivation for doing so would be to make sure all possible causes of the UE are detected and diagnosed (Williams, col. 6, lines 58-63, "after detection of uncorrectable errors, a new error detection/correction code is generated for the unusable data and the corresponding flag. Because a new error detection/correction code is generated, additional errors can be detected and diagnosis of the hardware faults that caused the additional errors can be initiated").
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Qiao, as applied to claim 21 above, and further in view of Higeta et al. (US 2012/0239996), hereinafter Higeta.
Regarding claim 29, the combination of Hong in view of Qiao, teaches the apparatus of claim 21, but fails to teach wherein the substrate comprises a board of a dual in line memory module (DIMM), wherein the controller comprises a controller of the DIMM.
However, Higeta, in an analogous art, teaches wherein the substrate comprises a board of a dual in line memory module (DIMM) (Higeta, para. [0039], lines 4-7, "The description will be made taking a system board 1 as an example of the information processing apparatus. The system board 1 includes memory modules 11a and 11b, memory controllers 12a and 12b"; para. [0044], lines 2-3, "Examples of the memory module 11a include a DIMM (Dual Inline Memory Module)"), wherein the controller comprises a controller of the DIMM (Higeta, para. [0040], lines 1-2, "The memory controller 12a is connected to the memory module 11a"; the controller being connected to a DIMM can imply that the controller has DIMM capabilities).
Hong, Qiao and Higeta are considered to be analogous to the claimed invention because all three references are in the same field of memory systems that handle errors and/or faults that occur in memory.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Hong in view of Qiao to incorporate the teachings of Higeta by including a substrate with a DIMM board, and a DIMM controller.
The suggestion/motivation for doing so would be to accommodate a memory of a large capacity device with a large capacity allow the system to continue operating despite the error (Higeta, para. [0003], lines 1-5, “As sizes of information processing apparatuses are getting larger, capacities of implemented memories are increased and high reliability is desired. Examples of a memory module having a large capacity include a DIMM (Dual Inline Memory Module)”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bock et al. (US 7,856,575) teaches a troubleshooting method of computer systems utilizing a fault tree analysis to determine the root cause of a fault that occurred.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE V BRADEN whose telephone number is (703)756-5381. The examiner can normally be reached Mon-Fri: 9AM-5:30 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/ Supervisory Patent Examiner, Art Unit 2112