DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 39 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
Amendments made in Applicant Arguments/Remarks Made in an Amendment of 05/12/2026 overcome the previous 35 USC § 112 rejections of claims 22, 25 and 31-32 made in the Non-Final Rejection Office Action mailed on 03/04/2026, therefore 35 USC § 112 rejections of claims 22, 25 and 31-32 in the Non-Final Rejection Office Action mailed on 03/04/2026 are withdrawn.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 39 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 39 recites the limitation "the semiconductor chip" in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, the Examiner interprets “the semiconductor chip” as “the semiconductor chip element”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 39, 22,25-28, 33-34 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2021/0175135 A1, hereinafter Hsu ‘135) in view of de Guzman et al. (US 7,576,401 B1, hereinafter de Guzman ‘401) in view of the following arguments.
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With respect to Claim 39 Hsu ‘135 discloses a semiconductor device (device 10 shown in Fig. 10) comprising:
a planar carrier (10, Fig 10, Para [0115]) having a main surface (top of 10) on which a semiconductor chip element (11/112, Fig 10, Para [0028], hereinafter SE) is mounted (disclosed in Fig 10 and Para [0029]), the semiconductor chip (Note examiner’s interpretation of “the semiconductor chip” as “the semiconductor chip element”)(SE) comprising at least one semiconductor chip (Fig 10 and Para [0028] discloses 11 as electronic device);
at least one wire connection (12, Fig 10, Para [0115]) between the main surface (top of 10) of the carrier (10) and a top surface (top of 11) of the at least one semiconductor chip (11)(Fig 10 discloses connecting top of 11 to carrier 10);
a first material (19, Fig 10, Para [0117]) completely enclosing (disclosed in Fig 10 and Para [0117]) the wire connection (12) and comprising a first plastic material (Para [0118] discloses 19 as epoxy); and
a second material (13, Fig 10, Para [0033]) forming a frame (Para [0033] discloses 13 has a rectangular shape) and surrounding a cavity (cavity as shown in annotated Fig 10 of Hsu ‘135, Para [0053], hereinafter CAV)(Para [0035] discloses 13 is used to hermetically seal the panel 14 to chip 11, no material has been placed in the space between 11 and 14, therefore it is obvious that there is a cavity between 11 and 14),
wherein the top surface (top of 11) of the at least one semiconductor chip (11) has a region that is free (region shown in annotated Fig 10 of Hsu ‘135) of the first (19) and second materials (13) and is arranged in the cavity (CAV),
wherein the top surface (top of 11) of the at least one semiconductor chip (11) has a region that is free of any material (annotated Fig 10 of Hsu ‘135 discloses a region of 11 that has a region free of any material),
But Hsu ‘135 fails to explicitly disclose and wherein the semiconductor chip element comprises, as the at least one semiconductor chip, an electronic semiconductor chip having the top surface on which an optoelectronic semiconductor chip is mounted, the optoelectronic semiconductor chip being spaced apart from the first and second materials in the cavity.
Nevertheless, in a related endeavor (Fig 10 of de Guzman ‘401), de Guzman ‘401 teaches and wherein the semiconductor chip element (1002/114, Fig 10 of de Guzman ‘401, Col 7, Line 36 and 43-44) comprises, as the at least one semiconductor chip (1002, Fig 10 of de Guzman ‘401, Col 7, Line 36) comprises, as the at least one semiconductor chip (1002, Fig 10 of de Guzman ‘401, Col 7, Line 36) an electronic semiconductor chip (1002, Fig 10 of de Guzman ‘401, Col 7, Line 36) having the top surface (top of 1002) on which an optoelectronic semiconductor chip (114, Fig 10 of de Guzman ‘401, Col 7, Line 43-44) is mounted (disclosed in Fig 10 of de Guzman ‘401 and Col 7, Lines 43-44).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate de Guzman ‘401’s teaching of and wherein the semiconductor chip element and wherein the semiconductor chip element comprises, an electronic semiconductor chip having the top surface on which an optoelectronic semiconductor chip is mounted, into Hsu ‘135’s device. Hsu ‘135 teaches an image sensor with a semiconductor chip element comprises a semiconductor chip upon which is mounted an optical component (Para [0028]) but is silent on the details of the optical component. de Guzman ‘401 also teaches an image sensor with a semiconductor chip element comprises comprising an electronic semiconductor chip with an optoelectronic semiconductor chip mounted on the semiconductor chip. The ordinary artisan would have been motivated to modify Hsu ‘135, therefore, in the manner set forth above, at least, because as de Guzman ‘401 provides details for the optical component on the semiconductor and further by the teachings of Col 8, Lines 23-32, that the stacked chip arrangement reduces the size of the substrate allowing for a smaller device footprint which enables further miniaturization of the end device.
As incorporated, the teaching of de Guzman ‘401 of the optoelectronic semiconductor chip (114) of de Guzman ‘401 would be used as the optical component (112) of Hsu ‘135.
Hsu ‘135 as modified by de Guzman ‘401 discloses the optoelectronic semiconductor chip (114 of de Guzman ‘401 as incorporated above) being spaced apart from the first (19) and second materials (13) in the cavity (CAV)(Fig 10 of Hsu ‘135 discloses 112 of Hsu ‘135 is spaced apart from first and second materials in the cavity, therefore, as incorporated in Hsu ‘135 as described above, 114 de Guzman ‘401 is spaced apart from the first and second materials.
With respect to Claim 22 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 39, but Hsu ‘135 as modified by de Guzman ‘401 fails to explicitly disclose wherein the first plastic material (19) is plastically and/or elastically deformable.
However, de Guzman ‘401 discloses first plastic material (19) as epoxy, witch Examiner notes is the same material disclosed as the first plastic material (41) disclosed the instant application in the Specification [0074]. Therefore the epoxy of Hsu ‘135 must behave the same as the epoxy of the instant application.
With respect to Claim 25 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 39, and Hsu ‘135 further discloses wherein the second material (13) is non-elastic (Para [0033] discloses 13 as metal) and harder than the first material (19)(one of ordinary skill in the art would recognize metal as harder than the epoxy of 19).
With respect to Claim 26 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 39, and Hsu ‘135 further discloses wherein the second material (13) comprises one or more materials selected from a third plastic material, a semiconductor material, or a metal material. (Para [0033] discloses 13 as metal material).
With respect to Claim 27 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 26, wherein the third plastic material comprises an epoxy or a black silicone. (Regarding the limitations of claim 27, the alternative of the third plastic material was not chosen as the second material, accordingly further limitations regarding this materials do not impart patentable weight.)
With respect to Claim 28 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 26, wherein the semiconductor material comprises silicon. (Regarding the limitations of claim 28, the alternative of the semiconductor material was not chosen as the second material, accordingly further limitations regarding this material do not impart patentable weight).
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With respect to Claim 33 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 20, and de Guzman ‘401 further teaches wherein the first material (130/1010, Fig 10 of de Guzman ‘401, Col 4, Line 6 and Col 7, Lines 44-45) is arranged in the cavity (128, Fig 10 of de Guzman ‘401, Col 4, Lines 2-3)(annotated Fig 10 of de Guzman ‘401 discloses portions of first material layer 1010 in the area framed by second material 126 defining the cavity)
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate de Guzman ‘401’s further teaching of wherein the first material is arranged in the cavity into Hsu ‘135 as modified by de Guzman ‘401’s device. The ordinary artisan would have been motivated to further modify Hsu ‘135 as modified by de Guzman ‘401, therefore, in the manner set forth above, at least, because as de Guzman ‘401 teaches in Col 8, Lines 23-32, the stacked chip arrangement, which incorporates the first material being partially arranged in the cavity, reduces the size of the substrate allowing for a smaller device footprint which enables further miniaturization of the end device.
As incorporated, the structure as taught by de Guzman ‘401 wherein the first material (130/1010) of de Guzman ‘401 is partially arranged in the cavity would be used so that the first material (19) of Hsu ‘135 as modified by de Guzman ‘401 is partially arranged in the cavity.
With respect to Claim 34 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 20, and de Guzman ‘401 further teaches wherein the second material (126, Fig 10 of de Guzman ‘401, Col 8, Line 21) covers the first material (130/1010, Fig 10 of de Guzman ‘401, Col 4, Line 6 and Col 7, Lines 44-45) (annotated Fig 10 of de Guzman ‘401 discloses second material layer 126 over areas of first material 130/1010).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate de Guzman ‘401’s further teaching of wherein the second material covers the first material into Hsu ‘135 as modified by de Guzman ‘401’s device. The ordinary artisan would have been motivated to modify Hsu ‘135 as modified by de Guzman ‘401, therefore, in the manner set forth above, at least, because as de Guzman ‘401 teaches in Col 8, Lines 23-32, the stacked chip arrangement, which incorporates the second material over the first material, reduces the size of the substrate allowing for a smaller device footprint which enables further miniaturization of the end device.
As incorporated, the structure as taught by de Guzman ‘401 wherein the second material (126) of de Guzman ‘401 is over the first material (130/1010) of de Guzman ‘401 would be used so that second material (13) is over first material (19) of Hsu ‘135 as modified by de Guzman ‘401.
With respect to Claim 36 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 39, and Hsu ‘135 discloses further comprising a cover element (14, Fig 10, Para [0115]) comprising a wavelength conversion material and/or a window element and/or a protective film (Para [0115] discloses 14 as a transparent panel), wherein the cover element (14) is arranged in or on the cavity (CAV) above the at least one semiconductor chip (11)(Fig 10 discloses 14 arranged over CAV and above chip 11).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘135 in view of de Guzman ‘401 in further view of Hartung et al. (US 2018/0033711 A1, hereinafter Hartung ‘711), in view of the following arguments.
With respect to Claim 23 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 39, but Hsu ‘135 as modified by de Guzman ‘401 fails to discloses wherein the first plastic material comprises silicone.
However, in a related endeavor (Fig 4A-4E of Hartung ‘711), Hartung ‘711 teaches wherein the first plastic material (51, Fig 4C of Hartung ‘711, Para [0046]) comprises silicone (Para [0046] discloses 51 as silicone).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Hartung ‘711’s teaching of wherein the first plastic material comprises silicone into Hsu ‘135 as modified by de Guzman ‘401’s device. Hsu ‘135 as modified by de Guzman ‘401 teaches an image sensor with a semiconductor chip element comprises comprising an electronic semiconductor chip with an optoelectronic semiconductor chip mounted on the semiconductor chip wherein the semiconductor chip has a resin over its wire bonds. Hartung ‘711 teaches a semiconductor device with wire bonds that are encapsulated with a silicon resin. The ordinary artisan would have been motivated to modify Hsu ‘135 as modified by de Guzman ‘401 in the manner set forth above, at least, because, as Hartung ‘711 teaches in Para [0046] that silicone resins keep thermomechanical stress low, which is a concern that Hsu ‘135 discloses as an issue for the epoxy resin. The use of the silicone resin as taught by Hartung ‘711 in Hsu ‘135 as modified by de Guzman ‘401 would be motivating to one of ordinary skill in the art to lower stress observed in the wire bond, thereby potentially increase device reliability.
As incorporated, the use of first plastic material comprises silicone taught by Hartung ‘711 would be used as the material of first plastic material (19) of Hsu ‘135 as modified by de Guzman ‘401.
Claims 24 and 37-38 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘135 in view of de Guzman ‘401 and in further view of Tamura et al. (US 5,122,861, hereinafter Tamura ‘861), in view of the following arguments.
With respect to Claim 24 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 39, but Hsu ‘135 as modified by de Guzman ‘401 fails to disclose wherein the first material comprises a second plastic material different from the first plastic material and from the second material, which is arranged on the first plastic material and which, together with the first plastic material, completely encloses the at least one wire connection.
Nevertheless, in a related endeavor (Fig 1-3, 7 and 13 of Tamura ‘861), Tamura ‘861 teaches wherein the first material (43/44, Fig 13 of Tamura ‘861, Col 10, Lines 65 and Col 10, Lines 67-68) comprises a second plastic material (44, Fig 13 of Tamura ‘861, Col 10, Lines 67-68) different from the first plastic material (43, Fig 13 of Tamura ‘861, Col 10, Lines 65)(Col 11, Lines 1-2 of Tamura ‘861 disclose 44 as epoxy resin and Col 11, Lines 3-4 of Tamura ‘861 disclose 43 as silicon resin), which is arranged on (disclosed in Fig 13 of Tamura ‘861) the first plastic material (43) and which, together with the first plastic (43) material, completely encloses the at least one wire connection (9, Fig 3 of Tamura ‘861, Col 4, lines 51)(Fig 13 of Tamura ‘861 disclose 43/44 completely encloses wire connector 9).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Tamura ‘861’s teaching of wherein the first material comprises a second plastic material different from the first plastic material, which is arranged on the first plastic material and which, together with the first plastic material, completely encloses the at least one wire connection into Hsu ‘135 as modified by de Guzman ‘401’s device. Hsu ‘135 as modified by de Guzman ‘401 teaches an image sensor with a material covering the wire connection but notes that the epoxy may expand due to humidity which will create stress that could potentially damage the device. Tamura ‘861 teaches an image sensor and provides details for using an encapsulant made of different layers of silicon and epoxy. The ordinary artisan would have been motivated to modify Hsu ‘135 as modified by de Guzman ‘401, therefore, in the manner set forth above, at least, because as Tamura ‘861 teaches in Col 5, Lines 39-50, using the two layer encapsulant arrangement provides moisture resistance to the device, thereby increasing reliability.
As incorporated, the teaching of Tamura ‘861 wherein the first material (43/44) comprises a second plastic material (44) different from the first plastic material (43) would be used as the first material (19) of Hsu ‘135 as modified by de Guzman ‘401 so that the first and second plastic materials completely encloses the at least one wire connection (12) of Hsu ‘135 as modified by de Guzman ‘401.
Hsu ‘135 as modified by de Guzman ‘401 as further modified by Tamura ‘861 discloses second plastic material (44 of Tamura ‘861 as incorporated above) different from the second material (13)( Col 11, Lines 1-2 of Tamura ‘861 disclose 44 as epoxy resin and Para [0033] of Hsu ‘135 discloses 13 as metal).
With respect to Claim 37 A method for manufacturing the semiconductor device according to claim 39 (Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 39), and Hsu ‘135 further discloses the method comprising:
Mounting (Para [0029] discloses 11 disposed on 10) the semiconductor chip element (SE) having the at least one semiconductor chip (11) on the carrier (10) and electrically contacting (Para [0029] discloses 11 electrically connected to carrier 10) the main surface (top of 10 as shown in Fig 10) of the carrier (10) and the top surface (top of 11 as shown in Fig 10) of the at least one semiconductor chip (11) with the at least one wire connection (12)(Para [0029] discloses 11 electrically connected to carrier 10 by wire bond 12);
completely enclosing (disclosed in Fig 10 and Para [0117]) the at least one wire connection (12) with the first material (19) and
applying (Para [0034] discloses 13 disposed on device which is mounted to the carrier) the second material (13) to the carrier (10).
But Hsu ‘135 as modified by de Guzman ‘401 fails to explicitly disclose completely enclosing the at least one wire connection with the first material comprising by vacuum injection molding, by a film-assisted molding process, by a casting process, by a spraying process, and/or by a sacrificial layer process.
Nevertheless, in a related endeavor (Fig 13 of Tamura ‘861), Tamura ‘861 teaches completely enclosing (Fig 13 discloses 43 encloses wire connectors) the at least one wire connection (9, Fig 3, Col 4, lines 51) with a first material (material of 43, Fig 13, Col 11, Lines 3-4 disclose 43 as silicone) comprising a first plastic material (Col 11, Lines 3-4 disclose 43 as silicone) by vacuum injection molding, by a film-assisted molding process, by a casting process, by a spraying process, and/or by a sacrificial layer process; (Col 11, Lines 32-34 disclose resin is filled via potting which a person of ordinary skill in the art will recognize as a casting process).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Tamura ‘861’s teaching of completely enclosing the at least one wire connection with the first material comprising by a casting process into Hsu ‘135 as modified by de Guzman ‘401’s method. Hsu ‘135 as modified by de Guzman ‘401 teaches an image sensor with a material covering the wire connection but notes that the epoxy may expand due to humidity which will create stress that could potentially damage the device. Tamura ‘861 teaches an image sensor and provides details for using an encapsulant made of different layers of silicon and epoxy. The ordinary artisan would have been motivated to modify Hsu ‘135 as modified by de Guzman ‘401, therefore, in the manner set forth above, at least, because as Tamura ‘861 teaches in Col 5, Lines 39-50, using the two layer encapsulant arrangement provides moisture resistance to the device, thereby increasing reliability.
As incorporated, the teaching of Tamura ‘861 of completely enclosing the at least one wire connection with the first material comprising by a casting process would be used as the process to enclose wire connection (12) of Hsu ‘135 as modified by de Guzman ‘401.
With respect to Claim 38 Hsu ‘135 as modified by de Guzman ‘401 and further disclosed by Tamura ‘861 discloses all limitations of the method according to claim 37, and Hsu ‘135 further discloses wherein the first (19) and second materials (13) are applied using the same molding tool (Para [0118] discloses 19 as epoxy and Para [0033] discloses 13 as an epoxy, therefore it would be obvious to one of ordinary skill in the art that the two materials could be applied using same tool).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘135 in view of de Guzman ‘401 and in further view of Murano et al. (US 5,617,131, hereinafter Murano ‘131), in view of the following arguments.
With respect to Claim 29 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the discloses all limitations of the semiconductor device according to claim 26, but Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the fails to explicitly disclose wherein the metal material comprises steel.
Nevertheless, in a related endeavor (Fig 1-4 of Murano ‘131), Murano ‘131 teaches wherein the metal material (9, Fig 3 of Murano ‘131, Col 6, Lines 19-24) comprises steel (Col 6, Lines 19-24 of Murano ‘131 teaches a spacer material 9 is formed of stainless steel).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Murano ‘131’s teaching of wherein the semiconductor material comprises silicon into Hsu ‘135 as modified by de Guzman ‘401’s device. Hsu ‘135 as modified by de Guzman ‘401 teaches a image sensor device with a spacer 13 and discloses it as metal but is open to the material of that spacer. Murano ‘131 also teaches a sensor with a spacer and teaches that stainless steel can be used as that spacer. The ordinary artisan would have been motivated to modify Hsu ‘135 as modified by de Guzman ‘401 in the manner set forth above, at least, because stainless steel is a readily available and well-known material in a semiconductor process, therefore using it as the spacer material can simplify the manufacturing process by requiring less unique materials.
As incorporated, stainless steel spacer taught by Murano ‘131 would be used as the second material (13) of Hsu ‘135 as modified by de Guzman ‘401.
Claims 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘135 in view of de Guzman ‘401 in further view of Watanabe (US 2007/0108578 A1, hereinafter Watanabe ‘578), in view of the following arguments.
With respect to Claim 30 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 39, but Hsu ‘135 as modified by de Guzman ‘401 fails to explicitly disclose wherein the first material is at least partially deposited on the second material as viewed from the carrier.
Nevertheless, in a related endeavor (Fig 10 of Watanabe ‘578), Watanabe ‘578 teaches wherein the first material (25, Fig 10 of Watanabe ‘578, Para [0082]) is at least partially deposited on the second material (100, Fig 10 of Watanabe ‘578, Para [0090]) as viewed from the carrier (24, Fig 10 of Watanabe ‘578, Para [0082]) (Fig 10 and Para [0132] of Watanabe ‘578 discloses 25 over the angled portion of 100).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Watanabe ‘578’s teaching of wherein the first material is at least partially deposited on the second material as viewed from the carrier into Hsu ‘135 as modified by de Guzman ‘401’s device. Hsu ‘135 as modified by de Guzman ‘401 teaches an image sensor with a semiconductor chip element comprises comprising an electronic semiconductor chip with an optoelectronic semiconductor chip mounted on the semiconductor chip wherein the semiconductor chip has a resin over its wire bonds and a second material forming a frame. Watanabe ‘578 also teaches an image sensor with a semiconductor chip element wherein the semiconductor chip has a resin over its wire bonds and a second material forming a frame. The ordinary artisan would have been motivated to modify Hsu ‘135 as modified by de Guzman ‘401 in the manner set forth above, at least, because this layer this configuration would provide some additional mechanical protection to the spacer.
As incorporated, the shape of first (25) and second materials (100) of Watanabe ‘578 wherein the first material is at least partially deposited on the second material as viewed from the carrier would be used as the shape of first material (19) and second material (13) in the device of Hsu ‘135 as modified by de Guzman ‘401 so that first material (19 as modified by Watanabe ‘578) partially covered second material (13 as modified by Watanabe ‘578) as viewed from the carrier (11).
With respect to Claim 31 Hsu ‘135 as modified by de Guzman ‘401 and further modified by Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 30, and Hsu ‘135 as modified by de Guzman ‘401 and further modified by Watanabe ‘578 further discloses wherein the first material (19) completely covers the second material (13) on a side opposite the carrier (11)(as modified above by Watanabe ‘578 the shape of 19 above the shape of 13 would be that of the shape of Fig 10 of Watanabe ‘578 which discloses the first material completely covers the second material on a side opposite the carrier).
With respect to Claim 32 Hsu ‘135 as modified by de Guzman ‘401 and further modified by Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 30, and Hsu ‘135 as modified by de Guzman ‘401 and further modified by Watanabe ‘578 further discloses wherein the first material (19) completely covers the second material (13) on a side opposite the carrier (11)(as modified above by Watanabe ‘578 the shape of 19 above the shape of 13 would be that of the shape of Fig 10 of Watanabe ‘578 which discloses the first material completely covers the second material on a side opposite the carrier)
And Watanabe ‘578 further teaches except for a viewing window (210, Fig 10, Para [0131]) (Fig 10 and Para [0132] disclose 25 does not cover window 210).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Watanabe ‘578’s further teaching of the first material not covering the viewing window into Hsu ‘135 as modified by de Guzman ‘401 as further modified by Watanabe ‘578’s device. The ordinary artisan would have been motivated to modify Hsu ‘135 as modified by de Guzman ‘401 as further modified by Watanabe ‘578 in the manner set forth above, at least, because leaving this open space allows light to enter the device an impact the optical component.
As incorporated, the further teaching of Watanabe ‘578 wherein the first material covers the second material except for a viewing window would be used in the device of Hsu ‘135 as modified by de Guzman ‘401 as further modified by Watanabe ‘578.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘135 in view of de Guzman ‘401 in further view of Yang (US 11,297,210 B2, hereinafter Yang ‘210), in view of the following arguments.
With respect to Claim 35 Hsu ‘135 as modified by de Guzman ‘401 discloses all limitations of the semiconductor device according to claim 39, and Hsu ‘135 further discloses wherein the semiconductor device (device 10) has a top surface (top of device 10 is facing away from the carrier as shown in Fig 10, hereinafter TS) facing away from the carrier (10), which top surface (TS) is planar (Fig 10 discloses to of device 10 is planar) and
But Hsu ‘135 as modified by de Guzman ‘401 fails to explicitly disclose has an opening through which a portion of the at least one semiconductor chip is exposed.
Nonetheless, in a related endeavor (Fig 2-4 of Yang ‘210), Yang ‘210 teaches an opening (opening shown Fig 2 of Yang ‘210 and disclosed in Col 3, Line 25), through which a portion of the at least one semiconductor chip (2, Fig 2 of Yang ‘210, Col 3, Line 36) is exposed. (Fig 2 of Yang ‘210 discloses a portion of 2 exposed through opening).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yang ‘210’s teaching of an opening through which a portion of the at least one semiconductor chip is exposed into Hsu ‘135 as modified by de Guzman ‘401’s device. Hsu ‘135 as modified by de Guzman ‘401 teaches an image sensor with a semiconductor chip element comprises a semiconductor chip upon which is mounted an optical component. Yang ‘210 also teaches an image sensor with a semiconductor chip element comprises comprising an electronic semiconductor chip light receiving elements. The ordinary artisan would have been motivated to modify Hsu ‘135 as modified by de Guzman ‘401, therefore, in the manner set forth above, at least, because as Yang ‘210 teaches in (Col 3, Lines 25-30) leaving the opening over the image sensor to aid light ray collection.
As incorporated, the teaching of Yang ‘210 of an opening such that a portion of the semiconductor element is exposed would be used in the device of Hsu ‘135 as modified by de Guzman ‘401 such that Hsu ‘135 as modified by de Guzman ‘401 would have an opening above semiconductor chip element (11).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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