DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 22, claim 22 recites the limitation “where the first plastic material is soft and/or elastic”. The terms “soft and/ or elastic” are broad and fail to identify the metes and bounds of the invention. As every physical material has some degree of softness or elasticity, it is unclear what is meant by the limitation of “where the first plastic material is soft and/or elastic”. For purposes of examination, Examiner has interpreted where the first plastic material is soft and/or elastic” as any material with a hardness or modulus value.
Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 25, claim 25 recites the limitation “where the second material is rigid”. The term “rigid” is broad and fails to identify the metes and bounds of the invention. As every physical material has some degree of rigidity, it is unclear what is meant by the limitation of “where the second material is rigid”. For purposes of examination, Examiner has interpreted “where the second material is rigid” as any material with a hardness or modulus value.
Claims 31-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 31-32, those claims recites the limitation “wherein the first material completely covers the second material”. The term “completely covers” is broad and fails to identify the metes and bounds of the invention. Referencing the specification of the instant application for a definition of “completely covers”, Para [0026] directs to Figures 2A and 2B but then notes that the region of a viewing window is open. Further referencing Figures 2A and 2B it is noted that the side and bottom of the second material is left uncovered by the first material. Therefore it is unclear how to interpret the claim limitation “completely covers”. For purposes of examination the Examiner interprets “completely covers” as “covers a side and top surface”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 20, 22-23, 25-27, 30-32 and 35-36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe (US 2007/0108578 A1, hereinafter Watanabe ‘578).
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With respect to Claim 20 Watanabe ‘578 discloses a semiconductor device (210, Fig 10, Para [0131]) comprising:
a planar carrier (24, Fig 10, Para [0082]) having a main surface (top of 24 as shown in annotated Fig 10 of Watanabe ‘578) on which a semiconductor chip element (28, Fig 10, Para [0082]) is mounted (disclosed in Fig 10), the semiconductor chip element (28) having at least one semiconductor chip (Para [0004] discloses sensor 28 as an image sensor package therefore it has at least one chip);
at least one wire connection (27, Fig 10, Para [0082]) between the main surface (top of 24) of the carrier (24) and a top surface (top of 28 as shown in annotated Fig 10 of Watanabe ‘578) of the at least one semiconductor chip (28);
a first material (25, Fig 10, Para [0082]) completely enclosing (Fig 10 and Para [0088] disclose 25 enclosing wire connection) the wire connection (27) and comprising a first plastic material (first material of 25, Para [0089] discloses 25 as silicon group resin); and
a second material (100, Fig 10, Para [0090]) forming a frame (Para [0134] discloses 100 provided on circumferential side surface of structure 210) and surrounding a cavity (cavity (denoted by dimension “a”) over chip 28 and structure 29 as annotated Fig 10 of Watanabe ‘578 and Para [0084], hereinafter cavity),
wherein the top surface (top of 28) of the at least one semiconductor chip (28) has a region (annotated Fig 10 of Watanabe ‘578 discloses region above chip 28 within the inner sides of 100 is free of first and second materials (25 and 100 respectively)) that is free of the first (25) and second materials (100) and is arranged in (disclosed in Fig 10) the cavity (cavity), and
wherein the top surface (top of 28) of the at least one semiconductor chip (28) has a region that is free of any material (annotated Fig 10 of Watanabe ‘578 discloses regions of top of semiconductor chip 28 being free of any material).
With respect to Claim 22 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 20, and Watanabe ‘578 further discloses wherein the first plastic material (first material of 25) is soft and/or elastic (note Examiner interpretation above of “soft and/or elastic” as any material with a hardness or modulus value) (Watanabe ‘578 disclose a first plastic material 25 as silicone, Para [0089] but fails to expressly disclose the material as “soft and/ or elastic”. However, Watanabe ‘578 discloses first plastic material 25 having a Young’s Modulus, which one of ordinary skill in the art will also recognize as an elastic modulus, which is defined as the stress of a material divided by an applied strain at fracture. Having this in mind, Examiner respectfully submits that Watanabe ‘578 inherently discloses first plastic material 25 is soft and/or elastic as it has a Young’s Modulus (modulus of elasticity)).
With respect to Claim 23 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 20, and Watanabe ‘578 further discloses wherein the first plastic material (25) comprises silicone (Para [0089] discloses 25 as silicon group resin).
With respect to Claim 25 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 20, and Watanabe ‘578 further discloses wherein the second material (100) is rigid (reference Examiner’s interpretation of “the second material is rigid” above as any material with a hardness or modulus value) (Watanabe ‘578 disclose a second material 100 as epoxy, Para [0091] with a Young’s Modulus of 0.1-10GPa but fails to expressly disclose the material as “rigid”. However, as noted, Watanabe ‘578 discloses second material having a Young’s Modulus, which one of ordinary skill in the art will also recognize as an elastic modulus, which is defined as the stress of a material divided by an applied strain at fracture. Having this in mind, Examiner respectfully submits that Watanabe ‘578 inherently discloses second material 100 is rigid as it has a Young’s Modulus (modulus of elasticity)).
With respect to Claim 26 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 20, and Watanabe ‘578 further discloses wherein the second material (100) comprises one or more materials selected from a third plastic material (Para [0091] discloses 100 as a material of an epoxy resin, hereinafter 3PM), a semiconductor material, or a metal material.
With respect to Claim 27 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 26, and Watanabe ‘578 further discloses wherein the third plastic material (3PM) comprises an epoxy (Para [0091] discloses 100 as an epoxy resin) or a black silicone.
With respect to Claim 30. Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 20, and Watanabe ‘578 further discloses wherein the first material (25) is at least partially deposited on the second material (100) as viewed from the carrier (24)(Fig 10 and Para [0132] discloses 25 over the angled portion of 100).
With respect to Claim 31 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 30, and Watanabe ‘578 further discloses wherein the first material (25) completely covers (Note; reference above Examiner’s Interpretation of “completely covers” as “covers a side and top surface”) the second material (100)(Fig 10 and Para [0132] discloses 25 over the angled top surface of 100).
With respect to Claim 32 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 30, and Watanabe ‘578 further discloses wherein the first material (25) completely covers (Note; reference above Examiner’s Interpretation of “completely covers” as “covers a side and top surface”) the second material (100) (Fig 10 and Para [0132] discloses 25 over the angled top surface of 100) except for a viewing window (210, Fig 10, Para [0131]) (Fig 10 and Para [0132] disclose 25 does not cover window 210).
With respect to Claim 35 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 20, and Watanabe ‘578 further discloses wherein the semiconductor device (120, Fig 10, Para [0131]) has a top surface (top of device 120 shown in Fig 10) facing away from the carrier (24)(Fig 10 shows top of device facing away from carrier), which top surface (top of device 120) is planar (Fig 10 discloses top surface of 120 as planar) and has an opening (opening in material 25 forming region where 210 is located) through which a portion of the semiconductor chip (28) is exposed (annotated Fig 10 of Watanabe ‘578 discloses regions of 28 exposed in cavity area under opening for 210).
With respect to Claim 36 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 20, and Watanabe ‘578 discloses further comprising a cover element (210, Fig 10, Para [0131]) comprising a wavelength conversion material and/or a window element (Para [0131] discloses 210 as a transparent member) and/or a protective film, wherein the cover element (210) is arranged in or on the cavity (cavity) above the at least one semiconductor chip (28)(Fig 10 discloses 210 is arranged over cavity an is above semiconductor chip 28).
Claims 20 and 37-38 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tamura et al. (US 5,122,861, hereinafter Tamura ‘861).
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With respect to Claim 20 Tamura ‘861 discloses a semiconductor device (Fig 1-3, 7 and 13) comprising:
a planar carrier (47, Fig 13 of Tamura ‘861, Col 11, Lines 12-13) having a main surface (top of carrier 47 as shown in annotated Fig 13 of Tamura ‘861) on which a semiconductor chip element (45/46, Fig 13, Col 11, Lines 9-10 and Col 11, Lines 10-11 and 25) is mounted (disclosed in Fig 13), the semiconductor chip element (45/46) having at least one semiconductor chip (Col 4, Lines 11-2 discloses 45/46 as an image sensor package therefore it has at least one chip);
at least one wire connection (9, Fig 3, Col 4, lines 51) between the main surface (top of 47) of the carrier (47) and a top surface (top of 45/46 as shown in annotated Fig 13 of Tamura ‘861) of the at least one semiconductor chip (Col 4, Lines 11-2 discloses 45/46 as an image sensor package therefore it has at least one chip);
a first material (43, Fig 13, Col 10, Lines 65) completely enclosing (Fig 13 discloses 43 completely enclosing wire connector 9) the wire connection (9) and comprising a first plastic material (Col 11, Lines 3-4 disclose 43 as silicone); and
a second material (44, Fig 13, Col 10, Lines 67-68) forming a frame (Fig 7 discloses recessed area where 43 and 44 are disposed surrounding (“a frame”) around device 45) and surrounding a cavity (area where device 45/46 is placed in package as shown in Figs 7 and 13),
wherein the top surface (top of 45/46) of the at least one semiconductor chip (Col 4, Lines 11-2 discloses 45/46 as an image sensor package therefore it has at least one chip) has a region (annotated Fig 13 of Tamura ‘861 discloses region above chip 45/46 is free of first and second materials (43 and 44 respectively) that is free of the first (43) and second materials (44) and is arranged in the cavity (area where device 45/46 is placed in package as shown in Figs 7 and 13)(Fig 13 discloses that cavity is filled with 45/46 and therefore free of first and second materials), and
wherein the top surface (top of 45/46) of the at least one semiconductor chip (45/46) has a region that is free of any material. (Fig 13 discloses that the top surface of 45/46 is free from any material).
With respect to Claim 37 Tamura ‘861 discloses a method for manufacturing the semiconductor device (Fig 10) according to claim 20, and Tamura ‘861 further discloses the method comprising:
mounting (disclosed in Fig 13) a semiconductor chip element (45/46, Fig 13, Col 11, Lines 9-10 and Col 11, Lines 10-11 and 25) having at least one semiconductor chip (Para [0004] discloses sensor 28 as an image sensor package, therefore it has at least on chip) on a carrier (47, Fig 13 of Tamura ‘861, Col 11, Lines 12-13) and electrically contacting (Figs 2 and 13 and Col 4, Lines 47-51 disclose wire bonds 9 connecting chip pad 8 to carrier pads (designated as 6 in Fig 2, 47 in Fig 13) a main surface (top of 44 as shown in annotated Fig 13 of Tamura ‘861) of the carrier (47) and a top surface (top of 45/46 as shown in annotated Fig 13 of Tamura ‘861) of the at least one semiconductor chip (45/46) with at least one wire connection (9, Fig 3, Col 4, Lines 47-51);
completely enclosing (Fig 13 discloses 43 encloses wire connectors) the at least one wire connection (9) with a first material (material of 43, Fig 13, Col 11, Lines 3-4 disclose 43 as silicone) comprising a first plastic material (Col 11, Lines 3-4 disclose 43 as silicone) by vacuum injection molding, by a film-assisted molding process, by a casting process (Col 11, Lines 32-34 disclose resin is filled via potting which a person of ordinary skill in the art will recognize as a casting process), by a spraying process, and/or by a sacrificial layer process; and
applying Col 11, Lines 32-34 disclose resin is filled via potting process) a second material (44, Fig 13, Col 10, Lines 67-68) to the carrier (47), forming a frame (Fig 7 discloses recessed area where 43 and 44 are disposed surrounding (“a frame”) around device 45) and surrounding a cavity (area where device 45/46 is placed in package as shown in Figs 7 and 13),
wherein the top surface (top of 45/46) of the semiconductor chip (45/46) has an region (annotated Fig 13 of Tamura ‘861 discloses region above chip 45/46 is free of first and second materials (43 and 44 respectively) that remains free of the first (43) and second plastic materials (44) and is arranged in the cavity (area where device 45/46 is placed in package as shown in Figs 7 and 13) (Fig 13 discloses that the top surface of 45/46 is free from any material).
With respect to Claim 38 Tamura ‘861 discloses all limitations of the method according to claim 37, and Tamura ‘861 further discloses wherein the first (43) and second materials (44) are applied using the same molding tool (Col 11, Lines 32-34 disclose resin is filled via potting process, therefore the same tool can be used for both materials).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 33-34 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe ‘578 in view of de Guzman et al. (US 7,576,401 B1, hereinafter de Guzman ‘401), in view of the following arguments.
With respect to Claim 21 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 20, and Watanabe ‘578 further discloses wherein the semiconductor chip element (28) comprises, as the at least one semiconductor chip (Para [0004] discloses sensor 28 as an image sensor package, therefore has at least on chip).
But Watanabe ‘578 fails to explicitly disclose an electronic semiconductor chip having the top surface on which an optoelectronic semiconductor chip is mounted, the optoelectronic semiconductor chip being spaced apart from the first and second materials in the cavity.
Nevertheless, in a related endeavor (Fig 10 of de Guzman ‘401), de Guzman ‘401 teaches an electronic semiconductor chip (1002, Fig 10 of de Guzman ‘401, Col 7, Line 36) having the top surface (top of 1002) on which an optoelectronic semiconductor chip (114, Fig 10 of de Guzman ‘401, Col 7, Line 43-44) is mounted (disclosed in Fig 10 of de Guzman ‘401 and Col 7, Lines 43-44), the optoelectronic semiconductor chip (114) being spaced apart from the first (130, Fig 10 of de Guzman ‘401, Col 4, Line 6) and second materials (126, Fig 10 of de Guzman ‘401, Col 8, Line 21) in the cavity (128, Fig 10 of de Guzman ‘401, Col 4, Lines 2-3).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate de Guzman ‘401’s teaching of an electronic semiconductor chip having the top surface on which an optoelectronic semiconductor chip is mounted, the optoelectronic semiconductor chip being spaced apart from the first and second materials in the cavity into Watanabe ‘578’s device. Watanabe ‘578 teaches an image sensor with a optoelectronic chip but is silent on the details of the chip. de Guzman ‘401 also teaches an image sensor and provides details on the optoelectronic chip. The ordinary artisan would have been motivated to modify Watanabe ‘578, therefore, in the manner set forth above, at least, because as de Guzman ‘401 teaches in Col 8, Lines 23-32, the stacked chip arrangement reduces the size of the substrate allowing for a smaller device footprint which enables further miniaturization of the end device.
As incorporated, the structure of an optoelectronic chip (114) mounted on a semiconductor chip (1002) as taught by de Guzman ‘401 would be used as the chip structure of (28) of Watanabe ‘578 so that the chip is spaced away from first and second materials in the device of Watanabe ‘578.
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With respect to Claim 33 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 20, but Watanabe ‘578 fails to explicitly disclose wherein the first material is arranged in the cavity.
Nevertheless, in a related endeavor (Fig 10 of de Guzman ‘401), de Guzman ‘401 teaches wherein the first material (130/1010, Fig 10 of de Guzman ‘401, Col 4, Line 6 and Col 7, Lines 44-45) is arranged in the cavity (128, Fig 10 of de Guzman ‘401, Col 4, Lines 2-3)(annotated Fig 10 of de Guzman ‘401 discloses portions of first material layer 1010 in the area framed by second material 126 defining the cavity)
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate de Guzman ‘401’s teaching of wherein the first material is arranged in the cavity into Watanabe ‘578’s device. Watanabe ‘578 teaches an image sensor with a optoelectronic chip but is silent on the details of the chip. de Guzman ‘401 also teaches an image sensor and provides details on the optoelectronic chip and how to configure that chip stack in the device. The ordinary artisan would have been motivated to modify Watanabe ‘578, therefore, in the manner set forth above, at least, because as de Guzman ‘401 teaches in Col 8, Lines 23-32, the stacked chip arrangement, which incorporates the first material being partially arranged in the cavity, reduces the size of the substrate allowing for a smaller device footprint which enables further miniaturization of the end device.
As incorporated, the structure as taught by de Guzman ‘401 wherein the first material (130/1010) of de Guzman ‘401 is partially arranged in the cavity would be used so that the first material (130) of Watanabe ‘578 is partially arranged in the cavity.
With respect to Claim 34 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 20, but Watanabe ‘578 fails to explicitly disclose wherein the second material covers the first material.
Nevertheless, in a related endeavor (Fig 10 of de Guzman ‘401), de Guzman ‘401 teaches wherein the second material (126, Fig 10 of de Guzman ‘401, Col 8, Line 21) covers the first material (130/1010, Fig 10 of de Guzman ‘401, Col 4, Line 6 and Col 7, Lines 44-45) (annotated Fig 10 of de Guzman ‘401 discloses second material layer 126 over areas of first material 130/1010).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate de Guzman ‘401’s teaching of wherein the second material covers the first material into Watanabe ‘578’s device. Watanabe ‘578 teaches an image sensor with a optoelectronic chip but is silent on the details of the chip. de Guzman ‘401 also teaches an image sensor and provides details on the optoelectronic chip and how to configure that chip stack in the device. The ordinary artisan would have been motivated to modify Watanabe ‘578, therefore, in the manner set forth above, at least, because as de Guzman ‘401 teaches in Col 8, Lines 23-32, the stacked chip arrangement, which incorporates the second material over the first material, reduces the size of the substrate allowing for a smaller device footprint which enables further miniaturization of the end device.
As incorporated, the structure as taught by de Guzman ‘401 wherein the second material (126) of de Guzman ‘401 is over the first material (130/1010) of de Guzman ‘401 would be used so that second material (100) is over first material (25) of Watanabe ‘578.
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With respect to Claim 39 Watanabe ‘578 discloses a semiconductor device (Fig 10) comprising:
a planar carrier (24, Fig 10, Para [0082]) having a main surface (top of 24 as shown in annotated Fig 10 of Watanabe ‘578) on which a semiconductor chip element (28, Fig 10, Para [0082]) is mounted (disclosed in Fig 10), the semiconductor chip (28) comprising at least one semiconductor chip (Para [0004] discloses sensor 28 as an image sensor package, therefore will have at least one chip);
at least one wire connection (27, Fig 10, Para [0082]) between the main surface (top of 24) of the carrier (24) and a top surface (top of 28 as shown in annotated Fig 10 of Watanabe ‘578) of the at least one semiconductor chip (28);
a first material (25, Fig 10, Para [0082]) completely enclosing (Fig 10 and Para [0088] disclose 25 enclosing wire connection) the wire connection (27) and comprising a first plastic material (Para [0089] discloses 25 as silicon group resin); and
a second material (100, Fig 10, Para [0090]) forming a frame (Para [0134] discloses 100 provided on circumferential side surface of structure 210) and surrounding a cavity (cavity (denoted by dimension “a”) over chip 28 and structure 29 as annotated Fig 10 of Watanabe ‘578 and Para [0084], hereinafter cavity),
wherein the top surface (top of 28) of the at least one semiconductor chip (28) has a region (annotated Fig 10 of Watanabe ‘578 discloses region above chip 28 within the inner sides of 100 is free of first and second materials (25 and 100 respectively)) that is free of the first (25) and second materials (100) and is arranged in (disclosed in Fig 10) the cavity (cavity), and
wherein the top surface (top of 28) of the at least one semiconductor chip (28) has a region that is free of any material (annotated Fig 10 of Watanabe ‘578 discloses regions of top of semiconductor chip 28 being free of any material).
wherein the semiconductor chip element (28) comprises, as the at least one semiconductor chip (Para [0004] discloses sensor 28 as an image sensor package, therefore has at least on chip), an electronic semiconductor chip having the top surface on
But Watanabe ‘578 fails to explicitly disclose an electronic semiconductor chip having the top surface on which an optoelectronic semiconductor chip is mounted, the optoelectronic semiconductor chip being spaced apart from the first and second materials in the cavity.
Nevertheless, in a related endeavor (Fig 10 of de Guzman ‘401), de Guzman ‘401 teaches an electronic semiconductor chip (1002, Fig 10 of de Guzman ‘401, Col 7, Line 36) having the top surface (top of 1002) on which an optoelectronic semiconductor chip (114, Fig 10 of de Guzman ‘401, Col 7, Line 43-44) is mounted (disclosed in Fig 10 of de Guzman ‘401 and Col 7, Lines 43-44), the optoelectronic semiconductor chip (114) being spaced apart from the first (130/1010, Fig 10 of de Guzman ‘401, Col 4, Line 6 and Col 7, Lines 44-45) and second materials (126, Fig 10 of de Guzman ‘401, Col 8, Line 21) in the cavity (128, Fig 10 of de Guzman ‘401, Col 4, Lines 2-3).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate de Guzman ‘401’s teaching of an electronic semiconductor chip having the top surface on which an optoelectronic semiconductor chip is mounted, the optoelectronic semiconductor chip being spaced apart from the first and second materials in the cavity into Watanabe ‘578’s device. Watanabe ‘578 teaches an image sensor with a optoelectronic chip but is silent on the details of the chip. de Guzman ‘401 also teaches an image sensor and provides details on the optoelectronic chip. The ordinary artisan would have been motivated to modify Watanabe ‘578, therefore, in the manner set forth above, at least, because as de Guzman ‘401 teaches in Col 8, Lines 23-32, the stacked chip arrangement reduces the size of the substrate allowing for a smaller device footprint which enables further miniaturization of the end device.
As incorporated, the structure of an optoelectronic chip (114) mounted on a semiconductor chip (1002) as taught by de Guzman ‘401 would be used as the chip structure of (28) of Watanabe ‘578 so that the chip is spaced away from first and second materials in the device of Watanabe ‘578.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe ‘578 in view of Tamura ‘861, in view of the following arguments.
With respect to Claim 24 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 20, and Watanabe ‘578 further discloses wherein the first material (25) the second material (100),
But Watanabe ‘578 fails to explicitly disclose wherein the first material comprises a second plastic material different from the first plastic material and from the second material, which is arranged on the first plastic material and which, together with the first plastic material, completely encloses the at least one wire connection.
Nevertheless, in a related endeavor (Fig 1-3, 7 and 13 of Tamura ‘861), Tamura ‘861 teaches wherein the first material (43/44, Fig 13 of Tamura ‘861, Col 10, Lines 65 and Col 10, Lines 67-68) comprises a second plastic material (44, Fig 13 of Tamura ‘861, Col 10, Lines 67-68) different from the first plastic material (43, Fig 13 of Tamura ‘861, Col 10, Lines 65)(Col 11, Lines 1-2 of Tamura ‘861 disclose 44 as epoxy resin and Col 11, Lines 3-4 of Tamura ‘861 disclose 43 as silicon resin), which is arranged on (disclosed in Fig 13 of Tamura ‘861) the first plastic material (43) and which, together with the first plastic (43) material, completely encloses the at least one wire connection (9, Fig 3 of Tamura ‘861, Col 4, lines 51)(Fig 13 of Tamura ‘861 disclose 43/44 completely encloses wire connector 9).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Tamura ‘861’s teaching of wherein the first material comprises a second plastic material different from the first plastic material and from the second material, which is arranged on the first plastic material and which, together with the first plastic material, completely encloses the at least one wire connection into Watanabe ‘578’s device. Watanabe ‘578 teaches an image sensor with a material covering the wire connection and is open to the composition of that materials, stating it could be silicon or epoxy. Tamura ‘861 teaches an image sensor and provides details for using an encapsulant made of different layers of silicon and epoxy. The ordinary artisan would have been motivated to modify Watanabe ‘578, therefore, in the manner set forth above, at least, because as Tamura ‘861 teaches in Col 5, Lines 39-50, using the two layer encapsulant arrangement provides moisture resistance to the device, thereby increasing reliability.
As incorporated, the teaching of Tamura ‘861 wherein the first material (43/44) comprises a second plastic material (44) different from the first plastic material (43) would be used as the first material (25) of Watanabe ‘578 so that the first and second plastic materials completely encloses the at least one wire connection (27) of Watanabe ‘578.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe ‘578 in view of Suda (US 2002/0163054 A1, hereinafter Suda ‘054), in view of the following arguments.
With respect to Claim 28 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 26, but Watanabe ‘578 fails to explicitly discloses wherein the semiconductor material comprises silicon.
Nevertheless, in a related endeavor (Fig 1A-1D of Suda ‘054), Suda ‘054 teaches wherein the semiconductor material (522, Fig 1D of Suda ‘054, Para [0055]) comprises silicon (Para [0055] of Suda ‘054 teaches a spacer material 522 is formed of silicon).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Suda ‘054’s teaching of wherein the semiconductor material comprises silicon into Watanabe ‘578’s device. Watanabe ‘578 teaches a image sensor device with a spacer 100 and is open to the material of that spacer. Suda ‘054 also teaches a sensor with a spacer and teaches that silicon can be used as that spacer. The ordinary artisan would have been motivated to modify Watanabe ‘578 in the manner set forth above, at least, because silicon is a readily available material in a semiconductor process, therefore using it as the spacer material can simplify the manufacturing process by requiring less unique materials.
As incorporated, silicon spacer taught by Suda ‘054 would be used as the second material (100) of Watanabe ‘578.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe ‘578 in view of Murano et al. (US 5,617,131, hereinafter Murano ‘131), in view of the following arguments.
With respect to Claim 29 Watanabe ‘578 discloses all limitations of the semiconductor device according to claim 26, but Watanabe ‘578 fails to explicitly disclose wherein the metal material comprises steel.
Nevertheless, in a related endeavor (Fig 1-4 of Murano ‘131), Murano ‘131 teaches wherein the metal material (9, Fig 3 of Murano ‘131, Col 6, Lines 19-24) comprises steel (Col 6, Lines 19-24 of Murano ‘131 teaches a spacer material 9 is formed of stainless steel).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Murano ‘131’s teaching of wherein the semiconductor material comprises silicon into Watanabe ‘578’s device. Watanabe ‘578 teaches a image sensor device with a spacer 100 and is open to the material of that spacer. Murano ‘131 also teaches a sensor with a spacer and teaches that stainless steel can be used as that spacer. The ordinary artisan would have been motivated to modify Watanabe ‘578 in the manner set forth above, at least, because stainless steel is a readily available and well-known material in a semiconductor process, therefore using it as the spacer material can simplify the manufacturing process by requiring less unique materials.
As incorporated, stainless steel spacer taught by Murano ‘131 would be used as the second material (100) of Watanabe ‘578.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sagar, Keerthi & Sreekumar, M.. (2013). Miniaturized Flexible Flow Pump using SMA Actuator. Procedia Engineering. 64. 896-906. 10.1016/j.proeng.2013.09.166, discloses a silicone rubber (Table 2) having a Young’s Modulus. Further, “In Light-Emitting Diodes: Research, Manufacturing, and Applications IV, H. Walter Yao, Ian T. Ferguson, E. Fred Schubert, Editors, Proceedings of SPIE Vol. 3938 (2000) • 0277-786X/00/$15.OO discloses epoxy having a Shore D hardness value (Table 4) and “William Moebs, Samuel J. Ling, Jeff Sanny, University Physics Volume 1, Chapter/section 12.3, OpenStax, https://openstax.org/books/university-physics-volume-1/pages/12-3-stress-strain-and-elastic-modulus, Houston, TX, Sep 19, 2016”, discloses a definition for elastic modulus.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898