DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application. Acknowledgement is made of the amendment received 11/20/2023. Claims 8, 10, 11, 15, and 16 are amended, and claims 19 and 20 are added for consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, it recites the limitation "the crystal plane [111] of the second silicon wafer" in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claims to have intended to state “the crystal orientation [111] of the second silicon wafer”, in which case proper antecedent basis is established. The claims will be examined on the basis of this interpretation hereafter. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1, 5, 7, 11, 12, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sumita (JP 2012068586 A, English translation of description provided, hereafter Sumita).
Regarding claim 1, Sumita discloses: A silicon-based mask (Sumita 9, 27, 90, fig 2, ¶0018, 0020), comprising a first silicon wafer (Sumita 21, ¶0029) and a second silicon wafer (Sumita 22, ¶0029) laminated one on another (Sumita fig 2, ¶0028, under a broadest reasonable interpretation (BRI) of “laminated”), wherein the first silicon wafer comprises a first via hole (Sumita 24, fig 2, ¶0034), the second silicon wafer comprises a second via hole (Sumita 26, fig 2, ¶0037), an orthogonal projection of a wall of the first via hole onto the second silicon wafer surrounds the second via hole (Sumita fig 2), and under a same etching condition, an etching rate of the second silicon wafer is smaller than an etching rate of the first silicon wafer (Sumita ¶0046, 22 is an etch stopper, therefore would at least be exposed to same conditions during the etching of 21).
Regarding claim 5, Sumita discloses: The silicon-based mask according to claim 1, wherein a thickness of the first silicon wafer (Sumita 21) is greater than a thickness of the second silicon wafer (Sumita 22)(Sumita fig 2, ¶0041, 0043, thickness of 22 is reduced from 725 to 20 µm).
Regarding claim 7, Sumita discloses: The silicon-based mask according to claim 1, wherein a doping type of the first silicon wafer (Sumita 21) comprises a P-type or an N-type (Sumita ¶0029, boron, phosphorus are P-type and N-type doping, respectively), and a doping type of the second silicon wafer (Sumita 22) comprises a P- type or an N-type (Sumita ¶0029).
Regarding claim 8, Sumita discloses: The silicon-based mask according to claim 1, further comprising a first protection layer (Sumita, bottom layer of 23 with respect to fig 2, ¶0033, 0044, under a BRI of “protection layer”) and a second protection layer (Sumita, top layer of 23 with respect to fig 2, ¶0033, 0044, under a BRI of “protection layer”), wherein the first protection layer is located on a side of the first silicon wafer (Sumita 21) away from the second silicon wafer (Sumita 22)(Sumita fig 2, bottom of 23 is on 21 away from 22), and the second protection layer is located on a side of the second silicon wafer away from the first silicon wafer (Sumita fig 2, top of 23 is on 22 away from 21).
Regarding claim 11, Sumita discloses: A method for manufacturing the silicon-based mask according to claim 1, comprising:
providing a first silicon wafer (Sumita 21);
forming a second silicon wafer (Sumita 22) on the first silicon wafer (Sumita fig 2, ¶0028, formed on at least via bonding), under a same etching condition, an etching rate of the second silicon wafer being smaller than an etching rate of the first silicon wafer (Sumita ¶0046, 22 is an etch stopper, therefore would at least be exposed to same conditions during the etching of 21); and
forming a first via hole in the first silicon wafer through wet etching (Sumita 24, fig 2, ¶0034, 0046), and forming a second via hole in the second silicon wafer through dry etching (Sumita 26, fig 2, ¶0037), an orthogonal projection of a wall of the first via hole onto the second silicon wafer surrounding the second via hole (Sumita fig 2).
Regarding claim 12, Sumita disclose: The method according to claim 11, wherein the forming the first via hole (Sumita 24) in the first silicon wafer (Sumita 21) through wet etching (Sumita fig 2, ¶0034, 0046) and forming the second via hole (Sumita 26) in the second silicon wafer (Sumita 22) through dry etching (Sumita fig 2, ¶0037) specifically comprises:
forming a first protection layer (Sumita 23, ¶0033, 0044, under a BRI of “protection layer”) on a side of the first silicon wafer away from the second silicon wafer (Sumita fig 2, formed at least in part on bottom of 21, away from 22), and forming a second protection layer (Sumita 25, ¶0036, under a BRI of “protection layer”) on a side of the second silicon wafer away from the first silicon wafer (Sumita fig 2, formed on top of 22, away from 21);
patterning the first protection layer (Sumita ¶0044, fig 2); forming the first via hole in the first silicon wafer through wet etching with the patterned first protection layer as a mask (Sumita fig 2, ¶0045); and
forming the second via hole in the second protection layer and the second silicon wafer through dry etching (Sumita ¶0049).
Regarding claim 15, Sumita discloses: The method according to claim 12, wherein the forming the first via hole (Sumita 24) in the first silicon wafer (Sumita 21) through wet etching (Sumita fig 2, ¶0034, 0046) specifically comprises etching the first silicon wafer to form the first via hole through a potassium hydroxide etching solution (Sumita ¶0046, “potassium hydroxide aqueous solution”) or a tetramethylammonium hydroxide etching solution.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sumita (JP 2012068586 A, English translation of description provided, hereafter Sumita), as applied to claim 1 above, and further in view of Atobe et al (US 20050064622 A1, hereafter Atobe).
Regarding claim 4, Sumita teaches: The silicon-based mask according to claim 1.
Sumita does not explicitly teach: wherein a slope angle of the first via hole is smaller than a slope angle of the second via hole.
Atobe, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a slope angle of a first via hole (Atobe 11, 111, 511, ¶0055, 0091) is smaller than a slope angle of a second via hole (Atobe 12, 112, 532, ¶0169-0170)(Atobe fig 5, ¶0055, 0085, 0098, 511 with taper of 54.74° with respect to the horizontal, 532, square shape, therefore ≈90° with respect to the horizontal).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first and second via holes of Sumita, such that “a slope angle of the first via hole is smaller than a slope angle of the second via hole”, as taught by Atobe, in order to form high precision apertures (Atobe ¶0098) and/or to prevent a deposited pattern from becoming thin at its edges by providing a wider access through the first via hole (Atobe ¶0060, 0135).
Regarding claim 10, Sumita teaches: The silicon-based mask according to claim 1.
Sumita does not explicitly teach: A display panel comprising an organic light-emitting material layer manufactured using the silicon-based mask according to claim 1.
Atobe, in the same field of endeavor of semiconductor device manufacturing, teaches: A display panel (Atobe 100, fig 8, 9) comprising an organic light-emitting material layer (Atobe 61-63, ¶0011, 0124, 0130) manufactured using the silicon-based mask (Atobe 9, 90, ¶0124, 0128).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the mask of Sumita to be used in the manufacture of a display panel comprising an organic light-emitting material layer, as taught by Atobe, in order to obtain an organic light-emitting display with high precision pixels (Atobe ¶0010).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sumita (JP 2012068586 A, English translation of description provided, hereafter Sumita), as applied to claim 1 above, and further in view of Amamiya (JP 3118390 B2, hereafter Amamiya).
Regarding claim 6, Sumita teaches: The silicon-based mask according to claim 5, wherein the second silicon wafer has a crystal orientation [111] (Sumita ¶0029)
Sumita does not explicitly teach: wherein a crystal orientation [110] of the first silicon wafer is coaxial with a crystal orientation [111] of the second silicon wafer, or the crystal orientation [110] of the first silicon wafer is perpendicular to the crystal plane [111] of the second silicon wafer.
Sumita further teaches: a crystal orientation of the first silicon wafer (Sumita 21) and the second silicon wafer (Sumita 22) are selected such that an etching rate of the second silicon wafer is less than an etching rate of the first silicon wafer (Sumita ¶0029, 0046).
Amamiya, in the same field of endeavor of semiconductor device manufacturing, in at least one embodiment, teaches: a crystal orientation [110] of a first silicon wafer (Amamiya 1, ¶0012, “lower silicon substrate … (110)”) is coaxial with a crystal orientation [111] of the second silicon wafer (Amamiya 2, ¶0012, “upper silicon substrate … (111)”)(Amamiya ¶0017), or the crystal orientation [110] of the first silicon wafer is perpendicular to the crystal plane (as best understood to mean “the crystal orientation”) [111] of the second silicon wafer (Amamiya ¶0017).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sumita such that “a crystal orientation [110] of the first silicon wafer is coaxial with a crystal orientation [111] of the second silicon wafer, or the crystal orientation [110] of the first silicon wafer is perpendicular to the crystal plane [111] of the second silicon wafer”, as taught by Amamiya, in order to achieve etch selectivity between the first and second silicon wafers under the same etching conditions (Amamiya ¶0062).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to choose any number of suitable crystal orientations for the first silicon wafer or the second silicon wafer, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice (MPEP 2144.07).
Claims 2 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sumita (JP 2012068586 A, English translation of description provided, hereafter Sumita), as applied to claim 1 above, and further in view of Kim (KR 100267965 B1, English translation of description provided, hereafter Kim).
Regarding claim 2, Sumita: The silicon-based mask according to claim 1.
Sumita does not explicitly teach: wherein under the same etching condition, a ratio of the etching rate of the first silicon wafer to the etching rate of the second silicon wafer is greater than or equal to 80.
Kim, in the same field of endeavor of semiconductor device manufacturing, teaches: a ratio etching rates of silicon wafers with different crystal orientations is greater than 100 (Kim “etching rate along the (100) plane is 100 times faster than that of the (111) plane”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sumita such that “under the same etching condition, a ratio of the etching rate of the first silicon wafer to the etching rate of the second silicon wafer is greater than or equal to 80”, as taught by Kim, in order to ensure the second silicon wafer functions as an effective etch stopper.
Regarding claim 19, Sumita in view of Kim teaches: The silicon-based mask according to claim 2, further comprising a first protection layer (Sumita, bottom layer of 23 with respect to fig 2, ¶0033, 0044, under a BRI of “protection layer”) and a second protection layer (Sumita, top layer of 23 with respect to fig 2, ¶0033, 0044, under a BRI of “protection layer”), wherein the first protection layer is located on a side of the first silicon wafer (Sumita 21) away from the second silicon wafer (Sumita 22)(Sumita fig 2, bottom of 23 is on 21 away from 22), and the second protection layer is located on a side of the second silicon wafer away from the first silicon wafer (Sumita fig 2, top of 23 is on 22 away from 21).
Claims 3 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sumita (JP 2012068586 A, English translation of description provided, hereafter Sumita), as applied to claim 1 above, and further in view of Zhang et al (CN 111334750 A, English translation of description provided, hereafter Zhang).
Regarding claim 3, Sumita teaches: The silicon-based mask according to claim 1.
Sumita does not explicitly teach: wherein a pore size d of the second via hole satisfies 2 µm < d < 20 µm.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches: a pore size d of a second via hole satisfies 2 µm < d < 20 µm (Zhang ¶0053).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the second via hole of Sumita such that it has a size d that satisfies 2 µm < d < 20 µm, as taught by Zhang, in order to enable accurate deposition of organic light emitting material through the second via hole, thereby achieving high-resolution pixel formation and/or improving a device PPI (Zhang ¶0050-0051).
Regarding claim 20, Sumita in view of Zhang teaches: The silicon-based mask according to claim 3, further comprising a first protection layer (Sumita, bottom layer of 23 with respect to fig 2, ¶0033, 0044, under a BRI of “protection layer”) and a second protection layer (Sumita, top layer of 23 with respect to fig 2, ¶0033, 0044, under a BRI of “protection layer”), wherein the first protection layer is located on a side of the first silicon wafer (Sumita 21) away from the second silicon wafer (Sumita 22)(Sumita fig 2, bottom of 23 is on 21 away from 22), and the second protection layer is located on a side of the second silicon wafer away from the first silicon wafer (Sumita fig 2, top of 23 is on 22 away from 21).
SECOND INTERPRETATION
Claim Rejections - 35 USC § 102
Claim 1, 5-8, 11, 12, 16, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Amamiya (JP 3118390 B2, English translation of description provided, hereafter Amamiya).
Regarding claim 1, Amamiya discloses: A silicon-based mask (Amamiya 1, 2, 13, fig 2, ¶0060), comprising a first silicon wafer (Amamiya 1, ¶0012, 0060) and a second silicon wafer (Amamiya 2, ¶0012, 0060) laminated one on another (Amamiya fig 2, ¶0060, under a BRI of “laminated”), wherein the first silicon wafer comprises a first via hole (Amamiya 11, 12, fig 2(c), ¶0061, hole formed by etch in 2(c)), the second silicon wafer comprises a second via hole (Amamiya 13, fig 2(e), ¶0063), an orthogonal projection of a wall of the first via hole onto the second silicon wafer surrounds the second via hole (Amamiya fig 2), and under a same etching condition, an etching rate of the second silicon wafer is smaller than an etching rate of the first silicon wafer (Amamiya ¶0062).
Regarding claim 5, Amamiya discloses: The silicon-based mask according to claim 1, wherein a thickness of the first silicon wafer (Amamiya 1) is greater than a thickness of the second silicon wafer (Amamiya 2)(Amamiya fig 2, ¶0060, 400 µm and 100 µm respectively).
Regarding claim 6, Amamiya discloses, in at least one embodiment: a crystal orientation [110] of the first silicon wafer (Amamiya 1, ¶0012, “lower silicon substrate … (110)”) is coaxial with a crystal orientation [111] of the second silicon wafer (Amamiya 2, ¶0012, “upper silicon substrate … (111)”)(Amamiya ¶0017), or the crystal orientation [110] of the first silicon wafer is perpendicular to the crystal plane (as best understood to mean “the crystal orientation”) [111] of the second silicon wafer (Amamiya ¶0017).
Regarding claim 7, Amamiya discloses: The silicon-based mask according to claim 1, wherein a doping type of the first silicon wafer (Amamiya 1) comprises a P-type or an N-type (Amamiya ¶0060, phosphorus doped, P-type), and a doping type of the second silicon wafer (Amamiya 2) comprises a P- type or an N-type (Amamiya ¶0060, phosphorus doped, P-type).
Regarding claim 8, Amamiya discloses: The silicon-based mask according to claim 1, further comprising a first protection layer (Amamiya, bottom layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”) and a second protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”), wherein the first protection layer is located on a side of the first silicon wafer (Amamiya 1) away from the second silicon wafer (Amamiya 2)(Amamiya fig 2, bottom of 4 is on 1 away from 2), and the second protection layer is located on a side of the second silicon wafer away from the first silicon wafer (Amamiya fig 2, top of 4 is on 2 away from 1).
Regarding claim 11, Amamiya discloses: A method for manufacturing the silicon-based mask according to claim 1, comprising:
providing a first silicon wafer (Amamiya 1);
forming a second silicon wafer (Amamiya 2) on the first silicon wafer (Amamiya fig 2, ¶0060, formed on at least via bonding), under a same etching condition, an etching rate of the second silicon wafer being smaller than an etching rate of the first silicon wafer (Amamiya ¶0062); and
forming a first via hole in the first silicon wafer through wet etching (Amamiya 11, 12, fig 2(c), ¶0061, hole formed by etch in 2(c)), and forming a second via hole in the second silicon wafer through dry etching (Amamiya 13, fig 2(e), ¶0063), an orthogonal projection of a wall of the first via hole onto the second silicon wafer surrounding the second via hole (Amamiya fig 2).
Regarding claim 12, Amamiya discloses: The method according to claim 11, wherein the forming the first via hole (Amamiya 11, 12, fig 2(c), ¶0061, hole formed by etch in 2(c)) in the first silicon wafer (Amamiya 1) through wet etching (Amamiya ¶0061) and forming the second via hole (Amamiya 13) in the second silicon wafer (Amamiya 2) through dry etching (Amamiya ¶0063) specifically comprises:
forming a first protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”) on a side of the first silicon wafer away from the second silicon wafer (Amamiya fig 2, formed at least in part on bottom of 1, away from 2), and forming a second protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”) on a side of the second silicon wafer away from the first silicon wafer (Amamiya fig 2, formed on top of 2, away from 1);
patterning the first protection layer (Amamiya ¶0067, fig 2(b)); forming the first via hole in the first silicon wafer through wet etching with the patterned first protection layer as a mask (Amamiya fig 2(c), ¶0068); and
forming the second via hole in the second protection layer and the second silicon wafer through dry etching (Amamiya ¶0071, fig 2(e)).
Regarding claim 16, Amamiya discloses: The method according to claim 12, further comprising, subsequent to forming the first via hole (Amamiya 11, 12, fig 2(c), ¶0061, hole formed by etch in 2(c)) and the second via hole (Amamiya 13), removing the first protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067) and the second protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067)(Amamiya fig 2(f), ¶0072).
Regarding claim 17, Amamiya discloses: The method according to claim 16, wherein the forming the first protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067) and the second protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067) specifically comprises forming the first protection layer and the second protection layer using an inorganic material (Amamiya 4, ¶0039, 0067), and the removing the first protection layer and the second protection layer specifically comprises removing the first protection layer and the second protection layer through wet etching using an etching solution (Amamiya ¶0044, 0072).
Claim Rejections - 35 USC § 103
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Amamiya (JP 3118390 B2, English translation of description provided, hereafter Amamiya), as applied to claim 8 above, and further in view of Liu et al (US 20190326514 A1, hereafter Liu).
Regarding claim 9, Amamiya teaches: The silicon-based mask according to claim 8.
Amamiya does not teach: wherein each of the first protection layer and the second protection layer comprises a magnetic material layer.
Liu, in the same field of endeavor of semiconductor device manufacturing, teaches: a first protection layer (Liu 103, ¶0052, under a BRI of “protection layer”) and a second protection layer (Liu 106, ¶0054, under a BRI of “protection layer”) comprises a magnetic material layer (Liu ¶0061, 0063, “Ni”, applicant discloses suitable materials for a magnetic material layer include “Ni”, spec ¶0067).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first and second protection layers of Amamiya to comprise a magnetic material, as taught by Liu, in order to prevent deformation, and/or breakage, and/or corrosion during cleaning (Liu ¶0035, 0064).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Amamiya (JP 3118390 B2, English translation of description provided, hereafter Amamiya), as applied to claim 11 above, and further in view of Sasaki et al (JP 3118390 B2, English translation of description provided, hereafter Sasaki).
Regarding claim 13, Amamiya teaches: The method according to claim 11, wherein the forming the first via hole (Amamiya 11, 12, fig 2(c), ¶0061, hole formed by etch in 2(c)) in the first silicon wafer (Amamiya 1) through wet etching (Amamiya ¶0061) and forming the second via hole (Amamiya 13) in the second silicon wafer (Amamiya 2) through dry etching (Amamiya ¶0063) specifically comprises:
forming the second via hole in the second silicon wafer through dry etching (Amamiya ¶0071, fig 2(e)).
forming a first protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”) on a side of the first silicon wafer away from the second silicon wafer (Amamiya fig 2, formed at least in part on bottom of 1, away from 2), and forming a second protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”) on a side of the second silicon wafer away from the first silicon wafer (Amamiya fig 2, formed on top of 2, away from 1); patterning the first protection layer (Amamiya ¶0067, fig 2(b)); and
forming the first via hole in the first silicon wafer through wet etching with the patterned first protection layer as a mask (Amamiya fig 2(c), ¶0068)
Amamiya does not teach: the second protection layer covering a wall of the second via hole.
Sasaki teaches: forming a second via hole (Sasaki 6, 7) in a second silicon wafer (Sasaki 1) through dry etching (Sasaki fig 1, ¶0012), forming a second protection layer (Sasaki top of 8) covering a wall of the second via hole (Sasaki fig 1, ¶0012, 0025).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Amamiya, such that the second via hole is formed before the second protective layer, and to conformally deposit the second protective layer such that “the second protection layer covering a wall of the second via hole”, as taught by Sasaki, in order to protect the second via holes from damage during subsequent wet etching steps and/or to prevent blockages or foreign matter adhesion (Sasaki ¶0006, 0010).
Regarding claim 14, Amamiya in view of Sasaki teaches: The method according to claim 13, wherein the forming the second via hole (Amamiya 13, similar to Sasaki 7) in the second silicon wafer (Amamiya 2, similar to Sasaki 1) through dry etching (Amamiya ¶0063, as modified by Sasaki) specifically comprises:
forming a photoresist layer (Amamiya ¶0078, similar to Sasaki 5) on a side of the second silicon wafer away from the first silicon wafer (Amamiya 1, similar to Sasaki 3)(Amamiya ¶0078);
patterning the photoresist layer (Amamiya ¶0079);
forming the second via hole in the second silicon wafer through dry etching with the patterned photoresist layer as a mask (Amamiya ¶0079, fig 2(d)); and
removing the patterned photoresist layer (Amamiya ¶0080).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Amamiya (JP 3118390 B2, English translation of description provided, hereafter Amamiya), as applied to claim 11 above, and further in view of Wang et al (US 7601215 B1, hereafter Wang).
Regarding claim 18, Amamiya teaches: The method according to claim 11.
Amamiya does not teach: wherein the forming the second silicon wafer on the first silicon wafer specifically comprises epitaxially growing the second silicon wafer on the first silicon wafer.
Wang, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a second silicon wafer (Wang col 2, lines 51-57, Si film, under a BRI of “wafer”) on a first silicon wafer (Wang col 4, lines 13-14, c-Si substrate) specifically comprises epitaxially growing the second silicon wafer on the first silicon wafer (Wang col 1, lines 19-36).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Amamiya to include epitaxially growing the second silicon wafer on the first silicon wafer, as taught by Wang, in order to provide a controlled thickness and uniformity to the second silicon wafer (Wang col 1, lines 28-29, col 7, lines 31-35).
Conclusion
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818