DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-7, 9-11, and 13-18 remain pending in this application. Acknowledgement is made of the amendment received 06/23/2026. Claims 8, 12, 19, and 20 are canceled, and claims 1, 6, 9, 11, 15, and 16 are amended.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 5, 7, 11, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sumita (JP 2012068586 A, English translation of description provided in previous office action dated 03/25/2026, hereafter Sumita) in view of Magdo et al (US 4256532 A, hereafter Magdo).
Regarding claim 1, Sumita teaches: A silicon-based mask (Sumita 9, 27, 90, fig 2, ¶0018, 0020), comprising a first silicon wafer (Sumita 21, ¶0029) and a second silicon wafer (Sumita 22, ¶0029) laminated one on another (Sumita fig 2, ¶0028, under a broadest reasonable interpretation (BRI) of “laminated”), wherein the first silicon wafer comprises a first via hole (Sumita 24, fig 2, ¶0034), the second silicon wafer comprises a second via hole (Sumita 26, fig 2, ¶0037), an orthogonal projection of a wall of the first via hole onto the second silicon wafer surrounds the second via hole (Sumita fig 2), and under a same etching condition, an etching rate of the second silicon wafer is smaller than an etching rate of the first silicon wafer (Sumita ¶0046, 22 is an etch stopper, therefore would at least be exposed to same conditions during the etching of 21);
the silicon-based mask further comprising a first protection layer (Sumita, bottom layer of 23 with respect to fig 2, ¶0033, 0044, under a BRI of “protection layer”) and a second protection layer (Sumita, top layer of 23 with respect to fig 2, ¶0033, 0044, under a BRI of “protection layer”), wherein the first protection layer is located on a side of the first silicon wafer (Sumita 21) away from the second silicon wafer (Sumita 22)(Sumita fig 2, bottom of 23 is on 21 away from 22), and the second protection layer is located on a side of the second silicon wafer away from the first silicon wafer (Sumita fig 2, top of 23 is on 22 away from 21).
Sumita does not teach: the first protection layer and/or the second protection layer comprises a first film layer and a second film layer laminated one on another, the first film layer is made of SiOx and located between the second film layer and the corresponding silicon wafer, the second film layer is made of SiNx.
Sumita further teaches: the first protection layer (Sumita 23) comprises SiOx or SiNx (Sumita ¶0033, “silicon nitride films, silicon oxide films”).
Magdo, in the same field of endeavor of semiconductor device manufacturing, teaches: a first protection layer (Magdo 21’, 25’, col 4, lines 40-45, col 6, lines 28-31, “protective layers of insulating material”) and a second protection layer (Magdo 24, 25, col 4, lines 21-25, 36-40, col 6, lines 28-31) comprises a first film layer (Magdo 21’, 24, respectively) and a second film layer (Magdo 25’, 25, respectively) laminated one on another (Magdo figs 2B), the first film layer is made of SiOx (Magdo col 4, lines 11-25, “silicon dioxide”) and located between the second film layer and a corresponding silicon wafer (Magdo 20, 20’)(Magdo fig 2B, col 4, lines 11-35), the second film layer is made of SiNx (Magdo col 4, lines 36-40, “silicon nitride”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sumita such that the first and second protection layers comprised a first and second film layers of SiOx and SiNx, respectively, and such that they are “laminated one on another” and the first film layer is “located between the second film layer and the corresponding silicon wafer”, as taught by Magdo, in order to minimize stress between the substrate and mask while maintaining layer etch selectivity, and thereby avoiding dislocation in the substrate and/or to avoiding distortion of the mask during processing (Magdo col 4, lines 7-10, incorporated by reference US3904454A, col 4, lines 35-50).
Regarding claim 5, Sumita in view of Magdo teaches: The silicon-based mask according to claim 1, wherein a thickness of the first silicon wafer (Sumita 21) is greater than a thickness of the second silicon wafer (Sumita 22)(Sumita fig 2, ¶0041, 0043, thickness of 22 is reduced from 725 to 20 µm).
Regarding claim 7, Sumita in view of Magdo teaches: The silicon-based mask according to claim 1, wherein a doping type of the first silicon wafer (Sumita 21) comprises a P-type or an N-type (Sumita ¶0029, boron, phosphorus are P-type and N-type doping, respectively), and a doping type of the second silicon wafer (Sumita 22) comprises a P- type or an N-type (Sumita ¶0029).
Regarding claim 11, Sumita teaches: A method for manufacturing the silicon-based mask according to claim 1, comprising:
providing a first silicon wafer (Sumita 21);
forming a second silicon wafer (Sumita 22) on the first silicon wafer (Sumita fig 2, ¶0028, formed on at least via bonding), under a same etching condition, an etching rate of the second silicon wafer being smaller than an etching rate of the first silicon wafer (Sumita ¶0046, 22 is an etch stopper, therefore would at least be exposed to same conditions during the etching of 21); and
forming a first via hole in the first silicon wafer through wet etching (Sumita 24, fig 2, ¶0034, 0046), and forming a second via hole in the second silicon wafer through dry etching (Sumita 26, fig 2, ¶0037), an orthogonal projection of a wall of the first via hole onto the second silicon wafer surrounding the second via hole (Sumita fig 2);
wherein the forming the first via hole (Sumita 24) in the first silicon wafer (Sumita 21) through wet etching (Sumita fig 2, ¶0034, 0046) and forming the second via hole (Sumita 26) in the second silicon wafer (Sumita 22) through dry etching (Sumita fig 2, ¶0037) specifically comprises:
forming a first protection layer (Sumita 23, ¶0033, 0044, under a BRI of “protection layer”) on a side of the first silicon wafer away from the second silicon wafer (Sumita fig 2, formed at least in part on bottom of 21, away from 22), and forming a second protection layer (Sumita 25, ¶0036, under a BRI of “protection layer”) on a side of the second silicon wafer away from the first silicon wafer (Sumita fig 2, formed on top of 22, away from 21);
patterning the first protection layer (Sumita ¶0044, fig 2); forming the first via hole in the first silicon wafer through wet etching with the patterned first protection layer as a mask (Sumita fig 2, ¶0045); and
forming the second via hole in the second protection layer and the second silicon wafer through dry etching (Sumita ¶0049).
Sumita does not teach: wherein the first protection layer and/or the second protection layer comprises a first film layer and a second film layer laminated one on another, the first film layer is made of SiOx and located between the second film layer and the corresponding silicon wafer, the second film layer is made of SiNx.
Sumita further teaches: the first protection layer (Sumita 23) comprises SiOx or SiNx (Sumita ¶0033, “silicon nitride films, silicon oxide films”).
Magdo, in the same field of endeavor of semiconductor device manufacturing, teaches: a first protection layer (Magdo 21’, 25’, col 4, lines 40-45, col 6, lines 28-31, “protective layers of insulating material”) and a second protection layer (Magdo 24, 25, col 4, lines 21-25, 36-40, col 6, lines 28-31) comprises a first film layer (Magdo 21’, 24, respectively) and a second film layer (Magdo 25’, 25, respectively) laminated one on another (Magdo figs 2B), the first film layer is made of SiOx (Magdo col 4, lines 11-25, “silicon dioxide”) and located between the second film layer and a corresponding silicon wafer (Magdo 20, 20’)(Magdo fig 2B, col 4, lines 11-35), the second film layer is made of SiNx (Magdo col 4, lines 36-40, “silicon nitride”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Sumita such that the first and second protection layers comprised a first and second film layers of SiOx and SiNx, respectively, and such that they are “laminated one on another” and the first film layer is “located between the second film layer and the corresponding silicon wafer”, as taught by Magdo, in order to minimize stress between the substrate and mask while maintaining layer etch selectivity, and thereby avoiding dislocation in the substrate and/or to avoiding distortion of the mask during processing (Magdo col 4, lines 7-10, incorporated by reference US3904454A, col 4, lines 35-50).
Regarding claim 15, Sumita in view of Magdo teaches: The method according to claim 11, wherein the forming the first via hole (Sumita 24) in the first silicon wafer (Sumita 21) through wet etching (Sumita fig 2, ¶0034, 0046) specifically comprises etching the first silicon wafer to form the first via hole through a potassium hydroxide etching solution (Sumita ¶0046, “potassium hydroxide aqueous solution”) or a tetramethylammonium hydroxide etching solution.
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Sumita (JP 2012068586 A, English translation of description provided in previous office action dated 03/25/2026, hereafter Sumita) in view of Magdo et al (US 4256532 A, hereafter Magdo), as applied to claim 1 above, and further in view of Kim (KR 100267965 B1, English translation of description provided in previous office action dated 03/25/2026, hereafter Kim).
Regarding claim 2, Sumita in view of Magdo teaches: The silicon-based mask according to claim 1.
Sumita in view of Magdo does not explicitly teach: wherein under the same etching condition, a ratio of the etching rate of the first silicon wafer to the etching rate of the second silicon wafer is greater than or equal to 80.
Kim, in the same field of endeavor of semiconductor device manufacturing, teaches: a ratio etching rates of silicon wafers with different crystal orientations is greater than 100 (Kim “etching rate along the (100) plane is 100 times faster than that of the (111) plane”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sumita in view of Magdo such that “under the same etching condition, a ratio of the etching rate of the first silicon wafer to the etching rate of the second silicon wafer is greater than or equal to 80”, as taught by Kim, in order to ensure the second silicon wafer functions as an effective etch stopper.
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sumita (JP 2012068586 A, English translation of description provided in previous office action dated 03/25/2026, hereafter Sumita) in view of Magdo et al (US 4256532 A, hereafter Magdo), as applied to claim 1 above, and further in view of Zhang et al (CN 111334750 A, English translation of description provided in previous office action dated 03/25/2026, hereafter Zhang).
Regarding claim 3, Sumita in view of Magdo teaches: The silicon-based mask according to claim 1.
Sumita in view of Magdo does not explicitly teach: wherein a pore size d of the second via hole satisfies 2 µm < d < 20 µm.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches: a pore size d of a second via hole satisfies 2 µm < d < 20 µm (Zhang ¶0053).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the second via hole of Sumita in view of Magdo such that it has a size d that satisfies 2 µm < d < 20 µm, as taught by Zhang, in order to enable accurate deposition of organic light emitting material through the second via hole, thereby achieving high-resolution pixel formation and/or improving a device PPI (Zhang ¶0050-0051).
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sumita (JP 2012068586 A, English translation of description provided in previous office action dated 03/25/2026, hereafter Sumita) in view of Magdo et al (US 4256532 A, hereafter Magdo), as applied to claim 1 above, and further in view of Atobe et al (US 20050064622 A1, hereafter Atobe).
Regarding claim 4, Sumita in view of Magdo teaches: The silicon-based mask according to claim 1.
Sumita in view of Magdo does not explicitly teach: wherein a slope angle of the first via hole is smaller than a slope angle of the second via hole.
Atobe, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a slope angle of a first via hole (Atobe 11, 111, 511, ¶0055, 0091) is smaller than a slope angle of a second via hole (Atobe 12, 112, 532, ¶0169-0170)(Atobe fig 5, ¶0055, 0085, 0098, 511 with taper of 54.74° with respect to the horizontal, 532, square shape, therefore ≈90° with respect to the horizontal).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first and second via holes of Sumita in view of Magdo, such that “a slope angle of the first via hole is smaller than a slope angle of the second via hole”, as taught by Atobe, in order to form high precision apertures (Atobe ¶0098) and/or to prevent a deposited pattern from becoming thin at its edges by providing a wider access through the first via hole (Atobe ¶0060, 0135).
Regarding claim 10, Sumita in view of Magdo teaches: The silicon-based mask according to claim 1.
Sumita in view of Magdo does not explicitly teach: A display panel comprising an organic light-emitting material layer manufactured using the silicon-based mask according to claim 1.
Atobe, in the same field of endeavor of semiconductor device manufacturing, teaches: A display panel (Atobe 100, fig 8, 9) comprising an organic light-emitting material layer (Atobe 61-63, ¶0011, 0124, 0130) manufactured using the silicon-based mask (Atobe 9, 90, ¶0124, 0128).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the mask of Sumita in view of Magdo to be used in the manufacture of a display panel comprising an organic light-emitting material layer, as taught by Atobe, in order to obtain an organic light-emitting display with high precision pixels (Atobe ¶0010).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sumita (JP 2012068586 A, English translation of description provided in previous office action dated 03/25/2026, hereafter Sumita) in view of Magdo et al (US 4256532 A, hereafter Magdo), as applied to claim 5 above, and further in view of Amamiya (JP 3118390 B2, English translation of description provided in previous office action dated 03/25/2026, hereafter Amamiya).
Regarding claim 6, Sumita in view of Magdo teaches: The silicon-based mask according to claim 5, wherein the second silicon wafer has a crystal orientation [111] (Sumita ¶0029)
Sumita in view of Magdo does not explicitly teach: wherein a crystal orientation [110] of the first silicon wafer is coaxial with a crystal orientation [111] of the second silicon wafer, or the crystal orientation [110] of the first silicon wafer is perpendicular to the crystal orientation [111] of the second silicon wafer.
Sumita further teaches: a crystal orientation of the first silicon wafer (Sumita 21) and the second silicon wafer (Sumita 22) are selected such that an etching rate of the second silicon wafer is less than an etching rate of the first silicon wafer (Sumita ¶0029, 0046).
Amamiya, in the same field of endeavor of semiconductor device manufacturing, in at least one embodiment, teaches: a crystal orientation [110] of a first silicon wafer (Amamiya 1, ¶0012, “lower silicon substrate … (110)”) is coaxial with a crystal orientation [111] of the second silicon wafer (Amamiya 2, ¶0012, “upper silicon substrate … (111)”)(Amamiya ¶0017), or the crystal orientation [110] of the first silicon wafer is perpendicular to the crystal orientation [111] of the second silicon wafer (Amamiya ¶0017).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sumita in view of Magdo such that “a crystal orientation [110] of the first silicon wafer is coaxial with a crystal orientation [111] of the second silicon wafer, or the crystal orientation [110] of the first silicon wafer is perpendicular to the crystal plane [111] of the second silicon wafer”, as taught by Amamiya, in order to achieve etch selectivity between the first and second silicon wafers under the same etching conditions (Amamiya ¶0062).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to choose any number of suitable crystal orientations for the first silicon wafer or the second silicon wafer, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice (MPEP 2144.07).
SECOND INTERPRETATION
Claim Rejections - 35 USC § 103
Claims 1, 5-7, 11, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Amamiya (JP 3118390 B2, English translation of description provided in previous office action dated 03/25/2026, hereafter Amamiya) in view of Magdo et al (US 4256532 A, hereafter Magdo).
Regarding claim 1, Amamiya teaches: A silicon-based mask (Amamiya 1, 2, 13, fig 2, ¶0060), comprising a first silicon wafer (Amamiya 1, ¶0012, 0060) and a second silicon wafer (Amamiya 2, ¶0012, 0060) laminated one on another (Amamiya fig 2, ¶0060, under a BRI of “laminated”), wherein the first silicon wafer comprises a first via hole (Amamiya 11, 12, fig 2(c), ¶0061, hole formed by etch in 2(c)), the second silicon wafer comprises a second via hole (Amamiya 13, fig 2(e), ¶0063), an orthogonal projection of a wall of the first via hole onto the second silicon wafer surrounds the second via hole (Amamiya fig 2), and under a same etching condition, an etching rate of the second silicon wafer is smaller than an etching rate of the first silicon wafer (Amamiya ¶0062);
the silicon-based mask further comprising a first protection layer (Amamiya, bottom layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”) and a second protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”), wherein the first protection layer is located on a side of the first silicon wafer (Amamiya 1) away from the second silicon wafer (Amamiya 2)(Amamiya fig 2, bottom of 4 is on 1 away from 2), and the second protection layer is located on a side of the second silicon wafer away from the first silicon wafer (Amamiya fig 2, top of 4 is on 2 away from 1).
Amamiya does not teach: the first protection layer and/or the second protection layer comprises a first film layer and a second film layer laminated one on another, the first film layer is made of SiOx and located between the second film layer and the corresponding silicon wafer, the second film layer is made of SiNx.
Amamiya further teaches: the first protection layer and/or second protection layer (Amamiya 4) comprises SiOx or SiNx (Amamiya ¶0039, 0053).
Magdo, in the same field of endeavor of semiconductor device manufacturing, teaches: a first protection layer (Magdo 21’, 25’, col 4, lines 40-45, col 6, lines 28-31, “protective layers of insulating material”) and a second protection layer (Magdo 24, 25, col 4, lines 21-25, 36-40, col 6, lines 28-31) comprises a first film layer (Magdo 21’, 24, respectively) and a second film layer (Magdo 25’, 25, respectively) laminated one on another (Magdo figs 2B), the first film layer is made of SiOx (Magdo col 4, lines 11-25, “silicon dioxide”) and located between the second film layer and a corresponding silicon wafer (Magdo 20, 20’)(Magdo fig 2B, col 4, lines 11-35), the second film layer is made of SiNx (Magdo col 4, lines 36-40, “silicon nitride”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Amamiya such that the first and second protection layers comprised a first and second film layers of SiOx and SiNx, respectively, and such that they are “laminated one on another” and the first film layer is “located between the second film layer and the corresponding silicon wafer”, as taught by Magdo, in order to minimize stress between the substrate and mask while maintaining layer etch selectivity, and thereby avoiding dislocation in the substrate and/or to avoiding distortion of the mask during processing (Magdo col 4, lines 7-10, incorporated by reference US3904454A, col 4, lines 35-50).
Regarding claim 5, Amamiya in view of Magdo teaches: The silicon-based mask according to claim 1, wherein a thickness of the first silicon wafer (Amamiya 1) is greater than a thickness of the second silicon wafer (Amamiya 2)(Amamiya fig 2, ¶0060, 400 µm and 100 µm respectively).
Regarding claim 6, Amamiya in view of Magdo, in at least one embodiment, teaches: The silicon-based mask according to claim 5, wherein a crystal orientation [110] of the first silicon wafer (Amamiya 1, ¶0012, “lower silicon substrate … (110)”) is coaxial with a crystal orientation [111] of the second silicon wafer (Amamiya 2, ¶0012, “upper silicon substrate … (111)”)(Amamiya ¶0017), or the crystal orientation [110] of the first silicon wafer is perpendicular to the crystal orientation [111] of the second silicon wafer (Amamiya ¶0017).
Regarding claim 7, Amamiya in view of Magdo teaches: The silicon-based mask according to claim 1, wherein a doping type of the first silicon wafer (Amamiya 1) comprises a P-type or an N-type (Amamiya ¶0060, phosphorus doped, P-type), and a doping type of the second silicon wafer (Amamiya 2) comprises a P- type or an N-type (Amamiya ¶0060, phosphorus doped, P-type).
Regarding claim 11, Amamiya discloses: A method for manufacturing the silicon-based mask according to claim 1, comprising:
providing a first silicon wafer (Amamiya 1);
forming a second silicon wafer (Amamiya 2) on the first silicon wafer (Amamiya fig 2, ¶0060, formed on at least via bonding), under a same etching condition, an etching rate of the second silicon wafer being smaller than an etching rate of the first silicon wafer (Amamiya ¶0062); and
forming a first via hole in the first silicon wafer through wet etching (Amamiya 11, 12, fig 2(c), ¶0061, hole formed by etch in 2(c)), and forming a second via hole in the second silicon wafer through dry etching (Amamiya 13, fig 2(e), ¶0063), an orthogonal projection of a wall of the first via hole onto the second silicon wafer surrounding the second via hole (Amamiya fig 2);
wherein the forming the first via hole (Amamiya 11, 12, fig 2(c), ¶0061, hole formed by etch in 2(c)) in the first silicon wafer (Amamiya 1) through wet etching (Amamiya ¶0061) and forming the second via hole (Amamiya 13) in the second silicon wafer (Amamiya 2) through dry etching (Amamiya ¶0063) specifically comprises:
forming a first protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”) on a side of the first silicon wafer away from the second silicon wafer (Amamiya fig 2, formed at least in part on bottom of 1, away from 2), and forming a second protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”) on a side of the second silicon wafer away from the first silicon wafer (Amamiya fig 2, formed on top of 2, away from 1);
patterning the first protection layer (Amamiya ¶0067, fig 2(b)); forming the first via hole in the first silicon wafer through wet etching with the patterned first protection layer as a mask (Amamiya fig 2(c), ¶0068); and
forming the second via hole in the second protection layer and the second silicon wafer through dry etching (Amamiya ¶0071, fig 2(e)).
Amamiya does not teach: wherein the first protection layer and/or the second protection layer comprises a first film layer and a second film layer laminated one on another, the first film layer is made of SiOx and located between the second film layer and the corresponding silicon wafer, the second film layer is made of SiNx.
Amamiya further teaches: the first protection layer and/or second protection layer (Amamiya 4) comprises SiOx or SiNx (Amamiya ¶0039, 0053).
Magdo, in the same field of endeavor of semiconductor device manufacturing, teaches: a first protection layer (Magdo 21’, 25’, col 4, lines 40-45, col 6, lines 28-31, “protective layers of insulating material”) and a second protection layer (Magdo 24, 25, col 4, lines 21-25, 36-40, col 6, lines 28-31) comprises a first film layer (Magdo 21’, 24, respectively) and a second film layer (Magdo 25’, 25, respectively) laminated one on another (Magdo figs 2B), the first film layer is made of SiOx (Magdo col 4, lines 11-25, “silicon dioxide”) and located between the second film layer and a corresponding silicon wafer (Magdo 20, 20’)(Magdo fig 2B, col 4, lines 11-35), the second film layer is made of SiNx (Magdo col 4, lines 36-40, “silicon nitride”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Amamiya such that the first and second protection layers comprised a first and second film layers of SiOx and SiNx, respectively, and such that they are “laminated one on another” and the first film layer is “located between the second film layer and the corresponding silicon wafer”, as taught by Magdo, in order to minimize stress between the substrate and mask while maintaining layer etch selectivity, and thereby avoiding dislocation in the substrate and/or to avoiding distortion of the mask during processing (Magdo col 4, lines 7-10, incorporated by reference US3904454A, col 4, lines 35-50).
Regarding claim 16, Amamiya in view of Magdo teaches: The method according to claim 11, further comprising, subsequent to forming the first via hole (Amamiya 11, 12, fig 2(c), ¶0061, hole formed by etch in 2(c)) and the second via hole (Amamiya 13), removing the first protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067) and the second protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067)(Amamiya fig 2(f), ¶0072).
Regarding claim 17, Amamiya in view of Magdo teaches: The method according to claim 16, wherein the forming the first protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067) and the second protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067) specifically comprises forming the first protection layer and the second protection layer using an inorganic material (Amamiya 4, ¶0039, 0067), and the removing the first protection layer and the second protection layer specifically comprises removing the first protection layer and the second protection layer through wet etching using an etching solution (Amamiya ¶0044, 0072).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Amamiya (JP 3118390 B2, English translation of description provided in previous office action dated 03/25/2026, hereafter Amamiya) in view of Magdo et al (US 4256532 A, hereafter Magdo), as applied to claim 1 above, and further in view of Liu et al (US 20190326514 A1, hereafter Liu).
Regarding claim 9, Amamiya in view of Magdo teaches: The silicon-based mask according to claim 1.
Amamiya in view of Magdo does not teach: wherein each of the first protection layer and the second protection layer comprises a magnetic material layer.
Liu, in the same field of endeavor of semiconductor device manufacturing, teaches: a first protection layer (Liu 103, ¶0052, under a BRI of “protection layer”) and a second protection layer (Liu 106, ¶0054, under a BRI of “protection layer”) comprises a magnetic material layer (Liu ¶0061, 0063, “Ni”, applicant discloses suitable materials for a magnetic material layer include “Ni”, spec ¶0067).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first and second protection layers of Amamiya in view of Magdo to comprise a magnetic material, as taught by Liu, in order to prevent deformation, and/or breakage, and/or corrosion during cleaning (Liu ¶0035, 0064).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Amamiya (JP 3118390 B2, English translation of description provided in previous office action dated 03/25/2026, hereafter Amamiya) in view of Magdo et al (US 4256532 A, hereafter Magdo), as applied to claim 11 above, and further in view of Sasaki et al (JP 2001337444 A, English translation of description provided in previous office action dated 03/25/2026, hereafter Sasaki).
Regarding claim 13, Amamiya in view of Magdo teaches: The method according to claim 11, wherein the forming the first via hole (Amamiya 11, 12, fig 2(c), ¶0061, hole formed by etch in 2(c)) in the first silicon wafer (Amamiya 1) through wet etching (Amamiya ¶0061) and forming the second via hole (Amamiya 13) in the second silicon wafer (Amamiya 2) through dry etching (Amamiya ¶0063) specifically comprises:
forming the second via hole in the second silicon wafer through dry etching (Amamiya ¶0071, fig 2(e)).
forming a first protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”) on a side of the first silicon wafer away from the second silicon wafer (Amamiya fig 2, formed at least in part on bottom of 1, away from 2), and forming a second protection layer (Amamiya, top layer of 4 with respect to fig 2, ¶0067, under a BRI of “protection layer”) on a side of the second silicon wafer away from the first silicon wafer (Amamiya fig 2, formed on top of 2, away from 1); patterning the first protection layer (Amamiya ¶0067, fig 2(b)); and
forming the first via hole in the first silicon wafer through wet etching with the patterned first protection layer as a mask (Amamiya fig 2(c), ¶0068)
Amamiya in view of Magdo does not teach: the second protection layer covering a wall of the second via hole.
Sasaki teaches: forming a second via hole (Sasaki 6, 7) in a second silicon wafer (Sasaki 1) through dry etching (Sasaki fig 1, ¶0012), forming a second protection layer (Sasaki top of 8) covering a wall of the second via hole (Sasaki fig 1, ¶0012, 0025).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Amamiya in view of Magdo, such that the second via hole is formed before the second protective layer, and to conformally deposit the second protective layer such that “the second protection layer covering a wall of the second via hole”, as taught by Sasaki, in order to protect the second via holes from damage during subsequent wet etching steps and/or to prevent blockages or foreign matter adhesion (Sasaki ¶0006, 0010).
Regarding claim 14, Amamiya in view of Magdo and Sasaki teaches: The method according to claim 13, wherein the forming the second via hole (Amamiya 13, similar to Sasaki 7) in the second silicon wafer (Amamiya 2, similar to Sasaki 1) through dry etching (Amamiya ¶0063, as modified by Sasaki) specifically comprises:
forming a photoresist layer (Amamiya ¶0078, similar to Sasaki 5) on a side of the second silicon wafer away from the first silicon wafer (Amamiya 1, similar to Sasaki 3)(Amamiya ¶0078);
patterning the photoresist layer (Amamiya ¶0079);
forming the second via hole in the second silicon wafer through dry etching with the patterned photoresist layer as a mask (Amamiya ¶0079, fig 2(d)); and
removing the patterned photoresist layer (Amamiya ¶0080).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Amamiya (JP 3118390 B2, English translation of description provided in previous office action dated 03/25/2026, hereafter Amamiya) in view of Magdo et al (US 4256532 A, hereafter Magdo), as applied to claim 11 above, and further in view of Wang et al (US 7601215 B1, hereafter Wang).
Regarding claim 18, Amamiya in view of Magdo teaches: The method according to claim 11.
Amamiya in view of Magdo does not teach: wherein the forming the second silicon wafer on the first silicon wafer specifically comprises epitaxially growing the second silicon wafer on the first silicon wafer.
Wang, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a second silicon wafer (Wang col 2, lines 51-57, Si film, under a BRI of “wafer”) on a first silicon wafer (Wang col 4, lines 13-14, c-Si substrate) specifically comprises epitaxially growing the second silicon wafer on the first silicon wafer (Wang col 1, lines 19-36).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Amamiya in view of Magdo to include epitaxially growing the second silicon wafer on the first silicon wafer, as taught by Wang, in order to provide a controlled thickness and uniformity to the second silicon wafer (Wang col 1, lines 28-29, col 7, lines 31-35).
Response to Arguments
Applicant’s arguments filed 06/23/2026, with respect to claim 6 has been fully considered and is persuasive. The 35 USC § 112 rejection of claim 6 has been withdrawn.
Applicant’s arguments filed 06/23/2026, with respect to claims 1-7, 9-11, and 13-18 have been fully considered and are not persuasive.
Regarding claims 1 and 11, Feature A, the applicant alleges at pages 11-13:
In the present application, the silicon-based mask includes a first protection layer and a second protection layer. That is, the final silicon-based mask product possesses the first protection layer and the second protection layer, which helps improve the stress and flatness of the silicon-based mask.
In contrast, the etching mask 23 in Sumita is an intermediate medium used during the manufacturing process. It serves as a mask to allow the first substrate to be etched to form the opening 24, and is subsequently removed using a hot phosphoric acid solution, as referred to in paragraph [0047] of Sumita. Therefore, referring to Fig. 2, the final mask product of Sumita does not include the etching mask 23, meaning that its final product does not contain any protection layer.
In Amamiya, referring to Fig. 2, its layer 4 is also eventually removed and is not retained in the final mask product.
Examiner’s Response:
The examiner respectfully disagrees. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., retention of a protection layer) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Sumita and Amamiya disclose the mask as claimed; in each, the layers of the first and second protection layers are located as claimed. A reference is relevant as prior art for all it contains, not only for its final product (see MPEP 2123(I)).
Regarding claims 1 and 11, Feature B, the applicant alleges at pages 13 and 14:
Regarding Feature B, in the application, the first protection layer 30 and/or the second protection layer 40 includes a first film layer and a second film layer laminated one on another, the first film layer is made of SiOx and located between the second film layer and the corresponding silicon wafer (the first silicon wafer 30 or the second silicon wafer 40), the second film layer is made of SiNx.
Examiner’s Response:
Applicant’s arguments with respect to Feature B has been considered but is moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Dong et al (US 20230031623 A1) is cited as an example of an analogous silicon-based mask for display manufacturing having a silicon oxide film between a substrate and a nitride film over the outer surface.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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