DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections Claim s 9 , 12, and 14 are objected to because of the following informalities: line 7 of claim 9 contains the term “structure” when it should be structures . Claim s 1 2 and 14 are also objected to due to their claim dependenc ies . Appropriate correction is required. Claim s 10 and 15 are objected to because of the following informalities: line 12 of claim 10 contains the term “structure” when it should be structures . Claim 15 is also objected to due to its claim dependency. Appropriate correction is required. Claim s 20 -23 and 25 are objected to because of the following informalities: line 6 of claim 20 contains the term “structure” when it should be structures . Claim s 21, 22, 23, and 25 are also objected to due to their claim dependenc ies . Appropriate correction is required. Claims 27 and 28 are objected to because of the following informalities: the last line of claim 27 contains the term “structure” when it should be structures . Claim 28 is also objected to due to its claim dependency . Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 8, 9, 12, 14, 18, and 19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liaw (United States Patent Application Publication No. US 2020/0043918 A1, hereinafter “ Liaw ”) . In reference to claim 1, Liaw discloses a device which meets the claim. Fig. 1 -2C of Liaw disclose a semiconductor structure which compris es a substrate (100) that includes a first region ( region above line C-C’ in fig. 1 ) with a plurality of first active regions (AA) arranged along a first direction (D2). There is a first isolation region ( region under and between (108b) and (108c) ) that is located between adjacent first active regions (AA) of the plurality of first active regions (AA). A plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) is located over the substrate . T he plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) extends in parallel to the first direction (D2) and is arranged along a second direction (D1) which is perpendicular to the first direction (D2 ) . T he plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) spans the adjacent first active regions (AA) and the first isolation region ( region under and between (108b) and (108c) ) between the adjacent first active regions (AA). A plurality of first gate structure s (108b ) is located over the first isolation region ( region under and between (108b) and (108c) ) . T he plurality of first gate structure s (108b ) spans the plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) along the second direction (D1) . There is a plurality of first electrical interconnection structures ( 126, 132 ) electrically connected to the plurality of first gate structure s (108b ) . With regard to claim 2, there is a n isolation layer (103) over the substrate (100). T he isolation layer (103) covers a part of sidewalls of the plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) . A top surface of the isolation layer (103) is lower than a top surface of the plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) . A first gate structure (108b ) of the plurality of first gate structure s (108b ) includes a first portion located on a surface of a first fin ( fig. 1: (104) above line C-C’, fig. 2A, 2B: (104) - the two leftmost ) of the plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) and a second portion located on a surface of the isolation layer (103) and a first electrical interconnection structure (126, 132) of the plurality of first electrical interconnection structures (126, 132) is electrically connected to the second portion. In reference to claim 3, there is a first dielectric layer (114) located over the substrate (100). T he first dielectric layer (114) covers a sidewall of a first gate structure (108b ) of the plurality of first gate structure s (108b ) . With regard to claim 4, a first electrical interconnection structure (126, 132) of the plurality of first electrical interconnection structures (126, 132) includes a plurality of plugs (126) located on a top surface of a second portion of the first gate structure (108b ) , and an interconnection layer (132) located over the plurality of plugs (126). T he plurality of plugs (126) is separated from each other and a top surface of the first gate structure (108b ) is lower than a top surface of the first dielectric layer (114) and a part of the plurality of plugs (126) is located in the first dielectric layer (114) . In reference to claim 8, there is a second gate structure ( fig. 1: ( 108a ) above line C-C’ ) located over first active regions (AA) of the plurality of the first active regions (AA). T he second gate structure ( fig. 1: (108a) above line C-C’ ) spans the plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) along the second direction (D1). With regard to claim 9, the substrate further include s a second region . A plurality of second fins (fig. 1: (104) below line C-C’, fig. 2A, 2B: (104) - the two rightmost) is located over the second region (region below line C-C’ in fig. 1). T he plurality of second fins (fig. 1: (104) below line C-C’, fig. 2A, 2B: (104) - the two rightmost) extends in parallel to the first direction (D2) and is arranged along the second direction (D1). A plurality of third gate structures (fig. 1: (108a) below line C-C’) is located over the second region (region below line C-C’ in fig. 1). T he plurality of third gate structure s (fig. 1: (108a) below line C-C’) spans the plurality of second fins (fig. 1: (104) below line C-C’, fig. 2A, 2B: (104) - the two rightmost). A part of the plurality of third gate structures (fig. 1: (108a) below line C-C’) is connected to the second gate structure (fig. 1: (108a) above line C-C’) . In reference to claim 12, the re is a first source/drain doped layer (106) in a first fin (fig. 1: (104) above line C-C’, fig. 2A, 2B: (104) - the two leftmost) of the plurality of first fins (fig. 1: (104) above line C-C’, fig. 2A, 2B: (104) - the two leftmost) located on two sides of each of the plurality of first gate structures (108b) and on two side of the second gate structures (fig. 1: (108a) above line C-C’). T he first source/drain doped layer (106) contains first source/drain ions (p. 3, paragraph 30). T he re is a second source/drain doped layer (106) in a second fin (fig. 1: (104) below line C-C’, fig. 2A, 2B: (104) - the two rightmost) of the plurality of first fins (fig. 1: (104) below line C-C’, fig. 2A, 2B: (104) - the two rightmost) located on two sides of each of the plurality of third gate structures (fig. 1: (108a) below line C-C’). T he second source/drain doped layer (106) contains second source/drain ions (p. 3, paragraph 30). Liaw discloses (p. 1, paragraph 22) that the semiconductor structure is a CMOS structure which includes NMOS transistors (n-type source/drains) and PMOS transistors (p-type source/drains). Therefore the first source/drain doped layer (106) in a first fin (fig. 1: (104) above line C-C’, fig. 2A, 2B: (104) - the two leftmost) is for an NMOS transistor which makes the first source/drain doped layer (106) in a first fin (fig. 1: (104) above line C-C’, fig. 2A, 2B: (104) - the two leftmost) doped with N-type ions. Thus the second source/drain doped layer (106) in a second fin (fig. 1: (104) below line C-C’, fig. 2A, 2B: (104) - the two rightmost) is for a PMOS transistor which makes the second source/drain doped layer (106) in a second fin (fig. 1: (104) below line C-C’, fig. 2A, 2B: (104) - the two rightmost) doped with P-type ions. Thus the conductivity type of the first source/drain doped layer (106) in a first fin (fig. 1: (104) above line C-C’, fig. 2A, 2B: (104) - the two leftmost) is different from the conductivity type of the second source/drain doped layer (106) in a second fin (fig. 1: (104) below line C-C’, fig. 2A, 2B: (104) - the two rightmost). With regard to claim 14, there is a first conductive layer (118) over the first source/drain doped layer (106) in a first fin (fig. 1: (104) above line C-C’, fig. 2A, 2B: (104) - the two leftmost). There is a second conductive layer (118) over the second source/drain doped layer (106) in a second fin (fig. 1: (104) below line C-C’, fig. 2A, 2B: (104) - the two rightmost). In reference to claim 18, Liaw discloses a method which meets the claim. Fig. 1-2C of Liaw disclose a method of forming a semiconductor structure which compris es providing a substrate (100) that includes a first region ( region above line C-C’ in fig. 1 ) with a plurality of first active regions (AA) arranged along a first direction (D2). A first isolation region ( region under and between (108b) and (108c) ) is formed that is located between adjacent first active regions (AA) of the plurality of first active regions (AA). A plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) is formed over the first region ( region above line C-C’ in fig. 1 ) . T he plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) extend s in parallel to the first direction (D2) and is arranged along a second direction (D1) which is perpendicular to the first direction (D2). T he plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) spans the adjacent first active regions (AA) and the first isolation region ( region under and between (108b) and (108c) ) between the adjacent first active regions (AA). A plurality of first gate structure s (108b ) is formed which is located over the first isolation region ( region under and between (108b) and (108c) ). T he plurality of first gate structure (108b ) spans the plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) along the second direction (D1). A plurality of first electrical interconnection structures (126, 132) is formed and is electrically connected to the plurality of first gate structure (108b ) . With regard to claim 19, a n isolation layer (103) is formed over the substrate (100) after forming the plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) . T he isolation layer (103) covers a part of sidewalls of the plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) . A top surface of the isolation layer (103) is lower than a top surface of the plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) . Claims 27 and 28 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liaw and as further evidenced by Marshall et al. (United States Patent Application Publication No. US 2005/0024121 A1, hereinafter “Marshall”) . In reference to claim 27, Liaw discloses a method which meets the claim. Fig. 1-2C of Liaw disclose an operation method of a semiconductor structure which comprises providing a semiconductor structure that includes a substrate (100) having a first region ( region above line C-C’ in fig. 1 ) with a plurality of first active regions (AA) arranged along a first direction (D2). There is a first isolation region ( region under and between (108b) and (108c) ) that is located between adjacent first active regions (AA) of the plurality of first active regions (AA). A plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) is located over the substrate . T he plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) extends in parallel to the first direction (D2) and is arranged along a second direction (D1) which is perpendicular to the first direction (D2). T he plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) spans the adjacent first active regions (AA) and the first isolation region ( region under and between (108b) and (108c) ) between the adjacent first active regions (AA). A plurality of first gate structure (108b ) is located over the first isolation region ( region under and between (108b) and (108c) ). T he plurality of first gate structure (108b ) spans the plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) along the second direction (D1). There is a plurality of first electrical interconnection structures (126, 132) electrically connected to the plurality of first gate structure s (108b ) . Liaw discloses that the semiconductor structure is an NMOS transistor (p. 1, paragraph 22). Marshall discloses that a negative voltage turns off the transistor channel in NMOS transistors (p. 1, paragraph 11). Thus in the operation method of Liaw , a voltage is applied to the plurality of first electrical interconnection structures (126, 132) to turn off a channel region (which turns off the NMOS transistors) at a bottom of the plurality of first gate structure (108b ). With regard to claim 28, the semiconductor structure further includes a first source/drain doped layer (106) in a first fin (104) of the plurality of first fins (fig. 1: (104) above line C-C’ , fig. 2A, 2B: (104) - the two leftmost) located on two sides of each of the plurality of first gate structure (108b ). T he first source/drain doped layer (106) contains first source/drain ions (p. 3, paragraph 30). Liaw discloses (p. 1, paragraph 22) that the semiconductor structure includes NMOS transistors (n-type source/drains) and PMOS transistors (p-type source/drains). Marshall discloses (p. 1, paragraph 11) that a negative voltage turns off the transistor channel in NMOS transistors (p. 1, paragraph 11) while a positive voltage turns off the transistor channel in PMOS transistors. Thus in the operation method of Liaw , when the first source/drain ions are N-type ions (NMOS transistor) , applying a negative voltage to the plurality of first electrical interconnection structures, and when the first source/drain ions are P-type ions (PMOS transistor) , applying a positive voltage to the plurality of first electrical interconnection structures (126, 132) turns off the respective transistors . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Oh et al. (United States Patent Application Publication No. US 2016 / 0379893 A1, hereinafter “Oh”) . In reference to claim 6, fig. 1-2C of Liaw disclose that a first electrical interconnection structure (126, 132) of the plurality of first electrical interconnection structures (126, 132) includes plugs (126) located over a top surface of adjacent first gate structures (108b) of the plurality of first gate structures (108b) and an interconnection layer located (132) over the plugs (126). Fig. 2C shows that a top surface of the first gate structure (108b) is lower than a top surface of the first dielectric layer (114) and a part of the plugs (126) is also located in the first dielectric layer (114) . Liaw does not disclose that the plugs (126) are also located over a surface of the first dielectric layer (114) between the adjacent first gate structures (108b). However fig. 6A- 6 C B of Oh discloses the use of offset gate contact plugs (140) over a surface of the first dielectric layer (128) between the adjacent first gate structures (1 26 ). Oh discloses that such a structure provides the benefit of improved function capacity and yield (p. 3, paragraph 36). In view of Oh, it would therefore be obvious to implement plugs that are located over a surface of the first dielectric layer (114) between the adjacent first gate structures (108b) in the Liaw device. Allowable Subject Matter Claim s 10, 15, 20-23, and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims AND if the claim language of claims 10 and 20 is corrected (see above section titled Claim Objections ) . The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion , it would not be obvious to implement a semiconductor structure which compri ses a substrate that includes a first region with a plurality of first active regions arranged along a first direction and a first isolation region located between adjacent first active regions of the plurality of first active regions , a plurality of first fins located over the substrate which extends in parallel to the first direction and is arranged along a second direction ( perpendicular to the first direction ) , and the plurality of first fins spans the adjacent first active regions and the first isolation region between the adjacent first active regions , a plurality of first gate structures located over the first isolation region and spans the plurality of first fins along the second direction , a plurality of first electrical interconnection structures electrically connected to the plurality of first gate structures , a second gate structure located over first active regions of the plurality of the first active regions and spans the plurality of first fins along the second direction in combination with the specific second region, plurality of second active regions, second isolation region, plurality of third fins, plurality of fourth gate structures, plurality of second electrical interconnection structures, and fifth gate structure explicitly described by the applicant in claim 10. In the examiner’s opinion, it would also not be obvious to implement a method for forming a semiconductor structure which compris es providing a substrate that includes a first region with a plurality of first active regions arranged along a first direction and a first isolation region located between adjacent first active regions of the plurality of first active regions , forming a plurality of first fins over the first region that extends in parallel to the first direction and is arranged along a second direction ( perpendicular to the first direction ) , and the plurality of first fins spans the adjacent first active regions and the first isolation region between the adjacent first active regions , forming a plurality of first gate structures over the first isolation region such that the plurality of first gate structures spans the plurality of first fins along the second direction , f orming a plurality of first electrical interconnection structures electrically connected to the plurality of first gate structures in combination with the specific formation step of a plurality of first dummy gate structures as described by the applicant in claim 20. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT KEVIN QUINTO whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1920 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday, 9-5:30 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Britt Hanley can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-270-3042 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEVIN QUINTO/ Examiner, Art Unit 2893 /Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893