Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“Resistive RAM Device Having Primary Memory Layer With Oxygen Gradient”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 10-11, 13, 17, 19, 23, 26 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2021/0175418 A1) in view of Yamaguchi et al. (US 2012/0012807 A1).
Regarding independent claim 1: Hsu teaches (e.g., Fig. 1 and Fig. 2) a non-volatile memory device, comprising:
a primary memory layer ([0014], [0017] and [0021]: 106/108/110) having:
a first active layer ([0014], [0017] and [0021]: 106) of a second metal oxide ([0014], [0017] and [0021]: 106 includes a second metal oxide material), the first active layer being immediately adjacent and connected to an underlying layer (Fig. 1);
a second active layer ([0014], [0017] and [0021]: layer 108 functions as a second active layer due to its material) of a third metal oxide ([0014], [0017] and [0021]: 108 includes a third metal oxide material); and
a third active layer ([0014], [0017] and [0021]: layer 110 functions as a third active layer due to its material),
the second active layer (108) being disposed between the first active layer (106) and the third active layer (110),
wherein the primary memory layer is characterized by an oxygen gradient (Fig. 2; [0025]: oxygen gradient shown on Fig. 2), and
wherein a highest oxygen concentration is associated with the first active layer (Fig. 2; [0025]: first active layer 106), and
wherein a lowest oxygen concentration is associated with the third active layer (Fig. 2; [0025]: third active layer 110).
Hsu does not expressly teach a buffer layer of a first metal oxide; first active layer being immediately adjacent and connected to the buffer layer.
Yamaguchi teaches (e.g., Fig. 4G) a non-volatile memory device, comprising a first active layer ([0058]: 124);
Yamaguchi further teaches a buffer layer ([0058]: 127) of a first metal oxide ([0058]: 127 includes a first metal oxide, [0053]-[0054]: The buffer layer 127 then absorbs hafnium (Hf) included in the variable resistance layer 124 to become HfSiO.sub.x.”; [0056]: “the buffer layer 127 are configured by similar materials to in the first example and the fourth example, respectively”); first active layer ([0058]: 124) being immediately adjacent and connected to the buffer layer ([0058]: 127).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Hsu, the buffer layer of the first metal oxide; the first active layer being immediately adjacent and connected to the buffer layer, as taught by Yamaguchi, for the benefits of suppressing variation in resistance value among a plurality of variable resistance layers, and thus increasing memory device yield (Yamaguchi: [0054]).
Regarding claim 6: Hsu and Yamaguchi teach the claim limitation if the non-volatile memory device as set forth in claim 1, on which this claim depends,
Hsu as modified by Yamaguchi teaches that wherein each of the first active layer, the second active layer, and the third active layer is associated with a respective work function, and wherein the respective work function decreases from the first active layer to the second active layer, and wherein the respective work function decreases from the second active layer to the third active layer (Hsu: [0014]: the first work function metal oxide 106 comprises magnesium oxide, MgO; [0017]: the second work function of metal oxide 108 comprises tantalum oxide, TaO.sub.2-1 and [0021]: the third work function of metal oxide 110 comprises tantalum oxide; this meet the claim requirement of decreasing work functions).
Regarding claim 7: Hsu and Yamaguchi teach the claim limitation if the non-volatile memory device as set forth in claim 1, on which this claim depends,
Hsu as modified by Yamaguchi teaches that the first metal oxide is characterized by a stoichiometric or near stoichiometric composition (Hsu: [0014]); and
wherein the first metal oxide comprises one of AlOx, SiOx, MgOx, CaOx, HfSiOx, or any combination thereof (Yamaguchi: [0053]: first metal oxide of 127 comprises AlO.sub.x).
Regarding claim 10: Hsu and Yamaguchi teach the claim limitation if the non-volatile memory device as set forth in claim 1, on which this claim depends,
wherein the second metal oxide comprises one of Ta oxide, Hf oxide, Zr oxide, Ti oxide, La oxide, or any combination thereof (Hsu: [0014]: the second metal oxide 106 comprises tantalum oxide, Ta.sub.2O.sub.5), and
wherein the second metal oxide is characterized by a stoichiometric or near stoichiometric composition (Hsu: second metal oxide comprises [0014]: the second metal oxide of 106 comprises Ta.sub.2O.sub.5).
Regarding claim 11: Hsu and Yamaguchi teach the claim limitation if the non-volatile memory device as set forth in claim 1, on which this claim depends,
wherein the third metal oxide comprises one of Ta oxide, Hf oxide, Zr oxide, Ti oxide, La oxide, or any combination thereof (Hsu: [0021]: the third metal oxide of 108 comprises tantalum oxide).
Regarding claim 13: Hsu and Yamaguchi teach the claim limitation if the non-volatile memory device as set forth in claim 1, on which this claim depends,
wherein the third active layer comprises a fourth metal oxide, wherein the fourth metal oxide comprises one of Ta oxide, Hf oxide, Zr oxide, Ti oxide, La oxide, or any combination thereof (Hsu: [0021]: fourth metal oxide of layer 110 comprises tantalum oxide).
Regarding claim 17: Hsu and Yamaguchi teach the claim limitation if the non-volatile memory device as set forth in claim 1, on which this claim depends,
wherein the third active layer comprises an active metal, and wherein the active metal is selected from the group consisting of Ta, Ti, Hf, and Zr or from the group consisting of Co, Ni, Fe, and an alloy of any two or more of Co, Ni, and Fe (Hsu: second metal oxide comprises [0014]: the second metal oxide of 106 comprises Ta.sub.2O.sub.5, thus the active layer is Ta).
Regarding claim 19: Hsu and Yamaguchi teach the claim limitation if the non-volatile memory device as set forth in claim 1, on which this claim depends,
wherein the buffer layer comprises
A
l
2
O
3
(Yamaguchi: [0062]), and wherein the first active layer comprises
T
a
2
O
x
in which 4.5<= x<=5 (Hsu: [0014]).
Regarding claim 23: Hsu and Yamaguchi teach the claim limitation if the non-volatile memory device as set forth in claim 1, on which this claim depends,
further comprises a first electrode layer (Hsu: [0027]: 102) and a second electrode layer (Hsu: [0027]: 104),
Hsu as modified by Yamaguchi teaches that the buffer layer (Yamaguchi: Fig. 4G: buffer layer 127) and the primary memory layer (Hsu: 106/108/110) are disposed between the first electrode layer (Hsu: [0027]: 102) and the second electrode layer (Hsu: [0027]: 104).
Regarding claim 26: Hsu and Yamaguchi teach the claim limitation if the non-volatile memory device as set forth in claim 1, on which this claim depends,
wherein each of the first active layer (Hsu: [0021]: 2nm to 10nm), the second active layer (Hsu: [0019]: 108 has a thickness of 10nm to 50 nm), and
the third active layer has a film thickness in a range from 0.3 nanometer to 50 nanometers (Hsu: [0020]: 0.3 nm to 10 nm).
Hsu as modified by Yamaguchi teaches an overlapping range of 1 nanometer to 10 nanometers.
Applicant is reminded that a prima facie case of obviousness typically exists when the ranges of a claimed composition overlap the ranges disclosed in the prior art or when the ranges of a claimed composition do not overlap but are close enough such that one skilled in the art would have expected them to have the same properties. In re Peterson, 65 USPQ2d 1379 (CA FC 2003).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to adapt the teachings of Hsu as modified by Yamaguchi to meet the particularities of the present claimed invention based on desired device electrical characteristics or requirements.
Regarding independent claim 30: Hsu teaches (e.g., Fig. 1 and Fig. 2) a non-volatile memory device, comprising:
a first electrode layer ([0014]: 102);
a second electrode layer ([0014]: 104);
a primary memory layer ([0014], [0017] and [0021]: 106/108/110) comprising three active layers ([0014], [0017] and [0021]: 106) disposed between an underlying layer and the second electrode (104),
the first active layer is physically connected to the third active layer ([0014], [0017] and [0021]: layer 110 functions as a third active layer due to its material) is physically connected to the second electrode (104);
wherein the first active layer having a high oxygen concentration (Fig. 2; [0025]: first active layer 106),
the second active layer (Fig. 2; [0025]: first active layer 108) having a lower oxygen concentration than the first active layer (Fig. 2; [0025]: first active layer 106), and
the third active layer (Fig. 2; [0025]: first active layer 110) having a lower oxygen concentration than the second active layer (Fig. 2; [0025]: first active layer 108),
an oxygen concentration decreasing in stages or gradually in a direction from the first active layer to the third active layer (Fig. 2; [0025]).
Hsu does not expressly teach
a buffer layer disposed between the first electrode and the second electrode;
the primary memory layer disposed between the buffer layer and the second electrode, the first active layer is physically connected to the buffer layer and the third active layer.
Yamaguchi teaches (e.g., Fig. 4G) a non-volatile memory device, comprising a primary layer ([0058]: 124), a first electrode ([0043]: 123) and a second electrode ([0043]: 125);
Yamaguchi further teaches a buffer layer ([0058]: 127) disposed between the first electrode ([0043]: 123) and the second electrode ([0043]: 125);
the primary memory layer ([0058]: 124) disposed between the buffer layer (127) and the second electrode (125),
the first active layer ([0043]: lower portion of 124) is physically connected to the buffer layer (127) and the third active layer (uppermost portion of primary memory layer 124).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Hsu, the buffer layer disposed between the first electrode and the second electrode; disposed between the buffer layer and the second electrode, and the first active layer being physically connected to the buffer layer and the uppermost active layer, as taught by Yamaguchi and arrive at “a buffer layer disposed between the first electrode and the second electrode; the primary memory layer disposed between the buffer layer and the second electrode, the first active layer is physically connected to the buffer layer and the third active layer, for the benefits of suppressing variation in resistance value among a plurality of variable resistance layers, and thus increasing memory device yield (Yamaguchi: [0054]).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2021/0175418 A1) in view of Yamaguchi et al. (US 2012/0012807 A1) as applied above and further in view of Lee et al. (US 2012/0049145 A1).
Regarding claim 27: Hsu and Yamaguchi teach the claim limitation if the non-volatile memory device as set forth in claim 1, on which this claim depends.
Hsu as modified by Yamaguchi does not expressly teach that the buffer layer has a film thickness in a range from 0.5 nanometer to 5 nanometers.
Lee teaches (e.g., Fig. 1) a non-volatile memory device, comprising a buffer layer ([0070]: B1);
Lee further teaches that the buffer layer has a film thickness in a range from 0.5 nanometer to 10 nanometers ([0070]).
Lee teaches an overlapping range with the range from 0.5 nanometer to 5 nanometers.
Applicant is reminded that a prima facie case of obviousness typically exists when the ranges of a claimed composition overlap the ranges disclosed in the prior art or when the ranges of a claimed composition do not overlap but are close enough such that one skilled in the art would have expected them to have the same properties. In re Peterson, 65 USPQ2d 1379 (CA FC 2003).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to adapt the teachings of Hsu as modified by Yamaguchi and Lee to arrive at “the buffer layer has a film thickness in a range from 0.5 nanometer to 5 nanometers“ so as to meet the particularities of the present claimed invention based on desired device electrical characteristics or requirements.
Allowable Subject Matter
Claims 12, 14-16, 20-21 and 28-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 12: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a non-volatile memory device comprising:
“wherein the second metal oxide and the third metal oxide are of a same group, and wherein the third metal oxide further comprises a first dopant, the first dopant being a metal different from any metal element forming the second metal oxide”.
Regarding claim 14: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a non-volatile memory device comprising:
“wherein the third metal oxide and the fourth metal oxide are of a same group, and wherein the fourth metal oxide further comprises a second dopant, the second dopant being a metal different from any metal element forming the second metal oxide”.
Regarding claim 15: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a non-volatile memory device comprising:
“wherein the third active layer comprises a fourth metal oxide, and wherein the fourth metal oxide is doped with a second dopant, the second dopant being a metal that is same as a first dopant”.
Regarding claim 16: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a non-volatile memory device comprising:
“wherein the third active layer comprises a fourth metal oxide, and wherein the fourth metal oxide is doped with a second dopant, the second dopant being a metal that is different from a first dopant”.
Regarding claim 20: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a non-volatile memory device comprising:
“wherein the second active layer comprises
T
a
O
y
in which 1<= y <=2.2, and
wherein the second active layer is doped with a first dopant, the first dopant being a metal different from any metal present in the first active layer”.
Claims 21 and 28-29 depend from claim 20, and therefore, are allowable for the same reason as claim 20.
Conclusion
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/HERVE-LOUIS Y ASSOUMAN/Examiner, Art Unit 2812