DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, it recites “wherein at least one of the source electrode and the drain electrode is formed on a side of the substrate of the channel layer” in the last two lines. It is unclear what side “of the substrate of the channel layer” refers to and is confusing. For the purpose of applying prior art, this will be interpreted using the broadest reasonable interpretation, wherein at least one of the source electrode and the drain electrode is formed on a side of the substrate that is the same as that of the channel layer. For at least this reason, claims 2-13 are also rejected based on their dependency from claim 1.
Regarding Claim 4, it recites “wherein the source electrode, the first carrier supply layer, and the first barrier layer are formed on the side of the substrate of the channel layer”. It is unclear what side “of the substrate of the channel layer” refers to and is confusing. For the purpose of applying prior art, this will be interpreted using the broadest reasonable interpretation, wherein the source electrode, the first carrier supply layer, and the first barrier layer are formed on the side of the substrate that is the same as that of the channel layer. For at least this reason, claims 10 is also rejected based on its dependency from claim 4.
Regarding Claim 5, it recites “wherein the drain electrode, the second carrier supply layer, and the second barrier layer are formed on the side of the substrate of the channel layer”. It is unclear what side “of the substrate of the channel layer” refers to and is confusing. For the purpose of applying prior art, this will be interpreted using the broadest reasonable interpretation, wherein the drain electrode, the second carrier supply layer, and the second barrier layer are formed on the side of the substrate that is the same as that of the channel layer. For at least this reason, claims 6, 7, and 11-13 are also rejected based on their dependency from claim 5.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-8, and 10-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Julio Costa et al. (US 6521961 B1; hereinafter Costa).
Regarding Claim 1, Costa teaches a semiconductor device (Fig. 1) comprising:
a field-effect transistor (100), which includes
a channel layer (114) made of a compound semiconductor (InGaAs; C2:L44-L45) and formed on a substrate (108);
a gate electrode (104; C2:L53-L54) formed on the channel layer (114); and
a source electrode (128) and a drain electrode (130) (C3:L55-L60), both formed with the gate electrode (104) interposed therebetween (as shown in Fig. 1),
wherein at least one of the source electrode (128) and the drain electrode (130) is formed on a side of the substrate (108) of the channel layer (114) (one of 128 and 130 is formed on a same side of the substrate 108 as the channel layer 114 as shown in Fig. 1).
Regarding Claim 3, Costa teaches the semiconductor device according to claim 1, further comprising:
a first carrier supply layer (120 under source electrode 128 hereinafter 120a; which is doped with Si as described in C3:L33-L48; This interpretation is commensurate in scope with the instant application, such as in instant Fig. 2 wherein one integrally formed layer {206 and/or 207} is interpreted as different layers {206a/207a and 206b/207b} vertically aligned with respective source or drain electrodes, this interpretation similarly applies to the first and second layers following) formed between the source electrode (128) and the channel layer (114);
a first barrier layer (116 under source electrode 128 hereinafter 116a; C2:L42-L45) made of a compound semiconductor (AlGaAs) and formed between the source electrode (128) and the channel layer (114);
a second carrier supply layer (120 under drain electrode 130 hereinafter 120b) formed between the drain electrode (130) and the channel layer (114); and
a second barrier layer (116 under drain electrode 130 hereinafter 116b) made of a compound semiconductor (AlGaAs) and formed between the drain electrode (130) and the channel layer (114) (as shown in Fig. 1).
Regarding Claim 4, Costa teaches the semiconductor device according to claim 3, wherein the source electrode (128), the first carrier supply layer (120a), and the first barrier layer (116a) are formed on the side of the substrate (108) of the channel layer (114) (as shown in Fig. 1).
Regarding Claim 5, Costa teaches the semiconductor device according to claim 3, wherein the drain electrode (130), the second carrier supply layer (120b), and the second barrier layer (116b) are formed on the side of the substrate (108) of the channel layer (114) (as shown in Fig. 1).
Regarding Claim 6, Costa teaches the semiconductor device according to claim 5, wherein
the source electrode (128), the first carrier supply layer (120a), and the first barrier layer (116a) are formed on the side of the substrate (108) of the channel layer (114),
the first carrier supply layer (120a) and the second carrier supply layer (120b) are integrally formed (they are integrally formed as a same layer, commensurate in scope with the instant application), and
the first barrier layer (116a) and the second barrier layer (116b) are integrally formed (they are integrally formed as a same layer, commensurate in scope with the instant application).
Regarding Claim 7, Costa teaches the semiconductor device according to claim 6, further comprising: a third carrier supply layer (120 under the gate electrode 104; hereinafter 120c) formed between the channel layer (114) and the gate electrode (104).
Regarding Claim 8, Costa teaches the semiconductor device according to claim 3, further comprising:
a first contact layer (heavily N+ doped 124 under the source electrode 128, hereinafter 124a; C3:L56-C4:L2) made of a compound semiconductor (GaAs) and formed between the source electrode (128) and the first barrier layer (116a); and
a second contact layer (heavily N+ doped 124 under the source electrode 130, hereinafter 124b; C3:L56-C4:L2) made of a compound semiconductor (GaAs) and formed between the drain electrode (130) and the second barrier layer (116b),
wherein the source electrode (128) is formed in ohmic contact with the first contact layer (124a) (C6:L9-L13), and
the drain electrode (130) is formed in ohmic contact with the second contact layer (124b)(C6:L9-L13).
Regarding Claim 10, Costa teaches the semiconductor device according to claim 4, further comprising:
a first contact layer (heavily N+ doped 124 under the source electrode 128, hereinafter 124a; C3:L56-C4:L2) made of a compound semiconductor (GaAs) and formed between the source electrode (128) and the first barrier layer (116a); and
a second contact layer (heavily N+ doped 124 under the source electrode 130, hereinafter 124b; C3:L56-C4:L2) made of a compound semiconductor (GaAs) and formed between the drain electrode (130) and the second barrier layer (116b),
wherein the source electrode (128) is formed in ohmic contact with the first contact layer (124a) (C6:L9-L13), and
the drain electrode (130) is formed in ohmic contact with the second contact layer (124b)(C6:L9-L13).
Regarding Claim 11, Costa teaches the semiconductor device according to claim 5, further comprising:
a first contact layer (heavily N+ doped 124 under the source electrode 128, hereinafter 124a; C3:L56-C4:L2) made of a compound semiconductor (GaAs) and formed between the source electrode (128) and the first barrier layer (116a); and
a second contact layer (heavily N+ doped 124 under the source electrode 130, hereinafter 124b; C3:L56-C4:L2) made of a compound semiconductor (GaAs) and formed between the drain electrode (130) and the second barrier layer (116b),
wherein the source electrode (128) is formed in ohmic contact with the first contact layer (124a) (C6:L9-L13), and
the drain electrode (130) is formed in ohmic contact with the second contact layer (124b)(C6:L9-L13).
Regarding Claim 12, Costa teaches the semiconductor device according to claim 6, further comprising:
a first contact layer (heavily N+ doped 124 under the source electrode 128, hereinafter 124a; C3:L56-C4:L2) made of a compound semiconductor (GaAs) and formed between the source electrode (128) and the first barrier layer (116a); and
a second contact layer (heavily N+ doped 124 under the source electrode 130, hereinafter 124b; C3:L56-C4:L2) made of a compound semiconductor (GaAs) and formed between the drain electrode (130) and the second barrier layer (116b),
wherein the source electrode (128) is formed in ohmic contact with the first contact layer (124a) (C6:L9-L13), and
the drain electrode (130) is formed in ohmic contact with the second contact layer (124b)(C6:L9-L13).
Regarding Claim 13, Costa teaches the semiconductor device according to claim 7, further comprising:
a first contact layer (heavily N+ doped 124 under the source electrode 128, hereinafter 124a; C3:L56-C4:L2) made of a compound semiconductor (GaAs) and formed between the source electrode (128) and the first barrier layer (116a); and
a second contact layer (heavily N+ doped 124 under the source electrode 130, hereinafter 124b; C3:L56-C4:L2) made of a compound semiconductor (GaAs) and formed between the drain electrode (130) and the second barrier layer (116b),
wherein the source electrode (128) is formed in ohmic contact with the first contact layer (124a) (C6:L9-L13), and
the drain electrode (130) is formed in ohmic contact with the second contact layer (124b)(C6:L9-L13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Costa in view of Kyle Bothe et al. (US 20200395475 A1; hereinafter Bothe).
Regarding Claim 2, Costa teaches the semiconductor device according to claim 1, but is silent regarding wherein two of the field-effect transistors are provided on the substrate, the two field-effect transistors sharing at least one of the gate electrode, the source electrode on an upper side of the channel layer, and the drain electrode on the upper side of the channel layer.
In the same field of endeavor, Bothe teaches a similar HEMT (Fig. 3A, 3B, and 3C) wherein two field effect transistors (300_A and 300_B; ¶0095) are provided on a substrate (322; ¶0083), wherein the two field effect transistors sharing at least the ohmic source electrode (315_AB are shared; ¶0095) on an upper side of a channel layer (324; ¶0087).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosures to have the multiple transistors with a shared electrode (of Bothe) for the device of Costa in order to make a plurality of transistor unit cells (Bothe; ¶0095) with a reduced distance between adjacent source contacts (Bothe; ¶0097), thereby increasing device density.
Regarding Claim 9, modified Costa teaches the semiconductor device according to claim 2, further comprising:
a first carrier supply layer (120 under source electrode 128 hereinafter 120a; which is doped with Si as described in C3:L33-L48; This interpretation is commensurate in scope with the instant application, such as in instant Fig. 2 wherein one integrally formed layer {206 and/or 207} is interpreted as different layers {206a/207a and 206b/207b} vertically aligned with respective source or drain electrodes, this interpretation similarly applies to the first and second layers following) formed between the source electrode (128) and the channel layer (114);
a first barrier layer (116 under source electrode 128 hereinafter 116a; C2:L42-L45) made of a compound semiconductor (AlGaAs) and formed between the source electrode (128) and the channel layer (114);
a second carrier supply layer (120 under drain electrode 130 hereinafter 120b) formed between the drain electrode (130) and the channel layer (114); and
a second barrier layer (116 under drain electrode 130 hereinafter 116b) made of a compound semiconductor (AlGaAs) and formed between the drain electrode (130) and the channel layer (114) (as shown in Fig. 1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20120043586 A1 shows formation of electrodes on respective front and back surfaces of a HEMT substrate in order to reduce wiring spacing reducing chip area size. US 20200381554 A1 teaches forming a drain electrode on a backside of the HEMT semiconductor device substrate to increase density of transistors and improving yield/performance. US 20180358359 A1 shows formation of source and drain electrodes on a backside and the gate electrode on the front side, thereby reducing parasitic capacitance.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898