DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments/amendments, see Remarks (p. 6-7)/Claims, filed 05 May 2026, with respect to the rejection(s) of the claim(s) in the previous Office action have been fully considered and are persuasive. Therefore, the previous rejection(s) has/have been withdrawn. However, upon further search and consideration, a new ground(s) of rejection (as required by the amendments) is made in view of newly cited reference Tomas A Palacios et al. (US 20150270356 A1), as presented in detail below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 14, 16, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tomas A Palacios et al. (US 20150270356 A1; hereinafter Palacios).
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Regarding Claim 1, Palacios discloses a semiconductor device (Fig. 4) comprising:
a field-effect transistor (¶0045), which includes
a channel layer (channel layer of channel region 6) made of a compound semiconductor (¶0045) and formed on a substrate (1; ¶0039);
a gate electrode (14; ¶0045) formed on the channel layer (of 6); and
a source electrode (12; ¶0045) and a drain electrode (4; ¶0039), both formed with the gate electrode (14) interposed therebetween (as shown in Fig. 4),
wherein at least one of the source electrode (12) and the drain electrode (4) is formed on a back surface of the substrate (1) (as shown in Fig. 4).
Regarding Claim 14, Palacios discloses the semiconductor device according to claim 1, wherein at least one of the source electrode and the drain electrode (4) is formed only on the back surface of the substrate (1) (as shown in Fig. 4 and commensurate in scope with Applicant’s figures).
Regarding Claim 16, Palacios discloses the semiconductor device according to claim 14, wherein the drain electrode (4) is formed only on the back surface of the substrate (4) (as shown in Fig. 4).
Regarding Claim 17, Palacios discloses the semiconductor device according to claim 1, wherein the front surface and the back surface of the substrate (1) are on opposing sides of the substrate (as shown in Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Palacios in view of Kyle Bothe et al. (US 20200395475 A1; hereinafter Bothe).
Regarding Claim 2, Palacios discloses the semiconductor device according to claim 1, but does not expressly disclose wherein two of the field-effect transistors are provided on the substrate, the two field-effect transistors sharing at least one of the gate electrode, the source electrode on an upper side of the channel layer, and the drain electrode on the upper side of the channel layer.
In the same field of endeavor, Bothe teaches a similar semiconductor device (Fig. 2A, 2B, 2C, and 3) wherein two field effect transistors (300_A and 300_B; ¶0095) are provided on a substrate (322; ¶0083), wherein the two field effect transistors sharing at least the ohmic source electrode (315_AB are shared; ¶0095) on an upper side of a channel layer (324; ¶0087).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosures to have the multiple transistors with a shared electrode (of Bothe) for the device of Palacios in order to make a plurality of transistor unit cells (Bothe; ¶0095) with a reduced distance between adjacent source contacts (Bothe; ¶0097), thereby increasing device density.
Claims 3-8, and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Palacios in view of Koichi Tamura (JP 2011254058 A; hereinafter Tamura; paragraph numbers provided with the provided NPL translation document).
Regarding Claim 3, Palacios discloses the semiconductor device according to claim 1, but is silent regarding the details of the channel region 6 (which comprises multiple layers; ¶0042) further comprising:
a first carrier supply layer formed between the source electrode (12) and the channel layer (of 6);
a first barrier layer made of a compound semiconductor and formed between the source electrode (12) and the channel layer (of 6);
a second carrier supply layer formed between the drain electrode (4) and the channel layer (of 6); and
a second barrier layer made of a compound semiconductor and formed between the drain electrode (4) and the channel layer (of 6).
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In the same field of endeavor, Tamura discloses a channel region of a semiconductor field effect transistor structure (see annotated Fig. 1) that can reduce channel resistance. The channel region comprising a channel layer (14; ¶0018); with a first barrier layer (15; wherein the “spacer layer” is a barrier layer as described in ¶0014, ¶0037) made of a compound semiconductor (¶0037) and a first carrier supply layer (16; ¶0037) formed on one side (top) of the channel layer (14); and a second barrier layer (13; ¶0014 and ¶0037) made of a compound semiconductor (¶0037) and a second carrier supply layer (12; ¶0037) formed on the opposite side (bottom) of the channel layer (14).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the channel region structure (above) of Tamura for the channel region (6) of Palacios in order to reduce the channel resistance (as described in Tamura ¶0042 and throughout the specification). This would result in the first carrier supply layer (Tamura; 16) and the first barrier layer (Tamura; 15) between the source electrode (Palacios; 12) and the channel layer (Tamura; 14), and the second carrier supply layer (Tamura; 12) and second barrier layer (Tamura; 13) between the drain electrode (Palacios; 4) and the channel layer (Tamura; 14).
Regarding Claim 4, modified Palacios teaches the semiconductor device according to claim 3, but does not expressly disclose the configuration wherein the source electrode (12) is formed on the back surface of the substrate (1), and the first carrier supply layer (Tamura; 16) and the first barrier layer (Tamura; 15) are formed between the substrate (1) and the channel layer (Tamura; 14).
However, Palacios discloses in ¶0039 that the bottom electrode can alternatively be a source electrode instead of being the exemplified drain electrode.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to change the configuration of the source electrode being on the back surface of the substrate because Palacios describes them as suitable alternatives for the disclosed purpose of being a functioning transistor. This would result in the source electrode (12) being formed on the back surface of the substrate (1), and the first carrier supply layer (Tamura; 16) and the first barrier layer (Tamura; 15) are formed between the substrate (1) and the channel layer (Tamura; 14).
Furthermore, Applicant has not presented persuasive evidence that the claimed configuration is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed configuration). Also, the Applicant has not shown that the claimed configuration produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art., it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to re-arrange the locations of the source and drain electrodes (and respective carrier supply and barrier layers) with a reasonable expectation of success since it has been held that rearranging parts of an invention involves only routine skill in the art, and in view of Palacios description acknowledging the equivalent and alternate arrangements. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950), see MPEP 2144.04 VI.
Regarding Claim 5, modified Palacios teaches the semiconductor device according to claim 3, wherein the drain electrode (4) is formed on the back surface of the substrate (1), and the second carrier supply layer (Tamura; 12) and the second barrier layer (Tamura; 13) are formed between the substrate (1) and the channel layer (Tamura; 14) (as modified by Tamura).
Regarding Claim 6, modified Palacios teaches the semiconductor device according to claim 5, wherein
the source electrode (12), the first carrier supply layer (Tamura; 16), and the first barrier layer (Tamura; 15) are formed on the side of the substrate (1) of the channel layer (Tamura; 14),
the first carrier supply layer (Tamura; 16) and the second carrier supply layer (Tamura; 12) are integrally formed (this is implicitly satisfied as being the same structural configuration as the instant application), and
the first barrier layer (Tamura; 15) and the second barrier layer (Tamura; 13) are integrally formed (this is implicitly satisfied as being the same structural configuration as the instant application) (Furthermore, these are merely product-by-process limitation(s) that do not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966. MPEP 2113 I).
Regarding Claim 7, modified Palacios teaches the semiconductor device according to claim 6, further comprising: a third carrier supply layer (Tamura; part of the first carrier supply layer, commensurate in scope with Applicant’s “first, second, and third carrier supply layer” of Fig. 2 wherein a single layer is interpreted as two carrier supply layers) formed between the channel layer (Tamura; 14) and the gate electrode (14).
Regarding Claim 8, modified Palacios teaches the semiconductor device according to claim 3, further comprising:
a first contact layer (11) made of a compound semiconductor (¶0045) and formed between the source electrode (12) and the first barrier layer (Tamura; 15); and
a second contact layer (3) made of a compound semiconductor (¶0036) and formed between the drain electrode (4) and the second barrier layer (Tamura; 13),
wherein the source electrode (12) is formed in ohmic contact with the first contact layer (11) (¶0045), and
the drain electrode (4) is formed in ohmic contact with the second contact layer (3)(¶0036).
Regarding Claim 10, modified Palacios teaches the semiconductor device according to claim 4, further comprising:
a first contact layer (3) made of a compound semiconductor (¶0036) and formed between the source electrode (4) and the first barrier layer (Tamura; 15); and
a second contact layer (11) made of a compound semiconductor (¶0045) and formed between the drain electrode (12) and the second barrier layer (Tamura; 13),
wherein the source electrode (4) is formed in ohmic contact with the first contact layer (3) (¶0036), and
the drain electrode (12) is formed in ohmic contact with the second contact layer (11)(¶0045).
Regarding Claim 11, modified Palacios teaches the semiconductor device according to claim 5, further comprising:
a first contact layer (11) made of a compound semiconductor (¶0045) and formed between the source electrode (12) and the first barrier layer (Tamura; 15); and
a second contact layer (3) made of a compound semiconductor (¶0036) and formed between the drain electrode (4) and the second barrier layer (Tamura; 13),
wherein the source electrode (12) is formed in ohmic contact with the first contact layer (11) (¶0045), and
the drain electrode (4) is formed in ohmic contact with the second contact layer (3)(¶0036).
Regarding Claim 12, modified Palacios teaches the semiconductor device according to claim 6, further comprising:
a first contact layer (11) made of a compound semiconductor (¶0045) and formed between the source electrode (12) and the first barrier layer (Tamura; 15); and
a second contact layer (3) made of a compound semiconductor (¶0036) and formed between the drain electrode (4) and the second barrier layer (Tamura; 13),
wherein the source electrode (12) is formed in ohmic contact with the first contact layer (11) (¶0045), and
the drain electrode (4) is formed in ohmic contact with the second contact layer (3)(¶0036).
Regarding Claim 13, modified Palacios teaches the semiconductor device according to claim 7, further comprising:
a first contact layer (11) made of a compound semiconductor (¶0045) and formed between the source electrode (12) and the first barrier layer (Tamura; 15); and
a second contact layer (3) made of a compound semiconductor (¶0036) and formed between the drain electrode (4) and the second barrier layer (Tamura; 13),
wherein the source electrode (12) is formed in ohmic contact with the first contact layer (11) (¶0045), and
the drain electrode (4) is formed in ohmic contact with the second contact layer (3)(¶0036).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Palacios in view of Bothe and Tamura.
Regarding Claim 9, modified Palacios teaches the semiconductor device according to claim 2, but is silent regarding the details of the channel region 6 (which comprises multiple layers; ¶0042) further comprising:
a first carrier supply layer formed between the source electrode (12) and the channel layer (of 6);
a first barrier layer made of a compound semiconductor and formed between the source electrode (12) and the channel layer (of 6);
a second carrier supply layer formed between the drain electrode (4) and the channel layer (of 6); and
a second barrier layer made of a compound semiconductor and formed between the drain electrode (4) and the channel layer (of 6).
In the same field of endeavor, Tamura discloses a channel region of a semiconductor field effect transistor structure (see annotated Fig. 1) that can reduce channel resistance. The channel region comprising a channel layer (14; ¶0018); with a first barrier layer (15; wherein the “spacer layer” is a barrier layer as described in ¶0014, ¶0037) made of a compound semiconductor (¶0037) and a first carrier supply layer (16; ¶0037) formed on one side (top) of the channel layer (14); and a second barrier layer (13; ¶0014 and ¶0037) made of a compound semiconductor (¶0037) and a second carrier supply layer (12; ¶0037) formed on the opposite side (bottom) of the channel layer (14).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the channel region structure (above) of Tamura for the channel region (6) of Palacios in order to reduce the channel resistance (as described in Tamura ¶0042 and throughout the specification). This would result in the first carrier supply layer (Tamura; 16) and the first barrier layer (Tamura; 15) between the source electrode (Palacios; 12) and the channel layer (Tamura; 14), and the second carrier supply layer (Tamura; 12) and second barrier layer (Tamura; 13) between the drain electrode (Palacios; 4) and the channel layer (Tamura; 14).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Palacios.
Regarding Claim 15, Palacios discloses the semiconductor device according to claim 14, but does not expressly disclose wherein the source electrode is formed only on the back surface of the substrate.
However, Palacios discloses in ¶0039 that the bottom electrode can alternatively be a source electrode instead of being the exemplified drain electrode.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to change the configuration of the source electrode being on the back surface of the substrate because Palacios describes them as suitable alternatives for the disclosed purpose of being a functioning transistor. This would result in the source electrode (12) being formed on the back surface of the substrate (1), and the first carrier supply layer (Tamura; 16) and the first barrier layer (Tamura; 15) are formed between the substrate (1) and the channel layer (Tamura; 14).
Furthermore, Applicant has not presented persuasive evidence that the claimed configuration is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed configuration). Also, the Applicant has not shown that the claimed configuration produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art., it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to re-arrange the locations of the source and drain electrodes (and respective carrier supply and barrier layers) with a reasonable expectation of success since it has been held that rearranging parts of an invention involves only routine skill in the art, and in view of Palacios description acknowledging the equivalent and alternate arrangements. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950), see MPEP 2144.04 VI.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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