DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Claims 11-12, 14-15 and 17-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/6/2026. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. The term “ gradually ” in claim s 1, 2, 4 and 6 is a relative term which renders the claim indefinite. The term “ gradually ” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “gradually” is used in claims 1-2 in relation to changing capacitance values. The claims do not include any particular figure of merit, such as percent change or difference in units of measure (i.e. Farads), to distinguish between ‘gradual’ and ‘abrupt’. Therefore, any change in capacitance value could be considered ‘gradual’. Similarly, the term “gradually” is used in claims 4 and 6 in relation to an amount of electrode plate overlap. These claims do not particularly define the amount of change, either in percentage or raw magnitude, necessary to be considered ‘gradual’. Therefore, the term “gradually” renders claims 1, 2, 4 and 6 indefinite, since one of ordinary skill in the art would not be reasonably apprised of the scope of the invention . For the purposes of compact prosecution, the Examiner has interpreted the claims as follows: Claim 1: ‘… capacitance values change gradually in storage capacitors ( Cst ) of respective ones of the pixel driving circuits …” Claim 2: “… the capacitance values decrease gradually in the storage capacitors of the respective ones of the pixel driving circuits …” Claim 4: “… the total overlapping areas of the electrode plates decrease gradually in the storage capacitors …” Claim 6: “… the second overlapping areas and the third overlapping areas decrease gradually in the storage capacitors …’ Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim s 1-3 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Bae et al. ( PG Pub. No. US 2020/0312934 A1) in view of Zhao et al. ( PG Pub. No. US 2020 / 0219443 A1 ) . Regarding claim 1 , Bae teaches a display panel (¶ 0004), comprising a display region (DA) and a peripheral region (PA) surrounding the display region (¶ 0144 , fig. 18 ); wherein a binding region ( ¶ 01 67 : 150 and/or PCB ) is provided on a side of the peripheral region (fig. 20) ; the display region comprises a first display region ( ¶ 0 065 : A 2 ) and a second display region (A 1 ) adjacent to each other (fig. 17 among others : A2 adjacent to A1 ); a light transmittance of the second display region is greater than a light transmittance of the first display region (¶ 0 067 : region A2 includes a metal layer ML, such that light transmittance in region A1 higher than that of A2 ); the display panel further comprises a plurality of pixel driving circuits (¶ 01 71 : PC ) and data leads ( ¶ 0168: data line DL and/or connection line 151 ) for loading data voltages to the pixel driving circuits (¶ 0168 & fig s . 20 -21 : DL/151 loads data to PC ) ; and in the second display region, storage capacitors ( Cst ) of respective ones of the pixel driving circuits (are) sequentially connected to a same one of the data leads ( ¶ 0083, fig. 21: capacitor Cst of each respective PC connected to DL through transistor T2). Bae does not teach the capacitance values of the storage capacitors change . Zhao teaches a display panel ( Abstract ) including storage capacitors ( ¶ 0027: C1 ) of respective ones of the pixel driving circuits ( ¶ 0009: drive TFT ) sequentially connected to a same data lead (¶ 0026 & fig. 2: plurality of C1 of respective subpixels 10 connected in a row to same lead 20 and/or connected in a column to same lead 30), wherein the capacitance values of the storage capacitors change (¶¶ 0012-0013: capacitance value of the storage capacitor of each of the subpixels in the same row and/or column increases and/or decreases). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the storage capacitors of Bae with the value change of Zhao, as a means to improv e the uniformity of the display scree n (Zhao, ¶ 0017). Regarding claim 2 , Bae in view of Zhao teaches t he display panel according to claim 1, wherein, along a direction away from the binding region, the capacitance values decrease gradually in the storage capacitors of the respective ones of the pixel driving circuits located in the second display region and connected to the same one of the data leads (Bae, fig. 20: along a direction away from 150, Cst in each pixel ‘P’, as modified with the changing capacitance values of Zhao, decrease) . Regarding claim 3 , Bae in view of Zhao teaches t he display panel according to claim 1, wherein the display panel further comprises scanning leads (Bae, ¶ 0166: scan line SL) for loading scanning signals to the pixel driving circuits (Bae, fig. 20: SL connected to pixel circuit PC ) ; and in the second display region, capacitance values are the same in storage capacitors of respective ones of the pixel driving circuits sequentially connected to a same one of the scanning leads (Zhao, ¶ 0031 & fig. 2: at least outermost storage capacitors C1 connected to scanning lines 20 include same capacitance values) . Regarding claim 8 , Bae in view of Zhao teaches t he display panel according to claim 1, wherein the display panel further comprises pixel driving regions for providing the pixel driving circuits (Bae, ¶ 0171 & fig s . 20 -21 : pixels P provide pixel circuits PC ) ; and an area of a pixel driving region in the second display region is smaller than an area of a pixel driving region in the first display region (Bae, fig. 17 : area A2 has additional layer ML, such that A1 has a smaller vertical dimension and resulting area than A2) . Regarding claim 9 , Bae in view of Zhao teaches t he display panel according to claim 8, wherein the display panel further comprises signal lines ( Bae, ¶ 0167: PL) for connecting adjacent ones of the pixel driving circuits ( Bae, figs. 20-21: PL connects pixel circuits PC of adjacent pixels P) ; and in the second display region, a material of a part of the signal lines outside the pixel driving region is a transparent conductive material (¶ 0096: pixel electrodes, including portions outside of PC regions, include transparent material such as ITO, IZO, ZnO , andIn 2 O 3 ). Regarding claim 10 , Bae in view of Zhao teaches t he display panel according to claim 8, wherein the display panel further comprises a base substrate (Bae, ¶ 0065: 100) , a semiconductor layer (Bae, ¶ 0068: Act1/Act2) , a first gate layer (Bae, ¶ 0077: G1) , a second gate layer (Bae, ¶ 0077: G 2 ), a first source-drain metal layer (Bae, ¶ 0092: SE1) , a second source-drain metal layer (Bae, ¶ 0092: D E 1 ) and a pixel electrode layer (Bae, ¶ 0095: 221) sequentially stacked (Bae, fig. 7) ; the display panel further comprises a transparent wiring layer (Bae, ¶ 0094 & fig. 7: contact of 221 formed in CNT3 of layer 209) located between any two adjacent ones of the semiconductor layer, the first gate layer, the second gate layer, the first source-drain metal layer, the second source-drain metal layer and the pixel electrode layer (Bae, fig. 7: CNT3 located between at least 221 and SE1/DE1) ; and in the second display region, a part of the signal lines outside the pixel driving region is located in the transparent wiring layer (Bae, ¶ 0173 & fig. 20) . Allowable Subject Matter Claims 4-7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating: “ odd-numbered layers of the electrode plates are electrically connected to each other, and even-numbered layers of the electrode plates are electrically connected to each other; two adjacent layers of the electrode plates overlap and are electrically insulated with each other; a total overlapping area of the electrode plates of the storage capacitor is equal to a sum of overlapping areas between any two adjacent layers of the electrode plates ” as recited in claim 4 . Claims 5-7 depend on claim 4, and are allowable for the same reasons. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sun et al. ( US 2006 / 0273994 A1 ) teaches a display panel with decreasing storage capacitor values across a pixel array (¶ 0023). Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT BRIAN TURNER whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-5411 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 8am-5pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRIAN TURNER/ Examiner, Art Unit 2818