Prosecution Insights
Last updated: April 19, 2026
Application No. 18/563,120

LEAD BONDING STRUCTURE COMPRISING EMBEDDED MANIFOLD TYPE MICRO-CHANNEL AND PREPARATION METHOD FOR LEAD BONDING STRUCTURE

Non-Final OA §102§103
Filed
Nov 21, 2023
Examiner
QUINTO, KEVIN V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Peking University
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
86%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
710 granted / 837 resolved
+16.8% vs TC avg
Minimal +1% lift
Without
With
+1.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
31 currently pending
Career history
868
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
47.7%
+7.7% vs TC avg
§102
34.0%
-6.0% vs TC avg
§112
14.4%
-25.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 837 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 5-10, 13, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ma et al. (CN 111769087 A, hereinafter “Ma”). In reference to claim 1, Ma discloses a structure which meets the claim. Fig. 1-12 of Ma discloses a wire bonding structure with an embedded manifold type micro-channel such that the wire bonding structure comprises a chip (000) comprising a substrate (000) and an embedded micro-channel (011) located on a back portion of the substrate (000). There is an interposer (130), comprising a manifold channel (118), a liquid inlet (113b, 210a), and a liquid outlet (114b, 210b). There is a low-temperature sealing layer (136) configured to hermetically communicate the embedded micro-channel (011) with the manifold channel (118). The low-temperature sealing layer (136) is located between the chip (000) and the interposer (130). There is a bonding wire (note various unlabeled wires) configured to electrically connect the chip (000) to the interposer (130). With regard to claim 2, the manifold channel (118) comprises an inflow channel (114a) and an outflow channel (113a). In reference to claim 5, Ma discloses that the low-temperature sealing layer (136) is a metal layer (see p. 10 of attached machine translation). With regard to claim 6, Ma discloses that the low-temperature sealing layer (136) is a metal layer (see p. 10 of attached machine translation). In reference to claim 7, the low-temperature sealing layer (136) is a metal layer which comprises Cu, Sn, Au, and Ag (see p. 10 of attached machine translation). The examiner notes the claimed deposition methods for the metal layer. However this places the claim into the form of a product-by-process claim: Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Thorpe, 227 USPQ 964, 966; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law makes clear. See also MPEP 2113. Claim 7 is not patentable over Ma regardless of the process used to form the metal layer, because only the final product is relevant, and not the process of making such as physical or chemical vapor deposition processes or electroplating with a low-temperature eutectic bonding process. With regard to claim 8, the low-temperature sealing layer (136) is a metal layer which comprises Cu, Sn, Au, and Ag (see p. 10 of attached machine translation). The examiner notes the claimed deposition methods for the metal layer. However this places the claim into the form of a product-by-process claim: Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Thorpe, 227 USPQ 964, 966; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law makes clear. See also MPEP 2113. Claim 8 is not patentable over Ma regardless of the process used to form the metal layer, because only the final product is relevant, and not the process of making such as chemical or physical vapor deposition processes or electroplating with a low-temperature eutectic bonding process. In reference to claim 9, Ma discloses a method which meets the claim. Fig. 1-12 of Ma discloses a preparation method of a wire bonding structure with an embedded manifold type micro-channel which comprises providing a chip (000). An embedded micro-channel located (011) is manufactured on a back portion of the chip (000). An interposer (130) is prepared with a manifold channel (118), a liquid inlet (113b, 210a), and a liquid outlet (114b, 210b). A low-temperature sealing layer (136) is formed between the chip (000) and the interposer (130) to hermetically communicate the embedded micro-channel (011) with the manifold channel (118). The low-temperature sealing layer (136) is located between the chip (000) and the interposer (130). The chip (000) is connected with the interposer (130) through a bonding wire (note various unlabeled wires) to achieve electrical connection between them. With reference to claim 10, the chip (000) is in a wafer state (p. 9 of the attached machine translation). In reference to claim 13, Ma discloses (p. 10 of the attached machine translation) the use of binding agents/layers in the form of BCB or a glass slurry for the low-temperature sealing layer (136). It is understood that these materials are cured in order to properly seal the manifold channel (118). With regard to claim 14, Ma discloses (p. 10 of the attached machine translation) the use of binding agents/layers in the form of BCB or a glass slurry for the low-temperature sealing layer (136). It is understood that these materials are cured in order to properly seal the manifold channel (118). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Chrysler et al. (United States Patent Application Publication No. US 2005/0151244 A1, hereinafter “Chrysler”). In reference to claim 3, Ma does not disclose that the inflow channel and the outflow channel are both in a shape of comb teeth. However fig. 1 of Chrysler discloses the use of microchannels (114) with cooling fins/walls (113) that have a comb teeth shape. Chrysler discloses that such a shape greatly increases the surface area which provide the benefit of enhanced heat transfer (p. 2, paragraph 20, p. 3, paragraph 33). In view of Chrysler, it would therefore be obvious to implement the inflow channel and the outflow channel of Ma with surfaces in the shape of comb teeth. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Hsu (United States Patent Application Publication No. US 2006/0115931 A1, hereinafter “Hsu”). In reference to claim 4, Ma does not disclose that the interposer material (130 – fig. 1-12) is a printed circuit board (PCB). However Hsu discloses that printed circuit boards have the benefit of low cost (p. 1, paragraph 2). In view of Hsu, it would therefore be obvious to form the interposer disclosed by Ma with a printed circuit board material. Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Hsu and further in view of Kwong (USPN 6,445,591 B1, hereinafter “Kwong”). In reference to claim 11, Ma does not disclose that the interposer material (130 – fig. 1-12) is a printed circuit board (PCB). However Hsu discloses that printed circuit boards have the benefit of low cost (p. 1, paragraph 2). In view of Hsu, it would therefore be obvious to form the interposer disclosed by Ma with a printed circuit board material. Ma does not explicitly disclose that the manifold channel (118), liquid inlet (113b, 210a), and liquid outlet (114b, 210b) in fig. 1-12 are etched by laser machining. However Kwong discloses that etching by laser machining provides the benefit of precision etching (column 8, lines 33-39). In view of Kwong, it would therefore be obvious to form the manifold channel, liquid inlet, and liquid outlet in the method of Ma constructed in view of Hsu by laser machining. With regard to claim 12, Ma does not disclose that the interposer material (130 – fig. 1-12) is a printed circuit board (PCB). However Hsu discloses that printed circuit boards have the benefit of low cost (p. 1, paragraph 2). In view of Hsu, it would therefore be obvious to form the interposer disclosed by Ma with a printed circuit board material. Ma does not explicitly disclose that the manifold channel (118), liquid inlet (113b, 210a), and liquid outlet (114b, 210b) in fig. 1-12 are etched by laser machining. However Kwong discloses that etching by laser machining provides the benefit of precision etching (column 8, lines 33-39). In view of Kwong, it would therefore be obvious to form the manifold channel, liquid inlet, and liquid outlet in the method of Ma constructed in view of Hsu by laser machining. Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Hsieh et al. (United States Patent Application Publication No. US 2004/0102028 A1, hereinafter “Hsieh”) and as further evidenced by Ehmke et al. (United States Patent Application Publication No. US 2017/0283255 A1, hereinafter “Ehmke”). In reference to claim 15, Ma discloses that the low-temperature sealing layer (136) is formed by plating a metal layer which comprises Au/Sn (see p. 10 of attached machine translation). Ehmke discloses that Au/Sn is a known low temperature eutectic bonding material (p. 1, paragraph 12). Thus Ma discloses that the low-temperature sealing layer (136) is formed by a plating process combined with a low-temperature eutectic bonding process. Ma does not disclose that the plating process is done by electroplating. However Hsieh discloses that electroplating has the advantages of low cost, a simple equipment requirement, and fast deposition speed (p. 2, paragraph 22). In view of Hsieh, it would therefore be obvious to use electroplating in the method disclosed by Ma. With regard to claim 16, Ma discloses that the low-temperature sealing layer (136) is formed by plating a metal layer which comprises Au/Sn (see p. 10 of attached machine translation). Ehmke discloses that Au/Sn is a known low temperature eutectic bonding material (p. 1, paragraph 12). Thus Ma discloses that the low-temperature sealing layer (136) is formed by a plating process combined with a low-temperature eutectic bonding process. Ma does not disclose that the plating process is done by electroplating. However Hsieh discloses that electroplating has the advantages of low cost, a simple equipment requirement, and fast deposition speed (p. 2, paragraph 22). In view of Hsieh, it would therefore be obvious to use electroplating in the method disclosed by Ma. In reference to claim 17, Ma discloses that the low-temperature sealing layer (136) is formed of a metal material which comprises Au and Sn (see p. 10 of attached machine translation). With regard to claim 18, Ma discloses that the low-temperature sealing layer (136) is formed of a metal material which comprises Au and Sn (see p. 10 of attached machine translation). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEVIN QUINTO/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Nov 21, 2023
Application Filed
Feb 07, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
86%
With Interview (+1.4%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 837 resolved cases by this examiner. Grant probability derived from career allow rate.

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