Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 5/25/26 has been entered.
Terminal Disclaimer
The terminal disclaimer filed on 5/25/26 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of any patent granted on Application Number 18/569751 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Response to Arguments
Regarding claims 1, 3-4 and 11-12. Applicant’s arguments with regard to the amendment have been fully considered but they are moot because the arguments do not apply to any of the references being used in the current rejection.
Regarding claim 10. Applicant's arguments regarding claim 10 are not persuasive because they are directed to Eriksson, whereas claim 10 is rejected under 35 U.S.C. § 102(a)(1) as anticipated by Schenkel. Applicant does not identify any alleged deficiency in Schenkel's disclosure of the limitations of claim 10. Accordingly, the rejection of claim 10 is maintained.
Claim Objections
The objections to the claims set forth in the previous Office Action are repeated and maintained because applicant has not addressed the noted informalities. Appropriate correction is required.
Claim 1 is objected to because of the following informalities: the “the third direction (z)” should be “the third direction
Claim 6 is objected to because of the following informalities: the “di-rection (x)” should be “direction”.
Claim 10 is objected to because of the following informalities: the “direction (x)” in line 10 should be “direction
Claim 10 is further objected to because of the following informalities: the “step b)” in line 10 should be “the b)” as antecedently recited in line 5.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schenkel (US 20130087766, which is in the IDS on 11/29/23).
Regarding claim 10. Schenkel discloses A method for manufacturing a qubit element (Fig 2, [0021]), comprising:
a) providing a wafer 170 [0021] and an insulation layer 115 of silicon dioxide ([0018]: SiO2) on a surface (top surface of 170) of the wafer;
b) etching a recess by:
b1) growing a quantum well structure directly or indirectly onto the insulation layer ([0027]: 28SOI (isotopically enriched Silicon-28 on insulator) for donor-dot device fabrication, the process of growing a 28Si enriched epi-layer onto a natural silicon device layer—which is part of a Silicon-on-Insulator (SOI) wafer—means indirectly growing a quantum well structure on the insulation layer),
wherein a quantum well is formed within the quantum well structure along a first direction (x) ([0024]: “quantum dots with a high degree of control have also been demonstrated in... Si--SiGe hetero-structures” which means the creation of a 2D electron system (a quantum well)); and
b2) locally etching the wafer on a side of the wafer opposite the insulation layer such that a recess is formed in the wafer ([0021]: etching vias in the silicon substrate 170); and
c) disposing a backgate 130 within the recess etched according to step b) ([0021]: Back gates 130 may be formed by etching vias in the silicon substrate 170, followed by deposition of conductive electrodes).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5 and 11-12 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Eriksson (US 20020179897; hereinafter "Eriksson-897") in view of Eriksson (US 20150279981; hereinafter "Eriksson-981").
Regarding claim 1. (Currently Amended) Figures 1 (plan view) and 3 (cross-sectional view taken along line 2-2 of Fig. 1) of Eriksson-897 disclose a qubit element comprising:
a quantum well structure (heterostructure 31) within which a quantum well 44 is formed along a first direction (vertical direction) (Fig. 3; ¶[0035]);
an electrode arrangement including electrodes 32 and 33 (Figs. 1 and 3; ¶[0038]) arranged spaced apart from the quantum well structure in the first direction and adapted to restrict movement of a charge carrier in the quantum well in and against a second direction and in and against a third direction, thereby forming quantum dots 36 and 37. Eriksson-897 teaches that the heterostructure provides confinement perpendicular to the layers (the first direction), while electrodes 32 and 33 provide lateral confinement within the quantum well to define the quantum dots, thereby restricting movement of charge carriers in two mutually perpendicular lateral directions.
wherein the first direction, the second direction, and the third direction are respectively perpendicular to each other in pairs, as the quantum well provides confinement perpendicular to the layer structure while the gate electrodes provide confinement in two mutually perpendicular lateral directions.
a backgate 41 arranged spaced apart from the quantum well structure against the first direction (Fig. 3).
However, Eriksson-897 does not disclose the particular structural arrangement of an insulating layer disposed between the backgate and the quantum well structure, wherein the quantum well structure is disposed on the insulating layer such that the backgate is arranged adjacent to the insulating layer and electrically insulated from the quantum well structure.
Eriksson-981 teaches a quantum semiconductor device including a fifth quantum heterostructure 902 comprising back gate layer 906, first tunnel barrier layer 908, and quantum well layer 910 (Fig. 9; ¶¶[0077]-[0078]). Eriksson-981 teaches that the back gate layer 906 is disposed adjacent to the first tunnel barrier layer 908, the first tunnel barrier layer 908 is formed of SiO₂, and the quantum well layer 910 is disposed on the first tunnel barrier layer. Thus, the SiO₂ tunnel barrier layer is positioned between the back gate layer and the quantum well layer, electrically insulating the back gate layer from the quantum well layer while supporting the quantum well layer. Eriksson-981 further describes the quantum well layer as being formed on the first tunnel barrier layer (claim 17), consistent with the structural arrangement illustrated in Fig. 9 and described in ¶¶[0077]-[0078].
Accordingly, Eriksson-981 teaches the claimed arrangement of an insulating layer disposed between the backgate and the quantum well structure, with the quantum well structure disposed on the insulating layer.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the qubit element of Eriksson-897 by incorporating the backgate/insulating-layer architecture taught by Eriksson-981 such that an insulating layer is disposed between the backgate and the quantum well structure with the quantum well structure disposed on the insulating layer. One of ordinary skill in the art would have been motivated to make this modification because Eriksson-981 recognizes that interposing an insulating SiO₂ layer between the backgate and the quantum well electrically insulates the backgate from the quantum well while maintaining electrostatic control of charge carriers within the quantum well. Incorporating this known architecture into the qubit element of Eriksson-897 would have predictably improved electrical isolation of the backgate while preserving effective electrostatic control of the quantum well, thereby yielding no more than the predictable use of prior-art elements according to their established functions.
Regarding claim 2. (Previously Amended) Eriksson-897 in view of Eriksson-981 discloses The qubit element according to claim 1, Eriksson-897 further comprising a base layer 42 formed from strained silicon (Fig 3: the bottom barrier (or buffer layer), which serves as the foundational, epitaxial base layer upon which the quantum well is grown) and arranged between the quantum well structure and the backgate (Fig 3).
Regarding claim 3 (Previously Amended), Eriksson-897 in view of Eriksson-981 discloses the qubit element according to claim 2, further comprising an insulation layer of silicon dioxide abutting the base layer on a side of the base layer opposite the quantum well structure. As discussed above with respect to claim 1, Eriksson-981 teaches a first tunnel barrier layer 908 formed of silicon dioxide (SiO₂) disposed between the back gate layer 906 and the quantum well layer 910 (Fig. 9; ¶¶[0077]-[0078]). It would have been obvious to incorporate the SiO₂ insulation layer of Eriksson-981 into the modified structure of Eriksson-897 such that the SiO₂ insulation layer is disposed adjacent to and abuts the lower surface of the base layer between the base layer and the backgate, thereby providing electrical insulation while maintaining electrostatic coupling.
Regarding claim 5 (Previously Amended), Eriksson-897 in view of Eriksson-981 discloses the qubit element according to claim 1. Eriksson-897 further discloses that the quantum well structure comprises three layers following one another in a first direction, namely lower barrier layer 42, quantum well layer 44, and upper barrier layer 47 (Fig. 3). Eriksson-897 teaches that lower barrier layer 42 and upper barrier layer 47 are silicon-germanium (SiGe) barrier layers, while quantum well layer 44 is a silicon layer (¶¶[0035]-[0036]). Eriksson-897 further teaches that the silicon quantum well is grown pseudomorphically between relaxed SiGe barrier layers (¶[0062]), thereby forming a strained silicon quantum well. Accordingly, Eriksson-897 teaches a quantum well structure having three layers following one another in the first direction, of which a middle layer of the three layers is formed from strained silicon, and the two remaining layers are formed from silicon-germanium (SiGe).
Regarding claim 11. (Currently Amended) Eriksson-897 discloses a method for operating a qubit element comprising a quantum well structure (heterostructure 31) within which a quantum well 44/45 is formed along a first direction (Figs. 1 and 2; ¶¶[0035], [0037]). Eriksson-897 further discloses an electrode arrangement (surface gates 32 and 33) arranged spaced apart from the quantum well structure in the first direction and adapted to electrostatically restrict movement of charge carriers within the quantum well in order to form quantum dots 36 and 37 (Figs. 1 and 2; ¶¶[0037]-[0038]). The first direction is perpendicular to the lateral directions in which the surface gates provide confinement, such that the first, second, and third directions are respectively perpendicular to each other in pairs. Eriksson-897 further discloses a backgate 41 arranged spaced apart from the quantum well structure against the first direction (Fig. 2).
Eriksson-897 further teaches the method comprising applying electrical voltages to the electrode arrangement such that a quantum dot is formed in the quantum well of the quantum well structure. Specifically, Eriksson-897 teaches that the surface gates 32 and 33 operate as field-effect transistor gates to provide lateral confinement of electrons within the quantum well, thereby defining quantum dots 36 and 37 (¶¶[0037]-[0038]). One of ordinary skill in the art would have understood that operation of field-effect transistor gates necessarily involves applying electrical voltages to the gates to electrostatically define the quantum dots.
However, Eriksson-897 does not disclose an insulation layer onto which the quantum well structure is directly or indirectly grown, wherein the backgate is arranged adjacent to the insulation layer and spaced apart from the quantum well structure against the first direction, and wherein the backgate is electrically insulated from the quantum well structure.
Eriksson-981 discloses a fifth heterostructure 902 including a backgate layer 906, a first tunnel barrier layer 908 comprising silicon dioxide (SiO₂), and a quantum well layer 910, wherein the quantum well layer is formed on the first tunnel barrier layer, the backgate layer is arranged adjacent to the first tunnel barrier layer, and the first tunnel barrier layer electrically insulates the backgate layer from the quantum well layer (Fig. 9; ¶¶[0077]-[0078]; claim 17). Accordingly, Eriksson-981 teaches an insulation layer onto which the quantum well structure is directly or indirectly grown, a backgate arranged adjacent to the insulation layer and spaced apart from the quantum well structure against the first direction, wherein the backgate is electrically insulated from the quantum well structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of operating the qubit element disclosed by Eriksson-897 to employ the backgate/insulating-layer architecture taught by Eriksson-981. One of ordinary skill in the art would have been motivated to do so because Eriksson-981 teaches that the insulating layer electrically separates the backgate from the quantum well while allowing electrostatic control of the quantum well. Incorporating this known backgate/insulating-layer architecture into the method of Eriksson-897 would have predictably provided electrical insulation between the backgate and the quantum well while maintaining effective electrostatic control of the quantum dot using known semiconductor device structures.
Regarding claim 12. (Previously Presented) Eriksson-897 in view of Eriksson-981 discloses The method according to claim 11, Eriksson-897 discloses further comprising implementing a qubit using a spin of a charge carrier in the quantum dot (([0037]: Eriksson-897 teaches this functional limitation, “The qubit in the device 30 is the spin of a single electron (or possibly several electrons) in the quantum dots 36 and 37”. The electron is a "charge carrier," and its "spin" is utilized as the quantum bit (qubit) through entanglement and manipulation (e.g., C-NOT gates). The operation involves "tun[ing] the spin-spin interaction" and performing "single qubit operation[s]." This matches the claimed method of implementing a qubit via the spin of a charge carrier in the dot).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Eriksson (US 20020179897; hereinafter "Eriksson-897") in view of Eriksson (US 2015/0279981; hereinafter "Eriksson-981"), and further in view of Schenkel (US 20130087766, which is in the IDS on 11/29/23).
Regarding claim 4. (Previously Amended) Eriksson-897 in view of Eriksson-981 discloses The qubit element according to claim 1, However, Eriksson-897 in view of Eriksson-981 does not disclose a wafer having a recess, wherein the backgate is arranged within the recess.
Schenkel (US 2013/0087766) discloses a quantum computing apparatus including a substrate (wafer) 170 and local back gates 130. Schenkel further teaches that the back gates 130 may be formed by etching vias in the silicon substrate 170 followed by deposition of conductive electrodes (Fig. 2; ¶[0021]). Accordingly, Schenkel teaches a wafer having recesses (etched vias), wherein the backgates are arranged within the recesses.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the qubit element of Eriksson-897, as modified by Eriksson-981, to incorporate the recessed backgate arrangement taught by Schenkel. One of ordinary skill in the art would have been motivated to do so because Schenkel teaches that local back gates formed in etched vias within the wafer provide localized electrostatic control of the quantum device, including control of the donor-quantum dot exchange coupling. Incorporating this known recessed backgate implementation into the qubit element of Eriksson-897, as modified by Eriksson-981, would have predictably provided a localized buried backgate structure capable of electrostatically controlling the quantum well while maintaining compatibility with conventional semiconductor fabrication techniques.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Eriksson (US 20020179897; hereinafter "Eriksson-897") in view of Eriksson (US 2015/0279981; hereinafter "Eriksson-981"), and further in view of in view of Pillarisetty (US 20200350423).
Regarding claim 6. Eriksson-897 in view of Eriksson-981 discloses The qubit element according to claim 1. However, Eriksson-897 in view of Eriksson-981 does not disclose further comprising a magnet arranged spaced apart from the quantum well structure against the first direction (x).
Fig 2 of Pillarisetty discloses a magnet 121 [0027] arranged spaced apart from the quantum well structure ([0028]: in 104) against the first direction (x).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Eriksson-897 in view of Eriksson-981’s device structure to have the Pillarisetty’s localized magnet line for the purpose of providing enhanced spin qubit control, enabling faster, more energy-efficient operation compared to global microwave fields. They facilitate long-range, selective entanglement between qubits via magnons and increase qubit stability by reducing sensitivity to environmental magnetic noise.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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