Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Abstract
The abstract of the disclosure is objected to because it is written in legal terminology which is too similar to claim language. In particular, legal phraseology such as the term “comprising”, “said” and “wherein” which are commonly used to define the limitations and scope pf patent claims, should generally be avoided in U.S. patent abstracts because the purpose of the abstract is not to define the patent claims, but to provide the reader with a clear and concise summary. The abstract should use plain language to describe the invention's technical problem, solution, and principal use.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. In particular, there is no place in a single paragraph abstract for element labels of drawings. Therefore, the label numbers in the present Abstract should be deleted. The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” etc. Correction is required. See MPEP § 608.01(b).
Claim Objections
Claim 1 is objected to because of the following informalities: the “the third direction (z)” should be “the third direction
Claim 6 is objected to because of the following informalities: the “di-rection (x)” should be “direction”.
Claim 10 is objected to because of the following informalities: the “direction (x)” in line 10 should be “direction
Claim 10 is further objected to because of the following informalities: the “step b)” in line 10 should be “the b)” as antecedently recited in line 5.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-2, 5 and 11-12 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-9 of copending Application No. 18569751 (reference application; hereinafter App-51) in view of Eriksson (US 20020179897).
Regarding claim 1, the claims 1 and 5 of App-51 disclose the claim 1. But the App-51 does not explicitly disclose an electrode arrangement arranged spaced apart from the quantum well structure.
Although App-51 does not specifically disclose an electrode arrangement arranged spaced apart from the quantum well structure, to the ordinary skilled in the art, the electrode arrangement is inherently designed to be spaced apart from the quantum well (QW) structure to prevent direct electrical contact, which can damage the delicate quantum states, or to allow for specific field-induced effects. For example, Fig 2 of Eriksson discloses an electrode 33 arrangement arranged spaced apart from the quantum well structure 44/45.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the claims 1 and 5 of App-51 to have the Eriksson’s device structure for the purpose of providing precise electrostatic confinement of electrons, essential for forming and manipulating single-electron spin qubits. Thereby enhancing uniformity of the potential landscape across arrays, reduction of defects and crosstalk, and increased stability for qubit operations.
Regarding claim 2, the claims 1 and 5 of App-51 in view of Eriksson disclose the claim 2. Eriksson discloses a base layer 42 formed from strained silicon (Fig 3: the bottom barrier (or buffer layer), which serves as the foundational, epitaxial base layer upon which the quantum well is grown) and arranged between the quantum well structure and the backgate (Fig 3).
Regarding claim 5, the claims 1 and 5 of App-51 in view of Eriksson disclose the claim 2. Eriksson discloses wherein the quantum well structure has three layers following one another in the first direction (Fig 3: 42/44/47), of which the middle layer 44 is formed from strained silicon (the SiGe layers 42 and 47 have a larger lattice constant than pure silicon, the middle Si layer is epitaxially grown and stretched (under tensile strain) to match the SiGe lattice), and of which the two remaining layers are respectively formed from silicon and germanium (Fig 3).
Regarding claim 11, the claim 11 of App-51 discloses the claim 11. But the App-51 does not explicitly disclose an electrode arrangement arranged spaced apart from the quantum well structure in the first direction; a backgate arranged spaced apart from the quantum well structure against the first direction.
However, Fig 2 of Eriksson discloses an electrode arrangement 32/33 (Fig 1/Fig 2) arranged spaced apart from the quantum well structure 44/45 in the first direction (vertical); a backgate 41 arranged spaced apart from the quantum well structure against the first direction.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the claim 11 of App-51 to have the Eriksson’s method for the purpose of providing precise electrostatic confinement of electrons, essential for forming and manipulating single-electron spin qubits. Thereby enhancing uniformity of the potential landscape across arrays, reduction of defects and crosstalk, and increased stability for qubit operations.
Regarding claim 12, the claims 11-12 of App-51 in view of Eriksson disclose the claim 12.
This is a provisional nonstatutory double patenting rejection.
Claim 10 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of copending Application No. 18569751 (reference application; hereinafter App-51) in view of Schenkel (US 20130087766, which is in the IDS on 11/29/23).
Regarding claim 10, the claim 10 of App-51 discloses the claim 10. The App-51 discloses ‘a base layer of strained silicon adjacent to the insulation layer’ and ‘providing a quantum well structure adjacent to the base layer’. Thus, it would have been obvious that ‘a quantum well structure’ at least ‘indirectly onto the insulation layer’. But the App-51 does not explicitly disclose the growing a quantum well structure.
However, Schenkel discloses growing a quantum well structure ([0027]: 28SOI (isotopically enriched Silicon-28 on insulator) for donor-dot device fabrication, the process of growing a 28Si enriched epi-layer onto a natural silicon device layer—which is part of a Silicon-on-Insulator (SOI) wafer—means indirectly growing a quantum well structure on the insulation layer).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the claim 10 of App-51 to have the Schenkel’s method for the purpose of providing high-performance qubit devices, specifically spin qubits and some superconducting architectures, due to their ability to create atomically smooth, low-disorder interfaces and, consequently, superior electron/hole confinement.
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 5 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 5, the claim recites the limitation “the middle layer” in line(s) 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation is interpreted as “a middle layer”.
Thus, the examiner recommends amending the limitation to “[[the]] a middle layer of the three layers”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5 and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eriksson (US 20020179897).
Regarding claim 1. Fig 1 (plan view) and Fig 3 (a sectional view of Fig 1 along 2-2) of Eriksson disclose A qubit element, comprising:
a quantum well structure (in the heterostructure 31) within which a quantum well 44 [0035] is formed along a first direction (vertical direction) (Fig 3);
an electrode arrangement 32/33 (Fig 1/Fig 3, [0038]) arranged spaced apart from the quantum well structure in the first direction and adapted to restrict a movement of a charge carrier in the quantum well in and against a second direction and in and against a third direction, in order to form a quantum dot (Eriksson teaches that while the heterostructure 31 provides confinement perpendicular to the layers (first direction), the gates 32 and 33 provide lateral confinement. The text clarifies that this lateral confinement restricts the movement of electrons (charge carriers) to form quantum dots 36 and 37. Restricting movement "laterally" inherently encompasses movement "in and against" two orthogonal axes (the second and third directions) within the plane of the quantum well),
wherein the first direction, the second direction and the third direction (z) are respectively perpendicular to each other in pairs (Eriksson describes a structure where confinement is provided "perpendicular to the layers" (z-axis/first direction) and "laterally" (x and y axes/second and third directions). In standard semiconductor fabrication as described (utilizing "standard lithography techniques"), the lateral gates define a horizontal plane that is perpendicular to the vertical growth axis of the heterostructure, thus satisfying the requirement that the three directions are perpendicular to each other in pairs); and
a backgate 41 arranged spaced apart from the quantum well structure against the first direction (Fig 3).
Regarding claim 2. Eriksson discloses The qubit element according to claim 1, further comprising a base layer 42 formed from strained silicon (Fig 3: the bottom barrier (or buffer layer), which serves as the foundational, epitaxial base layer upon which the quantum well is grown) and arranged between the quantum well structure and the backgate (Fig 3).
Regarding claim 5. Eriksson discloses The qubit element according to claim 1, wherein the quantum well structure has three layers following one another in the first direction (Fig 3: 42/44/47), of which the middle layer 44 is formed from strained silicon (the SiGe layers 42 and 47 have a larger lattice constant than pure silicon, the middle Si layer is epitaxially grown and stretched (under tensile strain) to match the SiGe lattice), and of which the two remaining layers are respectively formed from silicon and germanium (Fig 3) .
Regarding claim 11. Eriksson discloses A method for operating a qubit element [0046], the qubit element comprising a quantum well structure (in the heterostructure 31) (Fig 1), within which a quantum well 44/45 is formed along a first direction (vertical) (Fig 2),
an electrode arrangement 32/33 arranged spaced apart from the quantum well structure in the first direction and adapted to restrict a movement of a charge carrier in the quantum well in and against a second direction and in and against a third direction, in order to form a quantum dot (Fig 1/Fig 2: Eriksson teaches that while the heterostructure 31 provides confinement perpendicular to the layers (first direction), the gates 32 and 33 provide lateral confinement. The text clarifies that this lateral confinement restricts the movement of electrons (charge carriers) to form quantum dots 36 and 37. Restricting movement "laterally" inherently encompasses movement "in and against" two orthogonal axes (the second and third directions) within the plane of the quantum well),
wherein the first direction, the second direction and the third direction are respectively perpendicular to each other in pairs (Eriksson describes a structure where confinement is provided "perpendicular to the layers" (z-axis/first direction) and "laterally" (x and y axes/second and third directions). In standard semiconductor fabrication as described (utilizing "standard lithography techniques"), the lateral gates define a horizontal plane that is perpendicular to the vertical growth axis of the heterostructure, thus satisfying the requirement that the three directions are perpendicular to each other in pairs), and
a backgate 41 arranged spaced apart from the quantum well structure against the first direction (Fig 2),
the method comprising applying electrical voltages to the electrode arrangement such that a quantum dot is formed in the quantum well of the quantum well structure (Eriksson discloses the operation of this structure via voltage application. Paragraph [0038] describes the surface gates 32 and 33 as acting "like the gate of a field effect transistor." It further clarifies that a "quantum gate refers to... the physical series of voltage pulses applied to one qubit." Paragraph [0037] notes that these gates "provide lateral confinement" for electrons. In the field of semiconductor physics, "lateral confinement" via FET-style gates inherently requires the application of electrical potentials (voltages) to create the electrostatic barriers that define the quantum dot. Therefore, the Eriksson teaches applying voltages to form the dot).
Regarding claim 12. Eriksson discloses The method according to claim 11, further comprising implementing a qubit using a spin of a charge carrier in the quantum dot ([0037]: Eriksson teaches this functional limitation, “The qubit in the device 30 is the spin of a single electron (or possibly several electrons) in the quantum dots 36 and 37”. The electron is a "charge carrier," and its "spin" is utilized as the quantum bit (qubit) through entanglement and manipulation (e.g., C-NOT gates). The operation involves "tun[ing] the spin-spin interaction" and performing "single qubit operation[s]." This matches the claimed method of implementing a qubit via the spin of a charge carrier in the dot).
Claim 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schenkel (US 20130087766, which is in the IDS on 11/29/23).
Regarding claim 10. Schenkel discloses A method for manufacturing a qubit element (Fig 2, [0021]), comprising:
a) providing a wafer 170 [0021] and an insulation layer 115 of silicon dioxide ([0018]: SiO2) on a surface (top surface of 170) of the wafer;
b) etching a recess by:
b1) growing a quantum well structure directly or indirectly onto the insulation layer ([0027]: 28SOI (isotopically enriched Silicon-28 on insulator) for donor-dot device fabrication, the process of growing a 28Si enriched epi-layer onto a natural silicon device layer—which is part of a Silicon-on-Insulator (SOI) wafer—means indirectly growing a quantum well structure on the insulation layer),
wherein a quantum well is formed within the quantum well structure along a first direction (x) ([0024]: “quantum dots with a high degree of control have also been demonstrated in... Si--SiGe hetero-structures” which means the creation of a 2D electron system (a quantum well)); and
b2) locally etching the wafer on a side of the wafer opposite the insulation layer such that a recess is formed in the wafer ([0021]: etching vias in the silicon substrate 170); and
c) disposing a backgate 130 within the recess etched according to step b) ([0021]: Back gates 130 may be formed by etching vias in the silicon substrate 170, followed by deposition of conductive electrodes).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Eriksson (US 20020179897) in view of Schenkel (US 20130087766, which is in the IDS on 11/29/23).
Regarding claim 3. Eriksson discloses The qubit element according to claim 2. But Eriksson does not disclose further comprising an insulation layer of silicon dioxide abutting the base layer on a side of the base layer opposite the quantum well structure.
However, Fig 2 of Schenkel discloses an insulation layer of silicon dioxide 115 [0018] abutting the base layer on a side (back side of Si) of the base layer opposite the quantum well structure [0027] (Schenkel discloses SOI substrate, thus, the top active layer is thin silicon, and an insulating layer is directly underneath (abutting).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Eriksson’s device structure to have the Schenkel’s structure for the purpose of providing enhanced electrical isolation and, when combined with QWs, enhances carrier confinement for improved speed, efficiency, and reduced power consumption.
Regarding claim 4. Eriksson discloses The qubit element according to claim 1. But Eriksson does not disclose further comprising a wafer with a recess, wherein the backgate is arranged within the recess.
However, Fig 2 of Schenkel discloses comprising a wafer 170 with a recess (the recess where 130 formed), wherein the backgate 130 is arranged within the recess.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Eriksson’s device structure to have the Schenkel’s structure for the purpose of providing enhanced local electrostatic control, reduced crosstalk, and enhanced coherence. By burying the gate, it reduces dielectric losses, minimizes surface noise, and provides better screening, which is critical for defining and manipulating quantum dots or tuning superconducting qubit frequencies.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Eriksson (US 20020179897) in view of Pillarisetty (US 20200350423).
Regarding claim 6. Eriksson discloses The qubit element according to claim 1. But Eriksson does not disclose further comprising a magnet arranged spaced apart from the quantum well structure against the first direction (x).
But Fig 2 of Pillarisetty discloses a magnet 121 [0027] arranged spaced apart from the quantum well structure ([0028]: in 104) against the first direction (x).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Eriksson’s device structure to have the Pillarisetty’s localized magnet line for the purpose of providing enhanced spin qubit control, enabling faster, more energy-efficient operation compared to global microwave fields. They facilitate long-range, selective entanglement between qubits via magnons and increase qubit stability by reducing sensitivity to environmental magnetic noise.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812