Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/24/23, 10/22/24 was filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) #1, 4, 6, 8, 10 are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by Soffer (U.S. Pub. No. 2008/0253085), hereinafter referred to as "Soffer".
Soffer shows, with respect to claim #1, an inverter power module comprising: a ceramic substrate (fig, #8b, item 601) (paragraph 0230); an LTCC substrate disposed to be spaced apart (Below; fig. #Ex1, item OS1) from an upper portion (paragraph 0235) of the ceramic substrate (paragraph 0230); and a semiconductor chip (fig. #8b, item 612) (paragraph 0235) having a lower surface bonded to a metal pattern (fig. #8b, item 616) (paragraph 0240) on an upper surface (Below; fig. #Ex1, item SS1) of the ceramic substrate and an upper surface bonded to an external electrode (fig. #8b, item 604) of the LTCC substrate (paragraph 0234).
[AltContent: arrow][AltContent: textbox (Upper Section; US1)][AltContent: textbox (Multi-layer Area; MLA)][AltContent: textbox (Substrate upper Surface; SS1)]
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Soffer shows, with respect claim #4, an inverter further comprising: a bonding layer (fig, #8b, item 601) configured to bond a surface electrode (paragraph 0230) on a lower surface of the semiconductor chip to a metal pattern (fig, #8b, item 616) (paragraph 0234) on the upper surface (Above; fig. #Ex1, item SS1) of the ceramic substrate; and an adhesive layer (Above; fig. #Ex1, item 610) configured to bond a signal transmission electrode on an upper surface of the semiconductor chip to an external electrode on a lower surface of the LTCC substrate (paragraph 0236).
Soffer shows, with respect claim #6, an inverter further comprising: a heat dissipation plate bonded to a lower surface of the ceramic substrate (fig. #10b , item TCR) (paragraph 0234, 0291).
Soffer shows, with respect claim #8, an inverter further comprising: a circuit protection element (MLCC) (Above; fig. #Ex1, item MLA) mounted on an upper surface of the LTCC substrate (fig. #8a, item 601) (paragraph 0230-0231), wherein the circuit protection element is connected to a signal transfer electrode (fig. #8a, item 613) (paragraph 0238) on an upper surface of the semiconductor chip (fig. #8a, item 612) through an external electrode (fig. # , item 611, 618) connected to an internal electrode (fig. #8a, item 354) of the LTCC substrate (paragraph 0213).
Soffer shows, with respect to claim #10, an inverter power module comprising: a lower ceramic substrate (Above; fig, #Ex1, item LS1) (paragraph 0230); an upper (Above; fig, #Ex1, item IS1) ceramic substrate (fig, #8b, item 601) (paragraph 0230) disposed to be spaced apart (Above; fig. #Ex1, item OS1) from an upper portion of the lower ceramic substrate (paragraph 0235); a semiconductor chip (Above; fig. #Ex1, item 612) bonded to a metal pattern (fig. #8b, item 604) (paragraph 0234) on an upper surface (Above; fig. #Ex1, item SS1) of the lower ceramic substrate; and a conductive spacer (Above; fig. #Ex1, item 615) (paragraph 0238) installed between the semiconductor chip and the upper ceramic substrate to connect a signal transfer electrode (Above; fig. #Ex1, item 613) (paragraph 0238) on an upper surface of the semiconductor chip and a metal pattern of the upper ceramic substrate (fig. #8b, item 620) (paragraph 0233).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims #2, 3 are rejected under 35 U.S.C. 103 as being unpatentable over Soffer (U.S. Pub. No. 2008/0253085), hereinafter referred to as "Soffer" as shown in the rejection of claim #1 above and in view of APELSMEIER et al., (U.S. Pub. No. 2021/0091054), hereinafter referred to as "Apelsmeier".
Soffer substantially shows the claimed invention as shown in the rejection of claim #1 above.
Soffer fails to show, with respect to claim #2, an inverter power module wherein the ceramic substrate is an active metal brazing (AMB) substrate.
Apelsmeier teaches, with respect to claim #2, an inverter power module wherein the ceramic substrate is an active metal brazing (AMB) substrate (paragraph 0042).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #2, to modified the invention of Soffer as modified by the invention of Apelsmeier, which teaches, an inverter power module wherein the ceramic substrate is an active metal brazing (AMB) substrate, to incorporate a structural condition that provides high resistant to oxidation and corrosion and ensure long-term stability even in harsh environments, as taught by Apelsmeier.
Soffer fails to show, with respect to claim #3, an inverter power module wherein the semiconductor chip is a SiC chip.
Apelsmeier teaches, with respect to claim #3, an inverter power module wherein the semiconductor chip is a SiC chip (paragraph 0042).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #3, to modified the invention of Soffer as modified by the invention of Apelsmeier, which teaches, an inverter power module wherein the semiconductor chip is a SiC chip, to incorporate a structural condition with wide bandgap, high thermal conductivity and high breakdown voltage, as taught by Apelsmeier.
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Claim #5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Soffer (U.S. Pub. No. 2008/0253085), hereinafter referred to as "Soffer" as shown in the rejection of claim #4 above and in view of Chen et al., (U.S. Pub. No. 2013/0001756), hereinafter referred to as "Chen".
Soffer substantially shows the claimed invention as shown in the rejection of claim #4 above.
Soffer fails to show, with respect to claim #5, an inverter power module wherein the bonding layer is made of silver nanopaste, and the adhesive layer is made of silver nanopaste or solder.
Chen teaches, with respect to claim #5, an inverter power module wherein the bonding layer is made of silver nanopaste, and the adhesive layer is made of silver nanopaste or solder (paragraph 0030).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #5, to modified the invention of Soffer as modified by the invention of Chen, which teaches, an inverter power module wherein the bonding layer is made of silver nanopaste, and the adhesive layer is made of silver nanopaste or solder, to incorporate a structural condition that enhance the shielding area of the device, as taught by Chen.
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Claim #7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Soffer (U.S. Pub. No. 2008/0253085), hereinafter referred to as "Soffer" as shown in the rejection of claim #6 above and in view of Ho et al., (U.S. Pub. No. 2015/0179607), hereinafter referred to as "Ho".
Soffer substantially shows the claimed invention as shown in the rejection of claim #6 above.
Soffer fails to show, with respect to claim #7, an inverter power module wherein the heat dissipation plate includes a thermal interface material (TIM).
Ho teaches, with respect to claim #7, an inverter power module wherein the heat dissipation plate includes a thermal interface material (TIM) (paragraph 0026).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #7, to modified the invention of Soffer as modified by the invention of Ho, which teaches, an inverter power module wherein the heat dissipation plate includes a thermal interface material (TIM), to incorporate a structural condition that would provide a high performance interfaces with increased thermal conductivity, as taught by Ho.
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Claim #9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Soffer (U.S. Pub. No. 2008/0253085), hereinafter referred to as "Soffer" as shown in the rejection of claim #1 above and in view of Oya et al., (U.S. Pub. No. 2007/0247268), hereinafter referred to as "Oya".
Soffer substantially shows the claimed invention as shown in the rejection of claim #1 above.
Soffer fails to show, with respect to claim #9, an inverter power module further comprising: a lead frame bonded to the metal pattern on the upper surface of the ceramic substrate and extending outward; and a mold compound configured to surround and integrate the ceramic substrate, the LTCC substrate, and the semiconductor chip and to expose an end of the lead frame to an outside.
Oya teaches, with respect to claim #9, an inverter power module further comprising: a lead frame (fig. #8b, item 33) (paragraph 0144) bonded to the metal pattern (fig. #1b, item 15) (paragraph 0086) on the upper surface of the ceramic substrate (fig. #8b, item 16) (paragraph 0005, 0085) and extending outward (fig. #8b, item 33); and a mold compound (fig. #8b, item 31) configured to surround and integrate the ceramic substrate (paragraph 0146), the LTCC substrate, and the semiconductor chip and to expose an end of the lead frame to an outside (fig. #8b, item 33) (paragraph 0144).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #9, to modified the invention of Soffer as modified by the invention of Oya, which teaches, an inverter power module further comprising: a lead frame bonded to the metal pattern on the upper surface of the ceramic substrate and extending outward; and a mold compound configured to surround and integrate the ceramic substrate, the LTCC substrate, and the semiconductor chip and to expose an end of the lead frame to an outside, to incorporate a structural condition that would provide seal area for the inductor and electrical connection the circuits outside the device, as taught by Oya.
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Claim #11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Soffer (U.S. Pub. No. 2008/0253085), hereinafter referred to as "Soffer" as shown in the rejection of claim #10 above and in view of Lopata et al., (U.S. Pub. No. 2003/0194832), hereinafter referred to as "Lopata".
Soffer substantially shows the claimed invention as shown in the rejection of claim #10 above.
Soffer fails to show, with respect to claim #11, an inverter power module further comprising: a first heat dissipation plate bonded to a lower surface of the lower ceramic substrate; and a second heat dissipation plate bonded to an upper surface of the upper ceramic substrate.
Lopata teaches, with respect to claim #11, with respect to claim #11, an inverter power module further comprising: a first heat dissipation plate (fig. #20, item 206) bonded to a lower surface of the lower ceramic substrate; and a second heat dissipation plate (fig. #20, item 200) bonded to an upper surface of the upper ceramic substrate (paragraph 0261, 0270).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #11, to modified the invention of Soffer as modified by the invention of Lopata, which teaches, an inverter power module further comprising: a first heat dissipation plate bonded to a lower surface of the lower ceramic substrate; and a second heat dissipation plate bonded to an upper surface of the upper ceramic substrate, to incorporate a structural condition that enhance the shielding area of the device, as taught by Lopata.
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Claim #12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Soffer (U.S. Pub. No. 2008/0253085), hereinafter referred to as "Soffer" as modified by Lopata et al., (U.S. Pub. No. 2003/0194832), hereinafter referred to as "Lopata" as shown in the rejection of claim #11 above and in further view of Ho et al., (U.S. Pub. No. 2015/0179607), hereinafter referred to as "Ho".
Soffer as modified by Lopata, substantially shows the claimed invention as shown in the rejection of claim #11 above.
Soffer as modified by Lopata, fails to show, with respect to claim #12, an inverter power module wherein the heat dissipation plate includes a thermal interface material (TIM).
Ho teaches, with respect to claim #12, an inverter power module wherein the heat dissipation plate includes a thermal interface material (TIM) (paragraph 0026).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #12, to modified the invention of Soffer as modified by Lopata, with the modification of the Ho’s invention, which teaches, an inverter power module wherein the heat dissipation plate includes a thermal interface material (TIM), to incorporate a structural condition that would provide a high performance interfaces with increased thermal conductivity, as taught by Ho.
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Claims #13, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Soffer (U.S. Pub. No. 2008/0253085), hereinafter referred to as "Soffer" as shown in the rejection of claim #10 above and in view of APELSMEIER et al., (U.S. Pub. No. 2021/0091054), hereinafter referred to as "Apelsmeier".
Soffer substantially shows the claimed invention as shown in the rejection of claim #10 above.
Soffer fails to show, with respect to claim #13, an inverter power module wherein the upper ceramic substrate and the lower ceramic substrate are each an active metal brazing (AMB) substrate.
Apelsmeier teaches, with respect to claim #13, an inverter power module the upper ceramic substrate and the lower ceramic substrate are each an active metal brazing (AMB) substrate (paragraph 0042).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #13, to modified the invention of Soffer as modified by the invention of Apelsmeier, which teaches, an inverter power module wherein the upper ceramic substrate and the lower ceramic substrate are each an active metal brazing (AMB) substrate, to incorporate a structural condition that provides high resistant to oxidation and corrosion and ensure long-term stability even in harsh environments, as taught by Apelsmeier.
Soffer fails to show, with respect to claim #14, an inverter power module wherein the semiconductor chip is a SiC chip.
Apelsmeier teaches, with respect to claim #14, an inverter power module wherein the semiconductor chip is a SiC chip (paragraph 0042).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #14, to modified the invention of Soffer as modified by the invention of Apelsmeier, which teaches, an inverter power module wherein the semiconductor chip is a SiC chip, to incorporate a structural condition with wide bandgap, high thermal conductivity and high breakdown voltage, as taught by Apelsmeier.
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Claim #15, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Soffer (U.S. Pub. No. 2008/0253085), hereinafter referred to as "Soffer" as shown in the rejection of claim #10 above and in view of Fairchild et al., (U.S. Pub. No. 2007/0120250), hereinafter referred to as "Fairchild".
Soffer substantially shows the claimed invention as shown in the rejection of claim #10 above.
Sofer shows, with respect to claim #15, an inverter power module further comprising a bonding layer configured to bond a surface electrode (Above; fig. #Ex1, item 622) (paragraph 0240) of the semiconductor chip (Above; fig. #Ex1, item 612) (paragraph 0237) to a metal pattern (Above; fig. #Ex1, item 604) on an upper surface (Above; fig. #Ex1, item SS1) of the lower ceramic substrate (paragraph 0234, 0237); a first adhesive layer (Above; fig. #Ex1, item ) configured to bond the signal transmission electrode (Above; fig. #Ex1, item 613).
Sofer fails to show, with respect to claim #15, an inverter power module comprising a first adhesive layer configured to bond the signal transmission electrode on the upper surface of the semiconductor chip to a lower surface of the conductive spacer on the upper surface of the semiconductor chip to a lower surface of the conductive spacer and a second adhesive layer configured to bond an upper surface of the conductive spacer to a metal pattern on a lower surface of the upper ceramic substrate.
Fairchild teaches, with respect to claim #15, an inverter power module comprising an inverter power module (paragraph 0022) comprising a first adhesive layer (Below; fig. #Ex2, item 14a) (paragraph 0023) configured to bond the signal transmission electrode (Below; fig. #Ex2, item TS2 consisting of vias #26) on the upper surface of the semiconductor chip (Below; fig. #Ex2, item 12) to a lower surface of the conductive spacer on the upper surface of the semiconductor chip (paragraph 0026) to a lower surface of the conductive spacer and a second adhesive layer (Below; fig. #Ex2, item 14b) configured to bond an upper surface of the conductive spacer (Below; fig. #Ex2, item BS2) to a metal pattern (Below; fig. #Ex2, item BS2 consisting of vias #26) on a lower surface of the upper ceramic substrate (paragraph 0026, 0031-0032).
[AltContent: textbox (30)][AltContent: textbox (32)][AltContent: textbox (Bottom Spacer; BS2)][AltContent: textbox (Top Spacer; TS2)][AltContent: textbox (Lower Adhesive; 14b)][AltContent: textbox (Upper Adhesive; 14a)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Ex2)]
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It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #15, to modified the invention of Soffer as modified by the invention of Fairchild, which teaches, an inverter power module comprising an inverter power module comprising a first adhesive layer configured to bond the signal transmission electrode on the upper surface of the semiconductor chip to a lower surface of the conductive spacer on the upper surface of the semiconductor chip to a lower surface of the conductive spacer and a second adhesive layer configured to bond an upper surface of the conductive spacer to a metal pattern on a lower surface of the upper ceramic substrate, to incorporate a structural condition that advantageously provides for enhanced cooling of an electronics package 12 mounted onto a substrate, as taught by Fairchild.
Soffer fails to show, with respect to claim #16, an inverter power module wherein the bonding layer, the first adhesive layer, and the second adhesive layer are each made of silver nanopaste.
Fairchild teaches, with respect to claim #16, an inverter power module wherein the bonding layer, the first adhesive layer (Above; fig. #Ex2, item 32), and the second adhesive layer are each made of silver nanopaste (paragraph 0020).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #16, to modified the invention of Soffer as modified by the invention of Fairchild, which teaches, an inverter power module wherein the bonding layer, the first adhesive layer, and the second adhesive layer are each made of silver nanopaste, to incorporate a structural condition would provide superior electrical and thermal conductivity, high-strength bonding, and flexibility for electronic applications, as taught by Fairchild.
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Claim #17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Soffer (U.S. Pub. No. 2008/0253085), hereinafter referred to as "Soffer" as shown in the rejection of claim #10 above and in view of Oya et al., (U.S. Pub. No. 2007/0247268), hereinafter referred to as "Oya".
Soffer substantially shows the claimed invention as shown in the rejection of claim #10 above.
Soffer fails to show, with respect to claim #17, an inverter power module further comprising: a lead frame bonded to the metal pattern on the upper surface of the lower ceramic substrate and extending outward; and a mold compound configured to surround and integrate the ceramic substrate, the upper ceramic substrate, and the semiconductor chip and the conductive spacer and to expose an end of the lead frame to an outside.
Oya teaches, with respect to claim #17, an inverter power module further comprising: a lead frame (fig. #8b, item 33) (paragraph 0144) bonded to the metal pattern (fig. #1b, item 12a) (paragraph 0085) on the upper surface of the lower ceramic substrate (fig. #8b, item 16) (paragraph 0005, 0085) and extending outward (fig. #8b, item 33); and a mold compound (fig. #8b, item 31) configured to surround and integrate the ceramic substrate (paragraph 0146), the upper ceramic substrate (fig. #8b, item 18), and the semiconductor chip (fig. #8b, item 17) and the conductive spacer (fig. #8b, item 15) and to expose an end of the lead frame to an outside (fig. #8b, item 33) (paragraph 0085-0086, 0144).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #17, to modified the invention of Soffer as modified by the invention of Oya, which teaches, an inverter power module further comprising: a lead frame bonded to the metal pattern on the upper surface of the lower ceramic substrate and extending outward; and a mold compound configured to surround and integrate the ceramic substrate, the upper ceramic substrate, and the semiconductor chip and the conductive spacer and to expose an end of the lead frame to an outside, to incorporate a structural condition wherein the small-sized inductor element has a large inductance and a high quality factor , as taught by Oya.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
03/04/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899