Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Information Disclosure Statement The information disclosure statement (IDS) submitted on 05/13/24, 03/02/23 was filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . Claim #1 , 11 , 13 , 25 are rejected under 35 U.S.C. 103 as being unpatentable over SEONG et al., (U.S. Pub. No, 2017/0024060 ), hereinafter referred to as " Seong " and in view of Kim et al., (U.S. Pat. No. 2017/0097700 ), hereinafter referred to as " Kim ". Seong shows, with respect to claim #1 and 25 , display substrate, comprising: a base substrate ( fig. # 2 , item 100 ) having a wiring area ( fig. # 1 , item AA ) (paragraph 0034) ; at least one wiring layer ( fig. # 1 , item 300 ) located on the base substrate (paragraph 0034, 0044) , the wiring layer comprises a plurality of first wires ( Below; fig. # Ex 1 , item WP 1 ) and a plurality of second wires ( Below; fig. #Ex 1 , item WP 2 ) , which are arranged at intervals ( paragraph 0035 , 0073 ) and obtained by adopting different patterning processes, in the wiring area ( fig. # 8-10 , item 320a-e, 330a-e, 335a-e ) , at least part of the first wires are arranged adjacent to the second wire ( paragraph 0090, 0092-0096 ) . 2333501 2630384 1050966 2018805 2065646 2499360 A 2 0 0 A 2 741771 1858175 A 1 0 0 A 1 3236025 314696 0 0 2298560 107563 Wire Group 1; WP 1 0 0 Wire Group 1; WP 1 2863215 416560 0 0 1358900 817880 0 0 741045 1654810 0 0 741540 420980 0 0 4360985 1207477 4430688 1004228 Wire Group 2; WP 2 0 0 Wire Group 2; WP 2 3837354 1363785 0 0 2622062 543169 4474308 2426677 Ex 1 Ex 1 Seong substantially shows the claimed invention as shown in the rejection of claim #1 above. Seong fails to show, with respect to claim #1 and 25 , a device comprising a space between the first wire and the second wire adjacent to each other is less than 2 µm . Kim teaches, with respect to claim #1 and 25 , a device comprising a space between the first wire and the second wire adjacent to each other is less than 2 µm ( paragraph 0078 ) . It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim # 1 and 25 , to modified the invention of Seong as modified by the invention of Kim , which teaches, a device comprising a space between the first wire and the second wire adjacent to each other is less than 2 µm , to incorporate a structural condition that facilitates a reduction in resistance of a data line and therefore prevent the electrode pattern from being visually recognized from the outside, so the overall visibility will not be degraded , as taught by Kim . Seong shows, with respect to claim #11 , a display device wherein the display substrate comprises multiple wiring layers ( Above; fig. #Ex 1 , item WP 1 and WP 2 ) insulated from each other and orthographic projections of the wiring layers on the base substrate are independently from each other ( paragraph 0047, 0123 ) Seong shows, with respect to claim #1 3 , a method for manufacturing a display substrate comprising: providing base substrate ( fig. #2, item 100 ) with a wiring area (fig. #1, item 300) ; forming at least one wiring layer in the wiring area ( Above ; fig. #Ex 1 , item WP 1 ) of the base substrate, and patterning the wiring area corresponding to each wiring layer by adopting different patterning processes to obtain first wirings ( Above ; fig. #Ex 1 , item A 1 ) and second wirings ( Above ; fig. #Ex 1 , item A 2 ) arranged at intervals; at least part of the first wires are arranged adjacent to the second wires (fig. #8-10, item 320a-e, 330a-e, 335a-e) (paragraph 0090, 0092-0096) . Seong substantially shows the claimed invention as shown in the rejection of claim #1 3 above. Seong fails to show, with respect to claim #13, a method for manufacturing a display substrate comprising a space between the first wire and the second wire adjacent to each other is less than 2pm . Kim teaches, with respect to claim #1 3 , a display substrate comprising a space between the first wire and the second wire adjacent to each other is less than 2pm ( paragraph 0078 ) . It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim # 13 , to modified the invention of Seong as modified by the invention of Kim , which teaches, a method for manufacturing a display substrate comprising a space between the first wire and the second wire adjacent to each other is less than 2pm , to incorporate a structural condition that facilitates a reduction in resistance of a data line and therefore prevent the electrode pattern from being visually recognized from the outside, so the overall visibility will not be degraded , as taught by Kim . // Claim #2 is/ are rejected under 35 U.S.C. 103 as being unpatentable over SEONG et al., (U.S. Pub. No, 2017/0024060 ), hereinafter referred to as " Seong " as modified by Kim et al., (U.S. Pat. No. 2017/0097700 ), hereinafter referred to as " Kim " , as shown in the rejection of claim #1 and in further view of KWAK et al., (U.S. Pat. No. 2 017/0141349 ), hereinafter referred to as " Kwak ". Seong as modified by Kim, substantially shows the claimed invention as shown in the rejection of claim #1 above. Seong as modified by Kim, fails to show, with respect to claim # 2 , a display substrate wherein the first wires and the second wires of the at least one wiring layer are alternately arranged at intervals . Kwak teaches, with respect to claim # 2 , a display substrate wherein the first wires ( fig. #3, item 211a ) and the second wires ( fig. #3, item 211b ) of the at least one wiring layer ( fig. #1, item PA ) (paragraph 0034-0035) are alternately arranged at intervals ( paragraph 0072, 0080 ) . It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim # 2 , to modified the invention of Seong as modified by Kim , with the modification of the invention of Kwak , which teaches, a display substrate wherein the first wires and the second wires of the at least one wiring layer are alternately arranged at intervals , to incorporate a structural condition that facilitates a reduction in resistance of a data line and therefore prevent the electrode pattern from being visually recognized from the outside, so the overall visibility will not be degraded , as taught by Kwak . // / Claim #3 is/ are rejected under 35 U.S.C. 103 as being unpatentable over SEONG et al., (U.S. Pub. No, 2017/0024060 ), hereinafter referred to as " Seong " as modified by Kim et al., (U.S. Pat. No. 2017/0097700 ), hereinafter referred to as " Kim " , as shown in the rejection of claim #1 and in further view of Lee et al., (U.S. Pat. No. 2022/0352252 ), hereinafter referred to as " Lee ". Seong as modified by Kim, substantially shows the claimed invention as shown in the rejection of claim #1 above. Seong as modified by Kim, fails to show, with respect to claim # 3 , a display substrate wherein the display substrate comprises a display area and a frame area, the display area comprising a first display area and a second display area, the first display area having a light transmittance greater than that of the second display area; the first display area comprises a plurality of sub-pixels arranged in an array, each sub-pixel comprises a light emitting device and a pixel circuit, the pixel circuit is located in a part of the frame area adjacent to the first display area, or the second display area has a transition area adjacent to the first display area, and the pixel circuit is located in the transition area, or the pixel circuit is arranged in the second display area; the wiring area is at least partially located in the first display area, and the wiring layer is located between an anode of the light emitting device and the pixel circuit; the first wire is configured to electrically connect the light emitting device with the pixel circuit corresponding to the light emitting device, and the second wire is configured to electrically connect the light emitting device with the pixel circuit corresponding to the light emitting device . Lee teaches, with respect to claim # 3 , a display substrate wherein the display substrate ( fig. #6, item 110 ) (paragraph 0100) comprises a display area and a frame area, the display area ( fig. #1, item 100 ) (paragraph 0043) comprising a first display area ( fig. #8, item DPA1 ) and a second display area ( fig. #8, item DPA2 ) (paragraph 0072) , the first display area having a light transmittance greater than that of the second display area (paragraph 0199-0201) ; the first display area comprises a plurality of sub-pixels arranged in an array ( fig. #4, item PX1, 2, 3 ) (paragraph 0095) , each sub-pixel comprises a light emitting device ( fig. #4, item 300 ) and a pixel circuit ( fig. #4, item 210 ) , the pixel circuit is located in a part of the frame area adjacent to the first display area ( paragraph 0096, 0101 ) , or the second display area has a transition area adjacent to the first display area, and the pixel circuit is located in the transition area, or the pixel circuit is arranged in the second display area; the wiring area is at least partially located in the first display area ( paragraph 0101 ) , and the wiring layer ( fig. #4, item 262 ) is located between an anode ( fig. #4, item 210 ) of the light emitting device and the pixel circuit ( paragraph 0139 ) ; the first wire ( fig. #4, item 261 ) is configured to electrically connect the light emitting device with the pixel circuit corresponding to the light emitting device ( paragraph 0101 ) , and the second wire ( fig. #4, item 262 ) is configured to electrically connect the light emitting device with the pixel circuit corresponding to the light emitting device ( paragraph 0122 ) . It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim # 3 , to modified the invention of Seong as modified by Kim , with the modification of the invention of Lee , which teaches, wherein the display substrate comprises a display area and a frame area, the display area comprising a first display area and a second display area, the first display area having a light transmittance greater than that of the second display area; the first display area comprises a plurality of sub-pixels arranged in an array, each sub-pixel comprises a light emitting device and a pixel circuit, the pixel circuit is located in a part of the frame area adjacent to the first display area, or the second display area has a transition area adjacent to the first display area, and the pixel circuit is located in the transition area, or the pixel circuit is arranged in the second display area; the wiring area is at least partially located in the first display area, and the wiring layer is located between an anode of the light emitting device and the pixel circuit; the first wire is configured to electrically connect the light emitting device with the pixel circuit corresponding to the light emitting device, and the second wire is configured to electrically connect the light emitting device with the pixel circuit corresponding to the light emitting device , to incorporate a structural condition wherein a display device including pixels and light-emitting elements, where the pixels are disposed in different areas to distinguish the align the light-emitting elements for each area , as taught by Lee . // // Claim #7 is/ are rejected under 35 U.S.C. 103 as being unpatentable over SEONG et al., (U.S. Pub. No, 2017/0024060 ), hereinafter referred to as " Seong " as modified by Kim et al., (U.S. Pat. No. 2017/0097700 ), hereinafter referred to as " Kim " , as shown in the rejection of claim #1 and in further view of OKABE et al., (U.S. Pat. No. 2024/0381743 ), hereinafter referred to as " Okabe ". Seong as modified by Kim, substantially shows the claimed invention as shown in the rejection of claim #1 above. Seong as modified by Kim, fails to show, with respect to claim # 7 , a display substrate further comprising a planarization layer disposed on a side of the wiring layer away from the base substrate, wherein the planarization layer has first via holes at positions corresponding to the first wires and the second wires, and anodes of light emitting devices are electrically connected to the first wires and the second wires through the first via holes corresponding thereto . Okabe teaches, with respect to claim # 7 , a display substrate ( fig. # 2, item 10 ) (paragraph 0066) further comprising a planarization layer ( fig. #2, item 38pf ) (paragraph 0057) disposed on a side of the wiring layer ( fig. #2, item 36si ) away from the base substrate (paragraph 0074) , wherein the planarization layer has first via holes at positions corresponding to the first wires and the second wires ( fig. #2, item 38pf ) (paragraph 0158) , and anodes ( fig. #2, item 62pe ) of light emitting devices are electrically connected to the first wires and the second wires through the first via holes corresponding thereto ( paragraph 0090 ) . It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim # 7 , to modified the invention of Seong as modified by Kim , with the modification of the invention of Okabe , which teaches, wherein the display substrate further comprising a planarization layer disposed on a side of the wiring layer away from the base substrate, wherein the planarization layer has first via holes at positions corresponding to the first wires and the second wires, and anodes of light emitting devices are electrically connected to the first wires and the second wires through the first via holes corresponding thereto , to incorporate a structural condition wherein electrical contact with various areas of the display device may be reached , as taught by Okabe . // // Claim #8 is/ are rejected under 35 U.S.C. 103 as being unpatentable over SEONG et al., (U.S. Pub. No, 2017/0024060 ), hereinafter referred to as " Seong " as modified by Kim et al., (U.S. Pat. No. 2017/0097700 ), hereinafter referred to as " Kim " , as shown in the rejection of claim #1 and in further view of MURASHIGE et al., (U.S. Pat. No. 2023/0130571 ), hereinafter referred to as " Murashige ". Seong as modified by Kim, substantially shows the claimed invention as shown in the rejection of claim #1 above. Seong as modified by Kim, substantially shows the claimed invention in the rejection of claim #1 above. Seong shows, with respect to claim # 8 , display substrate, comprising wherein the display substrate comprises a display area ( Above; fig. #Ex 1 , item AA) (paragraph 0034) and a frame area ( Above; fig. #Ex 1 , item UA ) (paragraph 0044 ) , the display area comprising a plurality of signal lines ( Above ; fig. #Ex 1 , item WP 1 ) , and the frame area comprising the wiring area ( Above; fig. #Ex 1 , item AA) ; the first wires are configured to electrically connect with corresponding signal wires, and the second wires (fig. #8-10, item 320a-e, 330a-e, 335a-e) are configured to electrically connect with corresponding signal wires (paragraph 0081-0086 ) . Seong as modified by Kim, fail to show, with respect to claim # 8 , a device wherein the display substrate further comprises a gate metal layer and a source-drain metal laver which are sequentially formed on the base substrate, the wiring laver being located in the gate metal laver and/or the source-drain metal la yer. Murashige teaches, with respect to claim #8 , a device wherein the display substrate further comprises a gate metal layer ( fig. # 5 , item 28ge ) (paragraph 0059) and a source-drain metal la y er ( fig. # 5 , item 24 ) (paragraph 0056) which are sequentially formed on the base substrate [ fig. # 5 , item 10 (substrate) and, item 22 (base coat)] (paragraph 0052, 0055-0056) , the wiring la y er being located in the gate metal la y er ( fig. #5, item 28gl ) and/or the source-drain metal la yer (paragraph 0069) . It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim # 8 , to modified the invention of Seong as modified by Kim , with the invention of Murashige , which teaches, a device wherein the display substrate further comprises a gate metal layer and a source-drain metal la y er which are sequentially formed on the base substrate, the wiring laver being located in the gate metal la y er and/or the source-drain metal la yer, to incorporate a structural condition that would communication with neighboring gates and light emitting structures , as taught by Murashige . EXAMINATION NOTE The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments. Allowable Subject Matter Claims # 4-6 , 10 , 14, 16 , 17 , 18, 20-23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: While the prior art teaches a method comprising providing a carrier consisting of a package with a metal layer for conductive devices, (SEONG et al., 2017/0024060; Kim et al., 2017/0097700; KWAK et al., 2017/0141349; Lee et al., 2022/0352252; OKABE et al., 2024/0381743; MURASHIGE et al., 2023/0130571) , it fails to teach either collectively or alone, with respect to claim #4 , a display substrate wherein he first wires are made of p-ITO and the second wires are made of a-ITO; a crystal grain of the p- ITO is greater than a crystal grain of the a-ITO; a crystal boundary of the p-ITO is less than a crystal boundary of the a-ITO, and a resistance of the p-ITO is less than that of the a- ITO . Furthermore, with respect to claim #5 , the prior art fails to teach either collectively or alone, a display substrate wherein the first wires are made of a-ITO and the second wires are made of at least one of doped a-Si, IZO or IGZO . Also, with respect to claim #6 , the prior art fails to teach either collectively or alone, a display substrate wherein the base substrate and a second sub-wire disposed on a side of the first sub-wire away from the base substrate, the first sub-wire and the second sub-wire have a same pattern and are substantially overlapped, the first sub-wire is made of a-ITO, and the second sub-wire is made of at least one of doped a-Si, IZO or IGZO . Also, with respect to claim #10 , the prior art fails to teach either collectively or alone, a display substrate wherein a space b etween the first wire and the second wire adjacent to each other ranges from 0.15p m to 0.35p m, a width of the first wire is less than or equal to 2pm, and a width of the second wire is less than or equal to 2pm . Also, with respect to claim # 14 , the prior art fails to teach either collectively or alone, a method for manufacturing comprising annealing the first conductive layer; coating a first photoresist on a side of the annealed first conductive layer away from the base substrate, and exposing and developing the first photoresist to form a patterned first photoresist layer; etching the annealed first conductive layer by using a first etching material by taking the first photoresist layer as a mask, and forming the first wires arranged at intervals in the annealed first conductive layer; depositing a second conductive layer on a side of the first wires away from the base substrate, a material of the second conductive layer being the same as that of the first conductive layer not subjected to the annealing; coating a second photoresist on a side of the second conductive layer away from the base substrate, exposing and developing the second photoresist, forming a second photoresist-completely-removed region in an area of the second photoresist corresponding to the first wires, and forming a second photoresist-reserved region in an area of the second photoresist corresponding to an area between adjacent first wires to form a patterned second photoresist layer; and etching the second conductive layer by using a second etching material by taking the second photoresist layer as a mask, so as to form the second wires between every adjacent first wires . Also, with respect to claim # 18 , the prior art fails to teach either collectively or alone, a method for manufacturing comprising depositing a second conductive layer on a side, away from the base substrate, of the first conductive layer formed thereon with the first wires, a material of the second conductive layer being different from that of the first conductive layer; coating a second photoresist on a side of the second conductive layer away from the base substrate, exposing and developing the second photoresist to form a second photoresist completely-removed region in an area of the second photoresist corresponding to the first wires and form a second photoresist-reserved region in an area of the second photoresist corresponding to an area between adjacent first wires to form a patterned second photoresist layer; and etching the second conductive layer by using a first etching material by taking the second photoresist layer as a mask to form the second wires between every adjacent first wires, the second etching material being different from the first etching material Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Andre’ Stevenson Sr./ Art Unit 2899 /ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899