Prosecution Insights
Last updated: July 17, 2026
Application No. 18/564,501

SEMICONDUCTOR DEVICE HAVING A REDUCED CONCENTRATION OF CARBON VACANCIES AND ITS MANUFACTURING METHOD

Non-Final OA §102
Filed
Nov 27, 2023
Priority
May 28, 2021 — EU 21176547.4 +1 more
Examiner
TRAN, THANH Y
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
797 granted / 925 resolved
+18.2% vs TC avg
Moderate +9% lift
Without
With
+9.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
28 currently pending
Career history
952
Total Applications
across all art units

Statute-Specific Performance

§103
63.1%
+23.1% vs TC avg
§102
22.8%
-17.2% vs TC avg
§112
2.2%
-37.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 925 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 9-17 are objected to because of the following informalities: Claim 9 recites the limitation "the first semiconductor material" (emphasis added) in line 8. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the first semiconductor material” (as recited in line 8) is: “the silicon carbide semiconductor material” (emphasis added). Claim 11 recites the limitation "before implanting ions through at least one sidewall" (emphasis added) in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “before implanting ions through at least one sidewall” (as recited in lines 1-2) is: “before implanting the ions through the at least one sidewall” (emphasis added). Claim 13 recites the limitation "implanting ions through at least one sidewall" (emphasis added) in line 6. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “implanting ions through at least one sidewall” (as recited in line 6) is: “implanting the ions through the at least one sidewall” (emphasis added). Claim 14 recites the limitation "wherein implanting ions through at least one sidewall" (emphasis added) in line 4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “where implanting ions through at least one sidewall” (as recited in line 4) is: “wherein implanting the ions through the at least one sidewall” (emphasis added). Claim 17 recites the limitation "before implanting ions through the at least one sidewall" (emphasis added) in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “before implanting ions through the at least one sidewall” (as recited in lines 1-2) is: “before implanting the ions through the at least one sidewall” (emphasis added). Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 9-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by O’Loughlin et al. (U.S 2014/0070230 A1). As to claim 9, O’Loughlin et al. disclose in Fig. 6 a method for manufacturing a semiconductor device, comprising: growing at least one epitaxial layer (“SiC epitaxial structure” 14), the at least one epitaxial layer (“SiC epitaxial structure” 14) made from a silicon carbide semiconductor material having a [0001] crystallographic axis (Fig. 6, para. [0026]-[0028]); and implanting ions, comprising at least one of carbon ions and silicon ions, through at least one sidewall of the at least one epitaxial layer (“SiC epitaxial structure” 14) to form at least one implantation area (“carbon vacancy reduction material” 24) in a plane perpendicular to the [0001] crystallographic axis (Fig. 6, para.[0024], [0026], [0028]-[0035]), thereby reducing a concentration of carbon vacancies (Vc) in the silicon carbide semiconductor material (the silicon carbide semiconductor material of “SiC epitaxial structure” 14) with respect to the at least one epitaxial layer (“SiC epitaxial structure” 14) as-grown (Fig. 6, para. [0024], [0026], [0028], [0042]). As to claim 10, as applied to claim 9 above, O’Loughlin et al. disclose in Fig. 6 all claimed limitations including the method further comprising: at least one of: annealing the at least one epitaxial layer (“SiC epitaxial structure” 14) to further reduce a concentration of carbon vacancies (Vc) in the silicon carbide semiconductor material (the silicon carbide semiconductor material of “SiC epitaxial structure” 14) with respect to the at least one epitaxial layer (“SiC epitaxial structure” 14) after implanting ions (Fig. 6, para. [0024]); or proton irradiating the at least one epitaxial layer to further reduce a concentration of carbon vacancies (Vc) in the silicon carbide semiconductor material with respect to the at least one epitaxial layer after implanting ions. As to claim 11, as applied to claim 9 above, O’Loughlin et al. disclose in Fig. 6 all claimed limitations including the limitation: before implanting the ions through the at least one sidewall, the method further comprises: performing a plurality of processing steps to form at least one semiconductor circuit component (“semiconductor die” 10) comprising at least parts of the at least one epitaxial layer (“SiC epitaxial structure” 14); and separating the at least one semiconductor circuit component (“semiconductor die” 10) to obtain a semiconductor chip (10) having a top surface perpendicular to the [0001] crystallographic axis and a plurality of sidewalls perpendicular to the top surface (Fig. 6, para. [0026], [0034]). Allowable Subject Matter Claims 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 1-8 are allowed. The following is a statement of reasons for the indication of allowable subject matter: a semiconductor device comprising: at least one epitaxial layer made from a silicon carbide semiconductor material and having a [0001] crystallographic axis; and at least one implantation area formed at a sidewall of the epitaxial layer, a normal direction of the sidewall being perpendicular to the [0001] crystallographic axis, the at least one implantation area comprising an implanted species, comprising at least one of carbon ions or silicon ions; wherein at least one part of the epitaxial layer has a reduced concentration of carbon vacancies (Vc) with a concentration of carbon vacancy Z1/2 of below 10¹⁰/cm3, as recited in independent claim 1. Claims 2-8 are dependent upon independent claim 1, and are therefore allowed. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Thanh Y. Tran/Primary Examiner, Art Unit 2817 May 16, 2026
Read full office action

Prosecution Timeline

Nov 27, 2023
Application Filed
May 20, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
95%
With Interview (+9.0%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 925 resolved cases by this examiner. Grant probability derived from career allowance rate.

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