DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “SEMICONDUCTOR MANUFACTURING APPARATUS FOR MOLDING RESIN AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Claim(s) 1-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KR-19980018456-U (hereinafter, “KR-1998”, and the English translation provided with this Office action will be referenced for specific claim limitations/elements).
Regarding claims 1-13:
re claim 1, KR-1998 discloses (in Fig. 4) a semiconductor manufacturing apparatus that manufactures a semiconductor device, comprising:
a plurality of cavities 3 (see Exhibit A above and Abstract of the English translation) filled with a molding resin 4 to form a plurality of respective molded parts (see “plurality of molded parts” in Exhibit A); and
at least one runner 6 through which the molding resin flows, the at least one runner 6
having one end (see “an upper end on one end side” in Exhibit A) connected to a gate 5 (see “gates” in Exhibit A) of one of the cavities 3, and an other end (see “an upper end on an other end side” in Exhibit A) connected to a gate 5 of an other of the cavities 3, the cavities being adjacent to each other,
wherein an upper end of the at least one runner on one end side (see “an upper end on one end side” in Exhibit A) is higher than an upper end of the at least one runner on an other end side (see “an upper end on an other end side” in Exhibit A), and
no lead frame included in the semiconductor device is disposed at each of the gates 5
of the cavities;
re claim 2, the semiconductor manufacturing apparatus according to claim 1, wherein a vertical width of the at least one runner on the one end side (see vertical width “V1” in Exhibit A) differs from a vertical width of the at least one runner on the other end side (see vertical width “V2” in Exhibit A);
re claim 3, the semiconductor manufacturing apparatus according to claim 1, wherein the at least one runner 6 includes a step (see “step” in Exhibit A) between the one end side and the other end side;
re claim 4, the semiconductor manufacturing apparatus according to claim 1, wherein the at least one runner 6 includes a slope (see “slope” in Exhibit A) between the one end side and the other end side;
re claim 5, the semiconductor manufacturing apparatus according to claim 1, wherein the at least one runner 6 includes a recess protruding upward on the one end side (see “recess in vertical portion of runner” in Exhibit A, i.e., the vertical portion defines a recess);
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re claim 6, the semiconductor manufacturing apparatus according to claim 5, wherein the recess is acute-angled (see “acute angle of recess” in Exhibit B above, wherein the angle is acute depending on a chosen point of reference);
re claims 7 and 9-13, the semiconductor manufacturing apparatus according to claims 1-6, further comprising dies 2b (Fig. 4 and Abstract) supporting the plurality of molded parts (see “plurality of molded parts” in Exhibit A) from below when at least one runner part 6 connecting the molded parts is cut, the molded parts being adjacent to each other (i.e., when the plunger 8 is released, at least one runner part directly contacting the plunger is cut); and
re claim 8, A method of manufacturing a semiconductor device, the method comprising the steps of:
(a) preparing a molded product (Fig. 4) including a plurality of molded parts (see “plurality of molded parts” in Exhibit A) and at least one runner part (see “at least one runner part” in Exhibit B) connecting the molded parts, the molded parts being adjacent to each other;
(b) applying a load of a punch 8 (Fig. 4) with one end side (see “one end side” in Exhibit B) of the at least one runner part being in contact with the punch 8, the one end side being connected to one of the adjacent molded parts (i.e., the “one end side” is connected the “plurality of molding parts” by the resin in the runner 6); and
(c) cutting the at least one runner part with application of a load of the punch (i.e., when the punch 8 is released, the at least one runner part that is in contact with the punch is cut) with an other end side of the at least one runner part being in contact with the punch, the other end
side being connected to an other of the adjacent molded parts (i.e., “contact” does not require “direct contact” and would encompass contact with/through intervening elements; accordingly, as the punch 8 is released such that the “at least one runner part” in contact with the punch is cut, the punch 8 is still connected to the bottom die 2b, therefore, “an other end side” is still in contact with the punch 8 as it’s being released),
wherein no lead frame included in the semiconductor device is disposed in the at least
one runner part.
Therefore, KR-1998 anticipates claims 1-13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The references listed on the attached PTO-892 disclose semiconductor manufacturing apparatuses a plurality of molding parts, runners and gates have some similarities to the current invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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