DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “DISPLAY PANEL WITH FIRST PIXEL UNIT STAGGERED WITH STACKED SECOND PIXEL UNIT AND PREPARATION METHOD THEREOF”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 11-16 and 19 is/are rejected under 35 U.S.C. 102((a)(1) as being anticipated by Tian et al. (US 2018/0269352 A1; hereinafter, “Tian”).
Regarding claims 1-8, 11-16 and 19:
re claim 1, Tian discloses a display panel comprising:
an array substrate 200 (Fig. 2j, [0065], Fig. 2c, and [0053]) ; and
a plurality of pixel unit groups 100 (Figs. 2c, 2j and [0046]) disposed on a side of the array substrate 200 (Fig. 2j), wherein each of the pixel unit groups comprises a first pixel unit 103 (Fig. 2j and [0054]) and a second pixel unit 102 (Fig. 2j and [0054]), and an orthographic projection of the first pixel unit 103 on the array substrate 200 and an orthographic projection of the second pixel unit 102 on the array substrate 200 are staggered (Fig. 2j, wherein orthographic projections of units 102 and 103 don’t overlap),
the first pixel unit 103 comprises a first light-emitting unit layer 32 (Fig. 2j and [0048]) for emitting a first light color (red [0048]), and
the second pixel unit 102 comprises a second light-emitting unit layer 30 (Fig. 2j and [0048]) for emitting a second light color (blue [0048]) and a third light-emitting unit layer 31 (Fig. 2j and [0048]) for emitting a third light color (green [0048]), and the second light-emitting unit layer 30 and the third light-emitting unit layer 31 are sequentially stacked in a direction facing away from the array substrate 200 (Fig. 2j);
re claim 2, the display panel as claimed in claim 1, wherein the first light color is red (layer 32 [0048]), the second light color is blue (layer 30 [0048]), and the third light color is green (layer 31 [0048]);
re claim 3, the display panel as claimed in claim 2, wherein the first pixel unit 103 comprises a first semiconductor layer 23 (Fig. 2j and [0043]) of a first doping type (N), the first light-emitting unit layer 32 [0048], and a second semiconductor layer 22 [0043] of a second doping type (P) sequentially stacked in the direction facing away from the array substrate 200;
the second pixel unit 102 comprises a third semiconductor layer 20 (Fig. 2j and [0043]) of the second doping type (P), the second light-emitting unit layer 30 [0048], a fourth semiconductor layer 21 [0043] of the first doping type (N), the third light-emitting unit layer 31 [0048], and a fifth semiconductor layer 22 [0043] of the second doping type (P) sequentially stacked in the direction facing away from the array substrate (i.e., the layers are sequentially stacked and the stacked unit 102 faces away from the substrate 200), and
the first doping type is one of N-type or P-type, and the second doping type is another of N-type or P-type;
re claim 4, the display panel as claimed in claim 3, wherein the first pixel unit 103 (Fig. 2j) further comprises:
a first electrode 46 ]0061] in contact with the first semiconductor layer 23 of the first doping type (N), and
a second electrode 45 [0061] in contact with the second semiconductor layer 22 of the second doping type (P); and
the second pixel unit 102 further comprises:
a third electrode 206 [0066] in contact with the third semiconductor layer 20 of the second doping type (P) (Note: Contact does not require “direct contact”; accordingly, electrode 206 is in contact with layer 20 through the intervening layers),
a fourth electrode 44 [0066] in contact with the fourth semiconductor layer 21 of the first doping type (N), and
a fifth electrode 43 [0066] in contact with the fifth semiconductor layer 22 of the second doping type (P),
the first electrode 46 and the fourth electrode 44 are of a same electrode type (N-type electrode), and are one of anodes and cathodes, and the first electrode 46 is electrically connected to the fourth electrode 44 (i.e., common anode or common cathode configurations are typical, accordingly, Tian anticipates the first and fourth electrodes being electrically connected), and
the second electrode 45, the third electrode 206, and the fifth electrode 43 are of a same electrode type (P-type electrode), and are another of anodes or cathodes, and the second electrode, the third electrode, and the fifth electrode are insulated from each other (i.e., the electrodes are at least thermally insulated from each other to some extent because there are intervening layers between each other);
re claim 5, the display panel as claimed in claim 4, wherein the fourth semiconductor layer 21 (in unit 102, Fig. 2j) of the first doping type comprises a first part that is not covered by the third light-emitting unit layer 31, and the fourth electrode 44 (Fig. 2j) is in contact with the first part;
re claim 6, the display panel as claimed in claim 4, wherein the array substrate comprises a plurality of pad groups (204/205/206/207/208/209 in Fig. 2j and [0066]), and each of the pad groups corresponds to one pixel unit group (group of units 103/102/101 in Fig. 2j),
each of the pad groups comprises a first pad 207/209, a second pad 208, a third pad 204/206, and a fourth pad 206/207 (i.e., the current claim doesn’t require continuous pads), and
the first pad 207/209 is electrically connected to the first electrode 46 and the fourth electrode 44, the second pad 208 is electrically connected to the second electrode 45, the third pad 204/206 is electrically connected to the third electrode 206, and the fourth pad 206/207 is electrically connected to the fifth electrode 43;
re claim 7, the display panel as claimed in claim 6, wherein the first electrode 46 (Fig. 2j) is disposed on a side of the first semiconductor layer 23 (in unit 103 of Fig. 2j) of the first doping type facing the array substrate 200, and the first electrode 46 is in contact with and electrically connected to the first pad 207/209; and
the third electrode 206 is disposed on a side of the third semiconductor layer 20 (in unit 102 of Fig. 2j) of the second doping type facing the array substrate 200, and the third electrode 206 is in contact with and electrically connected to the third pad 204/206;
re claim 8, the display panel as claimed in claim 7, wherein a distance between a surface of the second semiconductor layer 22 (in unit 103 of Fig. 2j) of the second doping type facing away from the array substrate 200 and [an upper surface of] the array substrate 200 is a first distance (as viewed in Fig. 2j);
a distance between a surface of the fifth semiconductor layer 22 (in unit 102 in Fig. 2j) of the second doping type facing away from the array substrate 200 and [a lower surface of] the array substrate 200 is a second distance, and
the second distance is greater than the first distance (i.e., in Fig. 2j, a distance between layer 22 and a lower surface of substrate 200 is greater than a distance between layer 22 and an upper surface of substrate 200);
re claim 11, the display panel as claimed in claim 1, wherein the first light color is red (layer 32 [0048]), the second light color is green (layer 31 [0048]), and the third light color is blue (layer 30 [0048]), and the first pixel unit 103 comprises a first semiconductor layer 23 (Fig. 2j and [0043]) of a first doping type (N), the first light-emitting unit layer 32 [0048], and a second semiconductor layer 22 [0043] of a second doping type (P) sequentially stacked in the direction facing away from the array substrate 200;
the second pixel unit 102 comprises a third semiconductor layer 22 (Fig. 2j and [0043]) of the second doping type (P), the second light-emitting unit layer 31 [0048], a fourth semiconductor layer 21 [0043] of the first doping type (N), the third light-emitting unit layer 30 [0048], and a fifth semiconductor layer 20 [0043] of the second doping type (P) sequentially stacked in the direction facing away from the array substrate, and
the first doping type is one of N-type or P-type, and the second doping type is another of N-type or P-type;
re claim 12, the display panel as claimed in claim 11, wherein the first pixel unit 103 (Fig. 2j) further comprises:
a first electrode 46 ]0061] in contact with the first semiconductor layer 23 of the first doping type (N), and
a second electrode 45 [0061] in contact with the second semiconductor layer 22 of the second doping type (P); and
the second pixel unit 102 further comprises:
a third electrode 43 [0066] in contact with the third semiconductor layer 22 of the second doping type (P),
a fourth electrode 44 [0066] in contact with the fourth semiconductor layer 21 of the first doping type (N), and
a fifth electrode 206 [0066] in contact with the fifth semiconductor layer 20 of the second doping type (P) (Note: Contact does not require “direct contact”; accordingly, electrode 206 is in contact with layer 20 through the intervening layers)
the first electrode 46 and the fourth electrode 44 are of a same electrode type (N-type electrode), and are one of anodes and cathodes, and the first electrode 46 is electrically connected to the fourth electrode 44 (i.e., common anode or common cathode configurations are typical, accordingly, Tian anticipates the first and fourth electrodes being electrically connected), and
the second electrode 45, the third electrode 43, and the fifth electrode 206 are of a same electrode type (P-type electrode), and are another of anodes or cathodes, and the second electrode, the third electrode, and the fifth electrode are insulated from each other (i.e., the electrodes are at least thermally insulated from each other to some extent because there are intervening layers between each other);
re claim 13, the display panel as claimed in claim 12, wherein the fourth semiconductor layer 21 (in unit 102, Fig. 2j) of the first doping type comprises a first part that is not covered by the third light-emitting unit layer 30, and the fourth electrode 44 (Fig. 2j) is in contact with the first part;
re claim 14, the display panel as claimed in claim 12, wherein the array substrate comprises a plurality of pad groups (204/205/206/207/208/209 in Fig. 2j and [0066]), and each of the pad groups corresponds to one pixel unit group (group of units 103/102/101 in Fig. 2j),
each of the pad groups comprises a first pad 207/209, a second pad 208, a third pad 204/206, and a fourth pad 206/207 (i.e., the current claim doesn’t require continuous pads), and
the first pad 207/209 is electrically connected to the first electrode 46 and the fourth electrode 44, the second pad 208 is electrically connected to the second electrode 45, the third pad 206/207 is electrically connected to the third electrode 43, and the fourth pad 204/206 is electrically connected to the fifth electrode 206;
re claim 15, the display panel as claimed in claim 14, wherein the first electrode 46 (Fig. 2j) is disposed on a side of the first semiconductor layer 23 (in unit 103 of Fig. 2j) of the first doping type facing the array substrate 200, and the first electrode 46 is in contact with and electrically connected to the first pad 207/209; and
the third electrode 43 is disposed on a side of the third semiconductor layer 22 (in unit 102 of Fig. 2j) of the second doping type facing the array substrate 200, and the third electrode 43 is in contact with and electrically connected to the third pad 206/207;
re claim 16, the display panel as claimed in claim 7, wherein a distance between a surface of the second semiconductor layer 22 (in unit 103 of Fig. 2j) of the second doping type facing away from the array substrate 200 and [an upper surface of] the array substrate 200 is a first distance (as viewed in Fig. 2j);
a distance between a surface of the fifth semiconductor layer 20 (in unit 102 in Fig. 2j) of the second doping type facing away from the array substrate 200 and [an upper surface of] the array substrate 200 is a second distance, and
the second distance is greater than the first distance (i.e., in Fig. 2j, a distance between layer 20 and an upper surface of substrate 200 is greater than a distance between layer 22 and an upper surface of substrate 200); and
re claim 19, A method of preparing a display panel, comprising steps of:
forming a first pixel composite layer A3 (Fig. 2b and [0040]) on a side of a first base 10, wherein the first pixel composite layer (e.g., A3 in Fig. 2b) comprises a second semiconductor layer 22 of a second doping type P [0043], a first light-emitting unit layer 32 [0040], and a first semiconductor layer 23 of a first doping type N [0043] sequentially stacked;
forming a second pixel composite layer A2 (Fig. 2b) on a side of a second base 100, wherein the second pixel composite layer comprises a fifth semiconductor layer 20 (in A2 of Fig. 2b) of the second doping type P, a third light-emitting unit layer 30 [0040], a fourth semiconductor layer 21 (in A2 of Fig. 2b) of the first doping type N, a second light-emitting unit layer 31 [0040], and a third semiconductor layer 22 (in A2 of Fig. 2b) of the second doping type P sequentially stacked;
bonding a side of the first pixel composite layer A3 facing away from the first base 10 to a side of an array substrate 200 (Fig. 2h), and removing the first base 10 (Figs. 2b-2j); and
bonding a side of the second pixel composite layer A2 facing away from the second base 10 to a side of the array substrate 200, and removing the second base 10 (Figs. 2b-2j),
wherein the first pixel composite layer A3 (Fig. 2b) is patterned before the step of bonding (Fig. 2h) the side of the first pixel composite layer facing away from the first base to the side of the array substrate, and removing the first base; and the second pixel composite layer A2 (Fig. 2b) is patterned before the step of bonding (Fig. 2h) the side of the second pixel composite layer facing away from the second base 10 to the side of the array substrate 200, and removing the second base 10 (i.e., it is noted the current claim does not require bonding the first and second composite layers in separate steps or in any particular sequence of steps).
Therefore, Tian anticipates claims 1-8, 1-16 and 19.
Allowable Subject Matter
Claim 20 is allowed.
Claims 9, 10, 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 9-10 are allowed primarily because the prior art of record cannot anticipate or render obvious the limitations in claim 9 (when combined with claims 1-4 and 6), and claim 10 depends from claim 9;
Claims 17-18 are allowed primarily because the prior art of record cannot anticipate or render obvious the limitations in claim 17 (when combined with claims 1 and 1-14), and claim 18 depends from claim 17; and
Claim 20 is allowed primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination with all other recited limitations: wherein after the first pixel composite layer is patterned, an insulating protrusion is formed in a patterned area of the first pixel composite layer, a via hole running through the insulating protrusion is formed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The references listed on the attached PTO-892 disclose display device incorporating a combination of stacked LEDs having some similarities to the current invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892