DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “SEMICONDUCTOR STRUCTURE WITH COVERING LAYER AND AUXILIARY LAYER OVER GATE ELECTRODE AND FORMATION METHOD THEREOF”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. (US 2016/0141207 A1; hereinafter, “Hung”) evidenced by Pradhan et al. (US 2016/0035724 A1; hereinafter, “Pradhan”).
Regarding claims 1-4:
re claim 1, Hung discloses (in Figs. 1, 5, 6, 8 and 9) a semiconductor structure, comprising:
a substrate 300/302/408/304/409/406/404 [0023];
a covering layer located over a part of the substrate (e.g., a barrier layer that is one of the layers in 402, see last sentence in [0023], wherein gate 402 contains a plurality of layers, for example, a work function metal layer, a barrier layer and a low-resistance metal layer. Note: Pradhan is provided as evidence to show, in Figs. 16-17 and [0050-0051], a multilayer gate comprising a work function metal layer 156, a barrier layer 158 and a low-resistance metal layer 162/126);
an auxiliary layer (e.g., a low-resistance layer that is the top layer of the layers in 402, i.e., Pradhan shows the top layer of a multilayer gate is a low-resistance metal layer 162/126, see Figs. 17-18) located over a surface of the covering layer;
a first dielectric layer 308 [0025] located over surfaces of the substrate 300 and the auxiliary layer (the top, low-resistance metal layer of the layers in 402);
a conductive structure 314 [0015] located in the first dielectric layer 308, wherein a top surface of the first dielectric layer 314 is flush with a top surface of the conductive structure 314;
a second dielectric layer 316 [0028] located over surfaces of the first dielectric layer 308 and the conductive structure 314;
a first opening 322 (Fig. 8 and [0030]) located in the second dielectric layer 316 and the first dielectric layer 308, wherein the first opening exposes the auxiliary layer (Fig. 8, wherein the top, low-resistance metal layer of the layers in 402 is exposed), and a second opening 320 [0029] located in the second dielectric layer 316, wherein the second opening 320 exposes the top surface of the conductive structure 314; and
a first conductive layer 330 (Fig. 9 and [0031]) located in the first opening 322, and a second conductive layer 328 (Fig. 9 and [0031]) located in the second opening 320;
re claim 2, the semiconductor structure according to claim 1, wherein:
the substrate 300/302/408/304/409/406/404 (Fig. 5 and [0023]) includes a base 300, a gate structure 404 located over the base, and an interlayer dielectric layer 306 located over the base 300, wherein the interlayer dielectric layer 306 is also located over a sidewall of the gate structure 404 and exposes a top surface of the gate structure 404, and the covering layer (e.g., a barrier layer that is one of the layers in 402, see last sentence in [0023]) is located over the top surface of the gate structure 404;
re claim 3, the semiconductor structure according to claim 2, wherein:
the substrate 300/302/408/304/409/406/404 (Fig. 5 and [0023]) further includes a source/drain layer 408 located in the substrate on two sides of the gate structure (see Fig. 1, wherein source/drain layer 408 is on two sides of 402), wherein a bottom of the conductive structure 314 (Fig. 6) is deep into the substrate and is located over a surface of the source/drain layer 408 (Fig. 6); and
re claim 4, the semiconductor structure according to claim 1, wherein: a material of the covering layer includes metal (i.e., a barrier layer that is one of the layers in 402, see last sentence in [0023], wherein gate 402 contains a plurality of layers, for example, a work function metal layer, a barrier layer and a low-resistance metal layer. Note: Pradhan is provided as evidence to show, in Figs. 16-17 and [0050-0051], a multilayer gate comprising a work function metal layer 156, a barrier layer 158 and a low-resistance metal layer 162/126, wherein the barrier layer 158 include metal, e.g., titanium, see [0050]).
Therefore, claims 1-4 are anticipated by Hung, evidenced by Pradhan.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5-9, 13 and 15-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Pradhan, Lee et al. (US 2020/0135641 A1; hereinafter, “Lee”) and Chang et al. (US 5,028,565; hereinafter, “Chang”).
Regarding claim 5:
Hung discloses a method of forming a semiconductor structure, comprising:
providing a substrate 300/302/408/304/406/404 (Fig. 2);
forming a covering layer over a part of the substrate (e.g., in Fig. 2, a barrier layer that is one of the layers in 402, see last sentence in [0023], wherein gate 402 contains a plurality of layers, for example, a work function metal layer, a barrier layer and a low-resistance metal layer. Note: Pradhan is provided to show, in Figs. 16-17 and [0050-0051], a multilayer gate comprising a work function metal layer 156, a barrier layer 158 and a low-resistance metal layer 162/126);
using a first e.g., in Fig. 2, a low-resistance layer that is the top layer of the layers in 402, wherein a deposition process is required to form the low-resistance layer i.e., Pradhan shows the top layer of a multilayer gate is a low-resistance metal layer 162/126, see Figs. 17-18) over a surface of the
covering layer;
forming a first dielectric layer 308 (Fig. 4 and [0025]) over surfaces of the substrate and the auxiliary layer;
forming a conductive structure 314 (Fig. 5 and [0015]) in the first dielectric layer, wherein a top surface of the first dielectric layer 308 is flush with a top surface of the conductive structure 314;
forming a second dielectric layer 316 (Fig. 6 and [0028]) over surfaces of the first dielectric layer 308 and the conductive structure 314;
forming a first opening 322 (Fig. 8) and a second opening 320 (Fig. 8), wherein the first opening is located in the second dielectric layer 316 and the first dielectric layer 308, and the first opening exposes the auxiliary layer (Fig. 8, wherein the top, low-resistance metal layer of the layers in 402 is exposed), and the second opening 320 is located in the second dielectric layer 316 and the second opening exposes the top surface of the conductive structure 314; and
forming a first conductive layer 326 (Fig. 9) in the first opening 322 (Fig. 8) and forming a second conductive layer 326 (Fig. 9) in the second opening 320 (Fig. 8), wherein is tungsten, Hung [0031]) over a surface of the auxiliary layer (i.e., the low-resistance layer that is the top layer of the layers in 402, as shown by Pradhan in Figs. 16-17 and [0051], which is layer 162/126 that is also tungsten) which is the barrier layer of the multilayer 402, wherein Pradhan shows such a barrier layer 158 is titanium nitride, see Pradhan Figs. 16-17 and [0050]).
Hung does not explicitly disclose a covering layer and an auxiliary layer; however, Hung specifies the structure 402 is a multilayer gate structure comprising a work function metal layer, a barrier layer, and a low-resistance layer.
Pradhan shows (as explained in detail hereinbefore) that a multilayer gate structure comprises at least a covering layer (barrier layer 158, titanium nitride [0050]) and an auxiliary layer (low-resistance metal layer 162/126, tungsten [0051]); accordingly, Pradhan shows Hung’s multilayer gate structure 402 typically comprises at least a covering layer and an auxiliary layer.
Hung (in view of Pradhan) does not specify exactly how the auxiliary layer is formed; accordingly, Hung (in view of Pradhan) does not specify a first selective deposition process to form the auxiliary layer. Furthermore, Hung (in view of Pradhan) is silent with regard to a growth rate of the first conductive layer 326 with respect to either auxiliary layer or the covering layer. However, it is noted Hung discloses the first conductive layer 326 may be tungsten, and Pradhan discloses the auxiliary layer 162/126 is tungsten and the covering layer 158 is titanium nitride; furthermore, it is noted Pradhan discloses the tungsten auxiliary layer 162/126 may be formed by any technique known in the art [0051].
Lee teaches a method of selectively depositing tungsten 88/89 (Figs. 5-6 and [0031]) that could reduce process complexity and cost [0002]. Chang teaches the growth rate of tungsten on an underlying tungsten layer would be higher than a growth rate on an underlying titanium nitride (TiN) layer because a TiN layer requires a nucleation layer to improve uniformity of the deposited tungsten layer (e.g., see Chang’s abstract and Examples I and II in column 5).
It would have been obvious to one of ordinary skill in the art to modify Hung (in view of Pradhan) by selectively depositing the auxiliary layer, as taught by Lee, because the modification could reduce process cost and complexity. Furthermore, when Hung’s tungsten first conductive layer 326 is deposited, Chang teaches the first conductive layer would have a higher growth rate (with respect to total time) over a surface of the auxiliary layer that is higher than a growth rate over the covering layer, especially because the covering layer would require a nucleation layer to be first formed.
Regarding claims 6-9, 13 and 15-21:
re claim 6, Pradhan discloses the auxiliary layer 162/126 includes tungsten;
re claim 7, Lee discloses (in [0031]) a process of forming the tungsten layer includes a chemical vapor deposition process; and process parameters of the chemical vapor deposition process include: reaction gas includes tungsten hexafluoride and hydrogen, and reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius;
re claim 8, Hung discloses the substrate (Fig. 5) includes a base 300, a gate structure 404 located over the base, and an interlayer dielectric layer 306 located over the base 300, wherein the interlayer dielectric layer 306 is also located over a sidewall of the gate structure 404 and exposes a top surface of the gate structure 404, and the covering layer (e.g., a barrier layer that is one of the layers in 402, see last sentence in [0023]) is located over the top surface of the gate structure 404;
re claim 9, Hung discloses the substrate (Figs. 1, 5 and [0023]) further includes a source/drain layer 408 located in the substrate on two sides of the gate structure (see Fig. 1, wherein source/drain layer 408 is on two sides of 402), wherein a bottom of the conductive structure 314 (Fig. 6) is deep into the substrate and is located over a surface of the source/drain layer 408 (Fig. 6);
re claim 13, Lee discloses a process of forming the covering layer (e.g., in a gate structure 68 [0015]) includes atomic layer deposition process and that selective deposition could reduce process cost and complexity;
re claim 15, Lee discloses [0031] a process of forming a first conductive layer 88 and a second conductive layer 89 includes a second selective deposition process;
re claim 16, Lee discloses [0031] process parameters of the second selective deposition process include: reaction gas includes tungsten hexafluoride and hydrogen, and reaction temperature ranges from 300 degrees Celsius to 400 degrees Celsius;
re claim 17, Hung discloses a process of forming the first conductive layer 326/330 (Figs. 8-9, [0031] and [0027], wherein a planarization process is required to obtain a planarized surface shown in Figs. 5 and 9) and the second conductive layer 326/328 includes: depositing a conductive material layer in the first opening and the second opening until the first opening and the second opening are fully filled; and planarizing the conductive material layer until the second dielectric layer is exposed (Note: With regard to this claim, the second dielectric layer in claims 5 and 15 would map to layer 318 in Figs. 8-9 without changing any other limitations in claims 5 and 15);
re claim 18, Chang discloses the growth rate of tungsten on an underlying tungsten layer would be higher than a growth rate on an underlying titanium nitride (TiN) layer because a TiN layer requires a nucleation layer to improve uniformity of the deposited tungsten layer (e.g., see Chang’s abstract and Examples I and II in column 5);
re claim 19, Hung discloses a material of the first conductive layer 126 and the second conductive layer 326 includes tungsten [0031];
re claim 20, in Pradhan (in Figs. 16-17), a total thickness of the auxiliary layer 162/126 must be at least 10 nanometers in order to acquire a functional devices; accordingly, “a” thickness of the auxiliary layer ranging from 1 nanometer to 10 nanometer is readily acquired by choosing, e.g., an 8nm thick portion at the bottom of the auxiliary layer 162/126; and
re claim 21, Pradhan discloses it was very well known in the art that a conductive structure 188 (Fig. 26 and [0057]) may be formed of a material that includes cobalt; therefore, it would have been obvious to one of ordinary skill in the art to specifically incorporate a cobalt material for Hung’s conductive structure because Pradhan teaches/shows cobalt was well-known and suitable for a conductive structure connected to a source/drain (as required by Hung’s structure).
Therefore, claims 5-9, 13 and 15-21 are rendered obvious by Hung (in view of Pradhan, Lee and Chang).
Allowable Subject Matter
Claims 10, 11 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 10-11 are allowed because the prior art of record cannot anticipate or render obvious the limitations in claim 10 (when combined with claim 5), and claim 11 depends from claim 10; and
Claims 14 is allowed because the prior art of record cannot anticipate or render obvious the limitations in this claim, when combined with claims 5 and 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The references listed on the attached PTO-892 disclose devices (and method of forming devices) with features including conductive structures flush with dielectric layers, gate electrodes with covering layer, etc., wherein the devices have some similarities to the current invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892