DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed May 1, 2026, in which: claim(s) 1 and 5 is/are amended; claim(s) 12 and 14 is/are cancelled; and the rejection of the claims are traversed. Claim(s) 1-8, 11, 13, and 15 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments filed May 1, 2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made over Ochi et al. (US 20210296425 A1, hereinafter Ochi), and further in view of Hosoyachi et al. (US 20190259345 A1, hereinafter Hosoyachi).
Applicant's arguments, with respect to the rejection(s) of amended claim(s) 1 and 5 under 35 U.S.C. 112(b) have been fully considered but they are not persuasive.
Regarding both claims 1 and 5, as amended, both claims still recite “comprise all GOA circuits". As previously set forth, claims containing this phrase are indefinite in scope because the meaning of the phrase is ambiguous and it is unclear which of the possible mutually exclusive interpretations of the phrase is claimed. While the amended limitation further clarifies “…such that none of the GOA circuits in the display panel occupies space in any corner region of the peripheral region”, it remains unclear whether the scope of the claim includes embodiments where GOA circuits are present in regions which are both outside of the first through third peripheral subregion and do not occupy space in a corner region. Possible mutually exclusive interpretations include: a) all of the aforementioned first through third peripheral subregions comprise GOA circuits, and there may be additional GOA circuits which are not in corner regions (e.g. in a peripheral region corresponding to a fourth edge); b) all GOA circuits are exclusively within the set of aforementioned first through third peripheral subregions, each of which individually comprise GOA circuits. For the purpose of examination, the examiner interprets the limitations according to a).
Applicant's arguments, with respect to the rejection(s) of amended claim(s) 1 and 5 under 35 U.S.C. 103 have been fully considered but they are not persuasive.
Regarding applicant’s remarks that “The circuits that Hosoyachi manipulates in size and pitch are the unit circuits UC of the signal switching circuit SK, which are data-side analog switches for writing grayscale signals onto data lines. They are not GOA circuits driving rows of pixel units along gate lines.” (see page 3), as previously set forth, the features of Hosoyachi interpreted as GOA circuits are the individual output circuits Xn in gate drivers GD1 and GD2 (individual gate driver circuits of a gate of an array). Each output circuit connects to a signal line Gn, which connects to gates of transistors TR in sub pixels SPi as shown in Hosoyachi FIG. 1c and 2, thus output circuits Xn are gate driver on array circuits. Additionally, it is clearly shown in Hosoyachi FIG. 2 that output circuits Xn in gate driver GD1 are shorter than pixels PX in the D2 direction. Regardless of whether Hosoyachi’s dimensions were explicitly chosen to prevent overlap of output circuits Xn with corner regions (and from Hosoyachi [0052], it appears that the gate drivers were designed with this result in mind), a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In this case, as previously set forth and elaborated upon herein, Hosoyachi discloses both the structural limitation “a longitudinal dimension of each GOA circuit is smaller than a longitudinal dimension of the corresponding pixel unit” and its intended use “such that none of the GOA circuits in the display panel occupies space in any corner region of the peripheral region”.
Regarding applicant’s remarks that “Hosoyachi does not disclose or suggest any architecture in which the first peripheral subregion, the second peripheral subregion, and the third peripheral subregion comprise all GOA circuits in the display panel such that none of the GOA circuits in the display panel occupies space in any corner region of the peripheral region” (see page 4), as previously set forth, Hosoyachi is not relied upon to disclose this limitation. Instead Ochi discloses in FIG. 2 and 8 and associated text the first peripheral subregion, the second peripheral subregion, and the third peripheral subregion comprise all GOA circuits in the display panel (unit circuits 71 (shown in Ochi FIG. 8) are in each of gate drivers 72 and 73, which are present in parts of frame region 6 corresponding to three edges (left, right, and top in Ochi FIG. 2)) such that none of the GOA circuits in the display panel occupies space in any corner region of the peripheral region (unit circuits 71 of gate drivers 72 and 73 of are not in frame corners 6a).
The relative dimensions of output circuits Xn in gate driver GD1 being shorter than pixels PX in the D2 direction as disclosed by Hosoyachi in Hosoyachi FIG. 2 and associated text does not combine with Ochi in such a way that the combination would fail to disclose this. Hosoyachi also discloses a lack of gate drivers (output circuits Xn) The teaching referenced by the applicant that Hosoyachi “adjusts the routing of low-load scanning line Gn and reshapes and resizes the signal switching circuit SK and its unit circuits near the irregular edges to equalize signal behavior and luminance” is irrelevant. Hosoyachi discloses more than just that which is relied upon for the rejection, but the applicant has not clearly indicated how any such teaching would render the combined references unsatisfactory for disclosing the claimed limitations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 11, 13, and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding both claims 1 and 5, as amended, both claims still recite “comprise all GOA circuits". As previously set forth, claims containing this phrase are indefinite in scope because the meaning of the phrase is ambiguous and it is unclear which of the possible mutually exclusive interpretations of the phrase is claimed. While the amended limitation further clarifies “…such that none of the GOA circuits in the display panel occupies space in any corner region of the peripheral region”, it remains unclear whether the scope of the claim includes embodiments where GOA circuits are present in regions which are both outside of the first through third peripheral subregion and do not occupy space in a corner region. Possible mutually exclusive interpretations include: a) all of the aforementioned first through third peripheral subregions comprise GOA circuits, and there may be additional GOA circuits which are not in corner regions (e.g. in a peripheral region corresponding to a fourth edge); b) all GOA circuits are exclusively within the set of aforementioned first through third peripheral subregions, each of which individually comprise GOA circuits. For the purpose of examination, the examiner interprets the limitations according to a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 8, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ochi et al. (US 20210296425 A1, hereinafter Ochi), and further in view of Hosoyachi et al. (US 20190259345 A1, hereinafter Hosoyachi).
Regarding independent claim 1, Ochi discloses in Ochi FIG. 2, 4, 5, 6, and 8, and associated text a display panel, comprising:
a display region, wherein the display region comprises a first edge, a second edge, a third edge, and a fourth edge, wherein the first edge is disposed opposite to the second edge, the third edge is disposed opposite to the fourth edge (display region 5 has four edges (FIG. 2)), and a corner between the first edge and the fourth edge is curved (corners 5a are curved (FIG. 2)), and wherein the display region comprises a plurality of pixel units (display region 5 includes a plurality of pixels 12 (FIG. 4)); and
a peripheral region that at least partially surrounds the display region (frame region 6 (FIG. 2)), wherein a first peripheral subregion of the peripheral region corresponds to the first edge, a second peripheral subregion of the peripheral region corresponds to the second edge, and a third peripheral subregion of the peripheral region corresponds to the third edge (left, right and top edges of frame region 6);
wherein each of the first peripheral subregion, the second peripheral subregion, and the third peripheral subregion comprises a gate driver on array (GOA) circuit and a GOA signal line (unit circuits 71 of gate drivers 72 and 73, and gate wires 21g and routed wires 80 (GOA signal lines) are present in parts of frame region 6 corresponding to three edges (GOA signal lines corresponding to first and second edges in FIG. 2; GOA circuits of gate divers 72 and 73 and GOA signal lines corresponding to third edge in Ochi FIG. 8)), wherein each GOA circuit is configured to drive a corresponding pixel unit of the plurality of pixel units, and each GOA signal line is used to connect the GOA circuit and the corresponding pixel unit (each unit circuit 71 of the gate drivers 72/73 has a corresponding gate wire 21g ([0102]), and each gate wire 21g corresponds to a pixel circuit 35 ([0055])) the first peripheral subregion, the second peripheral subregion, and the third peripheral subregion comprise all GOA circuits in the display panel (unit circuits 71 (shown in Ochi FIG. 8) are in each of gate drivers 72 and 73, which are present in parts of frame region 6 corresponding to three edges (left, right, and top in Ochi FIG. 2)) such that none of the GOA circuits in the display panel occupies space in any corner region of the peripheral region (unit circuits 71 of gate drivers 72 and 73 of are not in frame corners 6a);
wherein the peripheral region comprises a signal providing region, the signal providing region is adjacent to the fourth edge, and a length of the signal providing region is smaller than or equal to a length of the fourth edge (terminal unit 7 is a region which provides signals through terminals 21t connected to source wires 21s, is adjacent to the fourth edge, and is in one or more dimensions smaller than a length of the fourth edge as depicted (FIG. 2));
wherein the display region further comprises K data connection lines disposed between the plurality of pixel units, and K is a natural number (source wires 21s, which are physical and discrete units and therefore must inherently come in a natural number (FIG. 2));
wherein each pixel unit comprises M columns*N rows of light-emitting devices (pixels 12 comprise a 1x3 matrix of sub-pixels 13 and each of the sub-pixels has a corresponding light-emitting element 37 (FIG. 4, [0067])), M columns*N rows of bottom drive circuits (pixel circuit 35 serves as the sub-pixel 13, therefore shares the same 1x3 matrix (FIG. 6, [0054])), and M*N anode leads, wherein the anode leads are used to connect the light-emitting devices to the bottom drive circuits (first electrode 38 of organic EL element 37 (a.k.a. light-emitting device 37) is an anode ([0061]), which is connected to TFT 19f, which is a component of pixel circuit 35 (FIG. 5 and 6)), the bottom drive circuits are disposed at lower layers of the light-emitting devices (as depicted in FIG. 5, where components of the pixel circuit are below the light-emitting device 37), and both M and N are natural numbers (1 and 3 are natural numbers),
wherein an interval between adjacent light-emitting devices in each pixel unit of the plurality of pixel units is larger than a dimension of the bottom drive circuits corresponding to the adjacent light-emitting devices in the pixel unit (as depicted, an interval between left edges of light-emitting devices 37 is greater than a dimension of the pixel circuit 35 components connected to each light-emitting device 37 (FIG. 5; please also refer to the following figure)), to enable a gap to exist between the pixel units (a gap between pixel units 12 exists (FIG. 4, regions not enclosed by 12)); and
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wherein the K data connection lines are used to pass through gaps between the plurality of pixel units in the display region (source wires 21s depicted passing through gaps between pixel units 12 (FIG. 4)), and to connect pixel units in Q columns in the plurality of pixel units to the signal providing region (source wires 21s connect to the terminal unit 7 (FIG. 2) and the pixel circuits 35 (FIG. 6)), and the pixel units in Q columns comprise pixel units corresponding to the corner between the first edge and the fourth edge, and Q is a natural number less than or equal to K (FIG. 4 shows at least three source wires 21s per column of pixels 12, therefore Ochi discloses K is greater than Q by at least 3 times).
Ochi does not explicitly disclose a longitudinal dimension of each GOA circuit is smaller than a longitudinal dimension of the corresponding pixel unit.
However, in the same field of endeavor, Hosoyachi discloses in Hosoyachi FIG. 2 and associated text a longitudinal dimension of the GOA circuit is smaller than a longitudinal dimension of the corresponding pixel unit (Hosoyachi FIG. 2 shows the length of output circuits Xn in gate driver GD1 are shorter than pixels PX in the D2 direction).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Ochi and Hosoyachi to provide the display panel of Ochi with the smaller GOA circuits of Hosoyachi to provide gate drivers that do not overlap with irregularly shaped edges/rounded corners, increasing the degree of freedom in panel layout and reducing the size of the frame (Hosoyachi [0052]).
Regarding dependent claim 4, Ochi, as modified by Hosoyachi, further discloses in Ochi FIG. 8 and associated text a width of the peripheral region at the corner between the first edge and the fourth edge is smaller than a width of the peripheral region at the first edge (The length A between the outer end edge and the display region 5 in the frame corner 6a of the frame region 6 may be shorter than the length B between the outer end edge and the display region 5 in the first frame side 6c, and than the length C between the outer end edge and the display region 5 in the second frame side 6d ([0123])).
Regarding independent claim 5, Ochi discloses in Ochi FIG. 2, 4, 5, 6, and 8, and associated text a display panel, comprising:
a display region, wherein the display region comprises a first edge, a second edge, a third edge, and a fourth edge, wherein the first edge is disposed opposite to the second edge, the third edge is disposed opposite to the fourth edge (display region 5 has four edges (FIG. 2)), and a corner between the first edge and the fourth edge is curved (corners 5a are curved (FIG. 2)), and wherein the display region comprises a plurality of pixel units (display region 5 includes a plurality of pixels 12 (FIG. 4)); and
a peripheral region that at least partially surrounds the display region (frame region 6 (FIG. 2)), wherein a first peripheral subregion of the peripheral region corresponds to the first edge, a second peripheral subregion of the peripheral region corresponds to the second edge, and a third peripheral subregion of the peripheral region corresponds to the third edge (left, right and top edges of frame region 6);
wherein each of the first peripheral subregion, the second peripheral subregion, and the third peripheral subregion comprises a gate driver on array (GOA) circuit and a GOA signal line (unit circuits 71 of gate drivers 72 and 73, and gate wires 21g and routed wires 80 (GOA signal lines) are present in parts of frame region 6 corresponding to three edges (GOA signal lines corresponding to first and second edges in FIG. 2; GOA circuits of gate divers 72 and 73 and GOA signal lines corresponding to third edge in Ochi FIG. 8)), wherein each GOA circuit is configured to drive a corresponding pixel unit of the plurality of pixel units, and each GOA signal line is used to connect the GOA circuit and the corresponding pixel unit (each unit circuit 71 of the gate drivers 72/73 has a corresponding gate wire 21g ([0102]), and each gate wire 21g corresponds to a pixel circuit 35 ([0055])) the first peripheral subregion, the second peripheral subregion, and the third peripheral subregion comprise all GOA circuits in the display panel (unit circuits 71 (shown in Ochi FIG. 8) are in each of gate drivers 72 and 73, which are present in parts of frame region 6 corresponding to three edges (left, right, and top in Ochi FIG. 2)) such that none of the GOA circuits in the display panel occupies space in any corner region of the peripheral region (unit circuits 71 of gate drivers 72 and 73 of are not in frame corners 6a);
peripheral subregions corresponding to the first edge and the second edge each comprise GOA circuits (gate drivers 72 are present in subregions of frame region 6 corresponding to the first and second edge);
wherein the peripheral region comprises a signal providing region, the signal providing region is adjacent to the fourth edge, and a length of the signal providing region is smaller than or equal to a length of the fourth edge (terminal unit 7 is a region which provides signals through terminals 21t connected to source wires 21s, is adjacent to the fourth edge, and is in one or more dimensions smaller than a length of the fourth edge as depicted (FIG. 2));
wherein the display region further comprises K data connection lines disposed between the plurality of pixel units, and K is a natural number (source wires 21s, which are physical and discrete units and therefore must inherently come in a natural number (FIG. 2));
wherein each pixel unit comprise M columns*N rows of light-emitting devices (pixels 12 comprise a 1x3 matrix of sub-pixels 13 and each of the sub-pixels has a corresponding light-emitting element 37 (FIG. 4, [0067])), M columns*N rows of bottom drive circuits (pixel circuit 35 serves as the sub-pixel 13, therefore shares the same 1x3 matrix (FIG. 6, [0054])), and M*N anode leads, wherein the anode leads are used to connect the light-emitting devices to the bottom drive circuits (first electrode 38 of organic EL element 37 (light-emitting device) is an anode ([0061]), which is connected to TFT 19f, which is a component of pixel circuit 35 (FIG. 5 and 6)), the bottom drive circuits are disposed at lower layers of the light-emitting devices (as depicted in FIG. 5, where components of the pixel circuit are below the light-emitting device 37), and both M and N are natural numbers (1 and 3 are natural numbers),
wherein an interval between adjacent light-emitting devices in each pixel unit is larger than a dimension of the bottom drive circuits corresponding to the adjacent light-emitting devices in the pixel unit (as depicted, an interval between left edges of light-emitting devices 37 is greater than one or more dimensions of the pixel circuit 35 components connected to each light-emitting device 37 (FIG. 5; please also refer to the following figure)), to enable a gap to exist between the pixel units (a gap between pixel units 12 exists (FIG. 4, regions not enclosed by 12)); and
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wherein the K data connection lines are used to pass through gaps between the plurality of pixel units in the display region (source wires 21s depicted passing through gaps between pixel units 12 (FIG. 4)), and to connect pixel units in Q columns in the plurality of pixel units to the signal providing region (source wires 21s connect to the terminal unit 7 (FIG. 2) and the pixel circuits 35 (FIG. 6)), and the pixel units in Q columns comprise pixel units corresponding to the corner between the first edge and the fourth edge, and Q is a natural number less than or equal to K (FIG. 4 shows at least three source wires 21s per column of pixels 12, therefore Ochi discloses K is greater than Q by at least 3 times).
Ochi does not explicitly disclose a longitudinal dimension of each GOA circuit is smaller than a longitudinal dimension of the corresponding pixel unit.
However, in the same field of endeavor, Hosoyachi discloses in Hosoyachi FIG. 2 and associated text a longitudinal dimension of the GOA circuit is smaller than a longitudinal dimension of the corresponding pixel unit (Hosoyachi FIG. 2 shows the length of output circuits Xn in gate driver GD1 are shorter than pixels PX in the D2 direction).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Ochi and Hosoyachi to provide the display panel of Ochi with the smaller GOA circuits of Hosoyachi to provide gate drivers that do not overlap with irregularly shaped edges/rounded corners, increasing the degree of freedom in panel layout and reducing the size of the frame (Hosoyachi [0052]).
Regarding dependent claim 8, Ochi, as modified by Hosoyachi, further discloses in Ochi FIG. 8 and associated text a width of the peripheral region at the corner between the first edge and the fourth edge is smaller than a width of the peripheral region at the first edge (The length A between the outer end edge and the display region 5 in the frame corner 6a of the frame region 6 may be shorter than the length B between the outer end edge and the display region 5 in the first frame side 6c, and than the length C between the outer end edge and the display region 5 in the second frame side 6d (Ochi [0123])).
Regarding dependent claim 11, Ochi, as modified by Hosoyachi, further discloses a display device, comprising: a display configured to display an image, wherein the display comprises the display panel according to claim 5 (A display device […] includes […] a display panel including: a region displaying an image (Ochi [0010])).
Claims 2, 3, 6-7, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ochi, and further in view of Hosoyachi and Kim et al. (US 20200135595 A1, hereinafter Kim).
Regarding dependent claim 2, Ochi, as modified by Hosoyachi, discloses the display panel of claim 1, but does not explicitly disclose a peripheral region corresponding to the corner between the first edge and the fourth edge comprises a panel crack detection (PCD) lead and a water-and-oxygen dam (Dam) region and a distance between the PCD lead and the corner is less than a distance between the Dam region and the corner, to enable the PCD lead not to pass through the Dam region.
However, in the same field of endeavor, Kim discloses a peripheral region corresponding to the corner between the first edge and the fourth edge comprises a panel crack detection (PCD) lead and a water-and-oxygen dam (Dam) region and a distance between the PCD lead and the corner is less than a distance between the Dam region and the corner, to enable the PCD lead not to pass through the Dam region (the main crack detection lines MCDa and MCDb may be disposed in an inner region of the peripheral area PA such that the main crack detection lines MCDa and MCDb are disposed between the dam portion 350d and the display area DA (Kim [0090])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Ochi, as modified by Hosoyachi, and Kim to provide the display panel of Ochi surrounded by the Dam region and PCD lead of Kim to prevent organic material from flowing outside (Kim [0097]) and enable detection of defects in the edge area (Kim [0006]).
Regarding dependent claim 3, Ochi, as modified by Hosoyachi and Kim, further discloses the peripheral region corresponding to the corner between the first edge and the fourth edge further comprises an isolation column, and the isolation column is disposed on both sides of the Dam region (Kim discloses at least one dam portion 350d (Kim [0089]). In embodiments containing three or more, the portions on either side of a middle dam portion are considered isolation columns.).
Regarding dependent claim 6, Ochi, as modified by Hosoyachi, discloses the display panel of claim 5, but does not explicitly disclose a peripheral region corresponding to the corner between the first edge and the fourth edge comprises a panel crack detection (PCD) lead and a water-and-oxygen dam (Dam) region and a distance between the PCD lead and the corner is less than a distance between the Dam region and the corner, to enable the PCD lead not to pass through the Dam region.
However, in the same field of endeavor, Kim discloses a peripheral region corresponding to the corner between the first edge and the fourth edge comprises a panel crack detection (PCD) lead and a water-and-oxygen dam (Dam) region and a distance between the PCD lead and the corner is less than a distance between the Dam region and the corner, to enable the PCD lead not to pass through the Dam region (the main crack detection lines MCDa and MCDb may be disposed in an inner region of the peripheral area PA such that the main crack detection lines MCDa and MCDb are disposed between the dam portion 350d and the display area DA (Kim [0090])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Ochi, Hosoyachi, and Kim to provide the display panel of Ochi and REF surrounded by the Dam region and PCD lead of Kim to prevent organic material from flowing outside (Kim [0097]) and enable detection of defects in the edge area (Kim [0006]).
Regarding dependent claim 7, Ochi, as modified by Hosoyachi and Kim, further discloses the peripheral region corresponding to the corner between the first edge and the fourth edge further comprises an isolation column, and the isolation column is disposed on both sides of the Dam region (Kim discloses at least one dam portion 350d (Kim [0089]). In embodiments containing three or more, the portions on either side of a middle dam portion are considered isolation columns.).
Regarding dependent claim 13, Ochi, as modified by Hosoyachi and Kim, further discloses in Ochi FIG. 8 and associated text a width of the peripheral region at the corner between the first edge and the fourth edge is smaller than a width of the peripheral region at the first edge (The length A between the outer end edge and the display region 5 in the frame corner 6a of the frame region 6 may be shorter than the length B between the outer end edge and the display region 5 in the first frame side 6c, and than the length C between the outer end edge and the display region 5 in the second frame side 6d (Ochi [0123])).
Regarding dependent claim 15, Ochi, as modified by Hosoyachi and Kim, further discloses in Ochi FIG. 8 and associated text a width of the peripheral region at the corner between the first edge and the fourth edge is smaller than a width of the peripheral region at the first edge (The length A between the outer end edge and the display region 5 in the frame corner 6a of the frame region 6 may be shorter than the length B between the outer end edge and the display region 5 in the first frame side 6c, and than the length C between the outer end edge and the display region 5 in the second frame side 6d (Ochi [0123])).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20200066196 A1, pertaining to display panel crack detection.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu: 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights