DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 12 is objected to because of the following informalities: claim 12 is dependent on claim 11, which is cancelled. For the purpose of examination, the examiner interprets claim 12 as dependent on claim 10 because the amended version of claim 10 contains all limitations previously set forth in the cancelled claim 11. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 2, 6-9, 14, 17, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yusa et al. (JP 2020102587 A, hereinafter Yusa), and further in view of Yoshioka et al. (US 20120206891 A1, hereinafter Yoshioka).
Regarding independent claim 1, Yusa discloses A three-dimensional circuit part comprising: a metal member (metal portion 50); a first resin layer provided on top of the metal member (resin portion 10); first circuit wiring including plating film provided on a wiring region of a surface of the first resin layer (circuit pattern 20/plating film 21 and/or the groove 13 in which the plating film 21 is formed are considered a wiring region, as shown in Yusa FIG. 1); and a first mounted component mounted on a mount region of the surface of the first resin layer to electrically connect to the first circuit wiring (mounting part 30 is mounted above concave-convex structure 12, considered the mounting portion, and is electrically connected to the circuit pattern, Yusa [0008]), wherein: in the surface of the first resin layer, the wiring region and the mount region overlap in an overlap region (concave-convex structure 12 is the mount region which is in and overlaps with groove 13, therefore concave-convex structure 12 is also considered an overlap region), and a surface roughness Rz of the overlap region is 10 μm to 120 μm (in an example embodiment, height h1 of convex portion 12B was 0.08mm-0.10mm and height h2 of concave portion 12A was 0.02mm-0.04mm (Yusa [0100]), resulting in an Rz of 60 μm to 80 μm, lying within the claimed range); and a minimum distance between the first circuit wiring and a face of the first resin layer facing the metal member within the overlap region is 10 μm to 100 μm (in the same example, height h2 of concave portion 12A was 20 μm to 40 μm (Yusa [0100]), lying within the claimed range). Yusa does not explicitly disclose a surface roughness Ra of the overlap region is higher than a surface roughness Ra of a portion of the wiring region other than the overlap region.
However, in the same field of endeavor, Yoshioka discloses a surface roughness Ra of the overlap region is higher than a surface roughness Ra of a portion of the wiring region other than the overlap region (the average surface roughness RzPB in the recess H3b corresponding to a mount region is greater than the average surface roughness RzLB in a non-overlap region of the wiring region H3a, as seen in Yoshioka FIG. 2B and Yoshioka [0061]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the circuit part of Yusa with the increased average surface roughness of the overlap region compared to other wiring regions as disclosed by Yoshioka to provide increased bonding strength and suppress separation of the conductor in the wiring region (Yoshioka [0015]).
Regarding dependent claim 2, Yusa, as modified by Yoshioka, further discloses the surface roughness Rz of the overlap region is higher than a surface roughness Rz of a portion of the wiring region other than the overlap region (it is clear from Yusa FIG. 2a that the difference in height between the highest and lowest points of the surface of concave-convex structures 12 is greater than that of the rest of bottom surface 13a of the groove 13, and similarly in Yoshioka FIG. 2B).
Regarding dependent claim 6, Yusa, as modified by Yoshioka, further discloses the first resin layer contains a thermosetting resin (resin portion 10 may include thermoset resins, Yusa [0026]).
Regarding dependent claim 7, Yusa, as modified by Yoshioka, further discloses the thermosetting resin is an epoxy resin (resin portion 10 may include thermoset resins such as an epoxy resin, Yusa [0026]).
Regarding dependent claim 8, Yusa, as modified by Yoshioka, further discloses the metal member is a product of sheet metal working (metal portion 50 may be a commercially available metal plate (Yusa [0048]), which is considered sheet metal and any structure of sheet metal is inherently a product of sheet metal working).
Regarding dependent claim 9, Yusa, as modified by Yoshioka, further discloses a material forming the product of sheet metal working is one selected from the group consisting of aluminum, stainless steel, and copper (the metals disclosed for metal portion 50 include aluminum, stainless steel, and copper (Yusa [0017])).
Regarding dependent claim 14, Yusa, as modified by Yoshioka, further discloses a method of manufacturing the three-dimensional circuit part according to claim 1, comprising: preparing the metal member (the metallic portion 50 is prepared (Yusa [0048])); forming the first resin layer by shaping a first resin sheet on top of the metal member or applying a first resin liquid to the metal member (base substrate H1 - corresponding to resin portion 10 on metallic portion 50 - may be formed by pouring a material (Yoshioka [0081]-[0082]), which would be liquid resin since H1 is made of resin (Yoshioka [0071])); forming the first circuit wiring through plating on the wiring region of the surface of the first resin layer (plating film 21 is formed by plating (Yusa [0089])); and mounting the first mounted component on the mount region of the surface of the first resin layer (mounting component 30 is mounted over concave-convex structure 12, considered the mount region (Yusa [0091])).
Regarding dependent claim 17, Yusa, as modified by Yoshioka, further discloses the first circuit wiring includes: illuminating the wiring region with a laser beam to roughen the wiring region (the bottom 13a of the groove 13 is roughened by laser (Yusa [0034])); providing the roughened wiring region with an electroless-plating catalyst (an electroless plating catalyst is applied to the surface of the resin portion 10 (Yusa [0059]), which includes the roughened surface of 13a); and forming electroless-plating film by bringing an electroless-plating solution into contact with the wiring region provided with the electroless-plating catalyst (an electroless plating solution is brought into contact with the surface [which electroless plating catalyst was previously to] (Yusa [0059])).
Regarding dependent claim 20, Yusa, as modified by Yoshioka, further discloses the preparing of the metal member is forming the metal member through metal sheet working of a metal sheet (metal portion 50 may be a commercially available metal plate (Yusa [0048]), which is considered sheet metal and any structure of sheet metal is inherently a product of sheet metal working).
Regarding dependent claim 21, Yusa, as modified by Yoshioka, further discloses a material of the metal sheet is one selected from the group consisting of aluminum, stainless steel, and copper (the metals disclosed for metal portion 50 include aluminum, stainless steel, and copper (Yusa [0017])).
Claims 10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yusa, and further in view of Nagamatsu et al. (US 20110174527 A1, hereinafter Nagamatsu).
Regarding independent claim 10, Yusa discloses A three-dimensional circuit part comprising: a metal member (metal portion 50); a first resin layer provided on top of the metal member (resin portion 10); first circuit wiring including plating film provided on a wiring region of a surface of the first resin layer (circuit pattern 20/plating film 21 and/or the groove 13 in which the plating film 21 is formed are considered a wiring region, as shown in Yusa FIG. 1); and a first mounted component mounted on a mount region of the surface of the first resin layer to electrically connect to the first circuit wiring (mounting part 30 is mounted above concave-convex structure 12, considered the mounting portion, and is electrically connected to the circuit pattern, Yusa [0008]). Yusa does not explicitly disclose the first resin layer includes a multi-stage groove structure including a first groove formed in the wiring region and a second groove formed within the first groove and having a smaller width than the first groove, the plating film of the first circuit wiring fills the multi-stage groove structure, wherein the plating film of the first circuit wiring includes a protrusion protruding outward from the multi-stage groove structure, or a height of the protrusion as measured from a portion of the surface of the first resin layer where the first circuit wiring is not present is not larger than 30% of a film thickness of the plating film.
However, in the same field of endeavor, Nagamatsu discloses the first resin layer includes a multi-stage groove structure including a first groove formed in the wiring region and a second groove formed within the first groove and having a smaller width than the first groove (first and second openings 1032 and 1232 respectively form a multi-stage groove in wiring layer 1020, where width d of opening 1232 is greater than width c of opening 1032 (Nagamatsu [0178])), the plating film of the first circuit wiring fills the multi-stage groove structure (electrode 1240 and electrode forming region 1022 are formed by electroplating (Nagamatsu [0184]), thus a plating film, and fills first and second openings 1032 and 1232), wherein the plating film of the first circuit wiring includes a protrusion protruding outward from the multi-stage groove structure (protrusion 1244), or a height of the protrusion as measured from a portion of the surface of the first resin layer where the first circuit wiring is not present is not larger than 30% of a film thickness of the plating film (as shown in Nagamatsu FIG. 26, the height of protrusion 1244 is less than 30% of the overall height of the plating film; please also refer to the following figure).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional circuit part of Yusa with the multi-stage groove and protrusion of Nagamatsu to provide a wiring region with protrusions that reduce the distance between the wiring region and mounted components so that solder balls and the pitch between electrodes can be made smaller (Nagamatsu [0191]).
Regarding dependent claim 12, Yusa, as modified by Nagamatsu, further discloses the protrusion protrudes from the first groove in a line-width direction of the first circuit wiring to extend along the surface of the first resin layer, wherein a length of a portion of the protrusion that protrudes from the first groove in the line-width direction as measured along the surface of the first resin layer is not larger than 30% of a line width of the first circuit wiring (as shown in Nagamatsu FIG. 26, a lateral length of protrusion 1244 is less than 30% of the width of wiring; please also refer to the preceding figure).
Regarding dependent claim 13, Yusa, as modified by Nagamatsu, further discloses a ratio of a film thickness of the plating film of the first circuit wiring to a line width of the first circuit wiring is 0.3 to 4 (as shown in Nagamatsu FIG. 26, the film thickness to line width ratio is roughly 1, falling within the claimed range; please also refer to the following figure); and the film thickness of the plating film of the first circuit wiring is 15 to 100 μm (the combined thickness of electrode 1240 and electrode forming region 1022 is greater than the thicknesses of first insulating layer 1030 (10 μm to 50 μm (Nagamatsu [0142])) and second insulating layer 1230 (10 μm to 50 μm (Nagamatsu [0175])) combined (20 μm to 100 μm) by a factor of 1.3 at most (due to the earlier determination that the height of the protrusion is at most 30% of the thickness of the plating film), resulting in a range of 26 μm to 130 μm, which has significant overlap with the claimed range). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
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Claims 4, 5, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yusa, and further in view of Yoshioka and Nagamatsu.
Regarding dependent claim 4, Yusa, as modified by Yoshioka, discloses in Yoshioka FIG. 2B the three-dimensional circuit part according to claim 1, but does not explicitly disclose a ratio of a surface roughness Rz of a portion of the wiring region other than the overlap region to the surface roughness Rz of the overlap region is not higher than 1/2 or a second resin layer provided on a portion of the surface of the first resin layer other than the overlap region to cover the first circuit wiring.
However, Yoshioka discloses a ratio of a surface roughness Ra of a portion of the wiring region other than the overlap region to the surface roughness Ra of the overlap region is not higher than 1/2 (the inverse of this ratio (RzPB/RzLB) is disclosed as 2 or greater (Yoshioka [0061])). While this does not explicitly disclose the claimed ratio of maximum height roughness Rz of the corresponding surfaces, one of ordinary skill in the art would recognize that the claimed ratio is statistically related to the ratio of average surface roughness Ra. That is, as the maximum height roughness Rz of a surface is reduced, the average roughness Ra is reduced due to the removal of outliers or reduction in the deviation of outliers from the mean. One of ordinary skill in the art would be motivated to try to reduce a ratio of a surface roughness Rz of a portion of the wiring region other than the overlap region to the surface roughness Rz of the overlap region because one can expect doing so would lead to an increase in the ratio RzPB/RzLB which Yoshioka teaches should be high (…even more preferably 10 or greater (Yoshioka [0061])). One could do so with a reasonable expectation of success, predictably resulting in an increased suppression of separation of the plating film from the wiring region (Yoshioka [0061]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to produce the three-dimensional circuit device of Yusa, as modified by Yoshioka, wherein a ratio of a surface roughness Rz of a portion of the wiring region other than the overlap region to the surface roughness Rz of the overlap region is not higher than 1/2 with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Additionally, in the same field of endeavor, Nagamatsu discloses in Nagamatsu FIG. 4B and associated text a second insulating layer provided on a portion of the surface of the first resin layer other than the overlap region to cover the first circuit wiring (insulating layer 150a covers portions of first conductor 162, which is part of wiring layer 140 other than the mount/overlap region, where insulating layer 150b is disposed). While it does not explicitly disclose the second insulating layer is resin, Nagamatsu discloses the use of resin in insulating layers, including the insulating resin layer 130 on which insulating layer 150a is formed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have “a second resin layer provided on a portion of the surface of the first resin layer other than the overlap region to cover the first circuit wiring”, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding dependent claim 5, Yusa, as modified by Yoshioka, discloses the three-dimensional circuit part according to claim 1, but does not explicitly disclose a second resin layer provided on a portion of the surface of the first resin layer other than the overlap region to cover the first circuit wiring; second circuit wiring including plating film provided on top of the second resin layer; and a second mounted component mounted on top of the second resin layer to electrically connect to the second circuit wiring.
However, in the same field of endeavor, Nagamatsu discloses in Nagamatsu FIG. 5B and associated text a second insulating layer provided on a portion of the surface of the first resin layer other than the overlap region to cover the first circuit wiring (insulating layer 150a covers portions of first conductor 162, which is part of wiring layer 140 other than the mount/overlap region, where insulating layer 150b is disposed); second circuit wiring including plating film provided on top of the second insulating layer (second conductor 164 and gold plating layer 166 formed on insulating layer 150a); and a second mounted component mounted on top of the second insulating layer to electrically connect to the second circuit wiring (second semiconductor module 200 is mounted on second conductor 164 and gold plating layer 166). While it does not explicitly disclose the second insulating layer is resin, Nagamatsu discloses the use of resin in insulating layers, including the insulating resin layer 130 on which insulating layer 150a is formed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have “a second resin layer provided on a portion of the surface of the first resin layer other than the overlap region to cover the first circuit wiring”, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding dependent claim 15, Yusa, as modified by Yoshioka, discloses the manufacturing method according to claim 14, but does not explicitly disclose before mounting the first mounted component, forming a second resin layer on a portion of the surface of the first resin layer other than the overlap region to cover the first circuit wiring, wherein the second resin layer is formed by shaping a second resin sheet on top of the first resin layer or applying a second resin liquid to the first resin layer.
However, in the same field of endeavor, Nagamatsu discloses in Nagamatsu FIG. 4B and 5D and associated text before mounting the first mounted component, forming a second insulating layer provided on a portion of the surface of the first resin layer other than the overlap region to cover the first circuit wiring (insulating layer 150a is formed over portions of first conductor 162 in Nagamatsu FIG. 4B, which is part of wiring layer 140 other than the mount/overlap region, where insulating layer 150b is disposed, and the step occurs before mounting semiconductor element 120 in Nagamatsu FIG. 5D). While it does not explicitly disclose the second insulating layer is resin, Nagamatsu discloses the use of resin in insulating layers, including the insulating resin layer 130 on which insulating layer 150a is formed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have “a second resin layer provided on a portion of the surface of the first resin layer other than the overlap region to cover the first circuit wiring”, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
While Nagamatsu does not explicitly disclose the second resin layer is formed by shaping a second resin sheet on top of the first resin layer or applying a second resin liquid to the first resin layer, Yoshioka teaches a known technique of forming a resin layer by applying liquid resin (base substrate H1 may be formed by pouring a material (Yoshioka [0081]-[0082]), which would be liquid resin since H1 is made of resin (Yoshioka [0071])) that is comparable to the base process/product. Yoshioka’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base manufacturing method of Yusa, as modified by Yoshioka, and further in view of Nagamatsu and the results would have been predictable and resulted in the second resin layer is formed by applying a second resin liquid to the first resin layer which results in an improved manufacturing method. Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention. The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Regarding dependent claim 16, Yusa, as modified by Yoshioka and Nagamatsu, discloses the manufacturing method of claim 15, but does not explicitly disclose the second resin layer is formed by applying the second resin liquid to the first resin layer. However, Yoshioka teaches a known technique of forming a resin layer by applying liquid resin (base substrate H1 may be formed by pouring a material (Yoshioka [0081]-[0082]), which would be liquid resin since H1 is made of resin (Yoshioka [0071])) that is comparable to the base process/product. Yoshioka’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base manufacturing method of Yusa, as modified by Yoshioka, and further in view of Nagamatsu and the results would have been predictable and resulted in the second resin layer is formed by applying a second resin liquid to the first resin layer which results in an improved manufacturing method. Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention. The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yusa, and further in view of Yoshioka and Yusa et al. (JP 2020025123 A, hereinafter Yusa 2).
Regarding dependent claim 18, Yusa, as modified by Yoshioka, discloses the manufacturing method according to claim 17. However, it does not explicitly disclose the forming of the first circuit wiring further includes: before illuminating the wiring region with the laser beam, forming a layer containing a catalytic-activity inhibitor agent on the surface of the first resin layer inclusive of the wiring region, wherein a portion of the layer containing the catalytic-activity inhibitor agent located on the wiring region is removed by illuminating the wiring region with the laser beam.
However, in the same field of endeavor, Yusa 2 discloses the forming of the first circuit wiring further includes: before illuminating the wiring region with the laser beam, forming a layer containing a catalytic-activity inhibitor agent on the surface of the first resin layer inclusive of the wiring region (a catalyst activity inhibiting layer (not shown) is formed on the surface of the resin layer 10, Yusa 2 [0056]), wherein a portion of the layer containing the catalytic-activity inhibitor agent located on the wiring region is removed by illuminating the wiring region with the laser beam (the catalyst activity inhibiting layer is removed from the laser-drawn portion, Yusa 2 [0056]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the manufacturing process of Yusa, as modified by Yoshioka, with the steps of applying and selectively removing a catalyst activity inhibiting layer to provide a manufacturing process for a three-dimensional circuit part that includes plating film only in the wiring region and prevents plating from forming elsewhere (Yusa 2 [0058]).
Regarding dependent claim 19, Yusa, as modified by Yoshioka, discloses the manufacturing method according to claim 14, wherein the forming of the first circuit wiring includes: forming a first groove in the wiring region through illumination with a laser beam or press working (groove 13 is formed by laser illumination (Yusa [0034])); forming a layer containing a catalytic-activity inhibitor agent on the surface of the first resin layer inclusive of the wiring region (a catalyst activity inhibitor is applied to the surface of the resin portion 10 including the grooves 13 and the uneven structure 12 (Yusa [0059])); providing the wiring region with an electroless-plating catalyst (an electroless plating catalyst is applied to the surface of the resin portion 10 (Yusa [0059]), including the grooves 13 and concave-convex structures 12 corresponding to the wiring region); and forming electroplating film on top of the electroless-plating film (the circuit pattern 20 may be formed by further laminating… electrolytic plating film on the electroless plating film (Yusa [0033])). Yusa, as modified by Yoshioka, does not explicitly disclose forming a second groove with a smaller width than the first groove by directing a laser beam into the first groove, forming electroless-plating film within the second groove by bringing an electroless-plating solution into contact with the wiring region provided with the electroless-plating catalyst.
However, in the same field of endeavor, Yusa 2 discloses forming a second groove with a smaller width than the first groove by directing a laser beam into the first groove (grooves 13 are cut by laser, resulting in increased depth in the roughened region, which has a smaller width than the first groove 13, as shown in Yusa 2 FIG. 2; please also refer to the following figure), and forming electroless-plating film within the second groove by bringing an electroless-plating solution into contact with the wiring region provided with the electroless-plating catalyst (an electroless plating catalyst is applied to the surface of the laser-drawn resin layer 10, and an electroless plating solution is brought into contact with the surface (Yusa [0056])).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the manufacturing method of Yusa, as modified by Yoshioka, and the steps of forming and plating of a second groove disclosed by Yusa 2 to provide a deeper wiring layer, which results in reduced resistance (Yusa 2 [0031]).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20090272562 A1, pertaining to a circuit board with roughened mounting region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Fri 8:30 am - 6:30 pm.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897