DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed 07/06/2026, in which: claim(s) 1, 6, 10, 22, 24, and 28 is/are amended; claim(s) 5, 7-9, 11, 18-20, 23, 25, and 29 is/are cancelled; claim(s) 30-31 is/are new; and the rejection of the claims are traversed. Claim(s) 1-4, 6, 10, 12-18, 21-22, 24, 26-28, and 30-31 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments filed 07/06/2026, with respect to amended claim(s) 1 and 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments with respect to the rejection(s) of claim(s) 6, as amended, and 31 have been fully considered but they are not persuasive.
Regarding Applicant’s arguments that Lin teaches away from the combination of Ishii, Chiu, Lin, and Hart to disclose the chip dicing configuration of claim 6 (see page 13), Lin was relied upon solely to disclose that a structure similar to Ishii’s terminal strip 40 was considered a chip. The combination was merely for definitional purposes, and no structural features of Lin were intended to be combined with Ishii, Chiu, or Hart. Additionally, no teaching of Lin to explicitly avoid dicing through metal lines has been found. Therefore, the way in which the chips of Lin were diced is irrelevant to the combination. Additionally, the motivation to combine the references as described to provide an increased degree of integration and to mitigate damage caused by charge accumulation in chip processing (Hart [0068]) overcomes any teaching away which might be present in Lin. While the new ground of rejection does not rely on Lin as applied in the prior rejection of record for any teaching or matter specifically challenged in this particular argument, Applicant will note that the references applied in the instant prior art rejection of claims 6 and 31 are similarly considered not to teach away from the dicing process and structures disclosed by Hart and/or any such teaching or suggestion is considered to be overcome by the advantages disclosed by Hart.
Regarding Applicant’s arguments that “Hart's scribe line metal connection (706) is a temporary, transient structure…. leaving no remaining structure in the final product” (see page 13), Examiner respectfully disagrees. As shown in Hart FIG. 9-11, portions of 910 and 704 remain in interposer regions 203 after dicing.
Regarding applicant’s argument that “Hart does not disclose or suggest that its severed metal layers 910-1/910-2 substantially surround any signal transmission metal region within a bonding surface configured for direct substrate-to-substrate bonding” (see page 13), Examiner agrees. However, Ishii is relied upon to disclose a ground region surrounding a signal transmission region, not Hart. Regardless of whether Hart’s metal layers 910 are redistribution layers or bonding surfaces is irrelevant, as the reference is primarily relied upon to provide structure and motivation for connecting the ground metal region disclosed by Ishii between chips, which results in the claimed structure.
Regarding Applicant’s arguments that “A person having ordinary skill in the art would have no technical motivation to combine Ishii and Hart because modifying Ishii's permanent continuous solid layer with Hart's temporary ESD line would fail to solve the dicing-induced mechanical delamination problem” (see page 14), obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the motivation to combine the references as described is to provide an increased degree of integration and to mitigate damage caused by charge accumulation in chip processing (Hart [0068]).
Applicant's arguments with respect to the rejection(s) of claim(s) 30 have been fully considered but they are not persuasive.
Regarding Applicant's argument that “combining Ishii with a direct bonding reference such as Takayuki would not yield the claimed invention”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Applicant’s allegation that “Ishii's architecture fundamentally relies on discrete bump connections between the packages and the terminal strip-eliminating the bumps would require a complete redesign of Ishii's structure, not a mere substitution of bonding technique”, assuming any redesign of Ishii’s structure would be necessary, to which Examiner respectfully disagrees, this does not preclude one of ordinary skill in the art from being motivated to use the superior bonding technique disclosed by Takayuki.
Applicant's arguments with respect to the rejection(s) of claim(s) 24, 26, and 28 have been fully considered but they are not persuasive.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, motivation is found in Takayuki page 3, which lists the benefits of direct bonding, including improved bond strength.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Applicant’s remarks state that the title has been amended, however, no specification replacement sheet has been filed, therefore the proposed amendment has not been entered. Additionally, the proposed title “BONDING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME” is still not descriptive. A plethora of bonding structures and their manufacturing methods are known in the art. A descriptive title would be one which distinguishes the instant application from others. For example, “DIRECT PIN-TO-PIN BONDING STRUCTURE WITH SHIELDED SIGNAL REGIONS”, or the like.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 10, 12-14, 16-17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii et al. (US 20100213592 A1, hereinafter Ishii), and further in view of Lee et al. (US 20210043557 A1, hereinafter Lee).
Regarding independent claim 1, Ishii discloses in Ishii FIG. 3, 4, and 6 and associated text a bonding structure comprising: a first substrate (semiconductor package 30A) including a first bonding surface (bottom surface 30Ab) including a first signal transmission metal region (pads 32 which connect to signal line conductors 43) and a first ground metal region (pads 32 which connect to GND conductor 41) insulated from the first signal transmission metal region (Portions of printed wiring board 31 are between pads 32 corresponding to the claimed transmission and ground metal regions. Printed wiring board 31 is formed of glass epoxy substrates, which is an insulating material (Ishii [0045]).); and a second substrate bonded to the first substrate (terminal strip 40A, bonded to semiconductor package 30A, as shown), the second substrate including a second bonding surface (top surface 40Aa) including a second signal transmission metal region (signal line conductors 43) and a second ground metal region (GND conductor 41) insulated from the second signal transmission metal region (signal line and GND conductors are insulated by insulator 45), wherein (a) the first signal transmission metal region and the second signal transmission metal region are bonded (the signal transmission metal regions as interpreted above are bonded, as shown); the first ground metal region and the second ground metal region are bonded (the ground metal regions as interpreted above are bonded, as shown); (b) the first signal transmission metal region is substantially surrounded by the first ground metal region in the first bonding surface (the pads 32 corresponding to the first ground metal region surround the pads 32 corresponding to first signal transmission metal regions, as the respective sets of pads 32 are interpreted above; see also the following annotated Ishii FIG. 6), and the second signal transmission metal region is substantially surrounded by the second ground metal region in the second bonding surface (signal line conductors 43 are surrounded by GND conductor 41, as shown in Ishii FIG. 4(b) especially); (c) the first signal transmission metal region comprises a plurality of first conductive signal connections (solder layers 33 on pads 32, corresponding to the first signal transmission metal region as described above), and the second signal transmission metal region comprises a plurality of second conductive signal connections (signal line conductor connection portions 43a of solder layer 47), the plurality of first and second conductive signal connections being bonded to each other (the signal transmission metal regions as interpreted above are bonded as shown); and (d) the first ground metal region comprises a plurality of first conductive ground connections (solder layers 33 on pads 32, corresponding to the first ground metal region as described above), and the second ground metal region comprises a plurality of second conductive ground connections (GND conductor connection portions 41a of solder layer 47), the plurality of first and second conductive ground connections being bonded to each other (the ground metal regions as interpreted above are bonded as shown). Ishii does not explicitly disclose the above limitations where the first and second conductive signal connections are signal transmission metal pins or the first and second conductive ground connections are ground metal pins.
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However, in the same field of endeavor, Lee discloses in Lee FIG. 20A and associated text metal pins (micro-pillars 34 and 570 are interpreted as metal pins, which are in both bonding surfaces). Additionally, one of ordinary skill in the art would recognize that Lee’s micro-pillars 34/570 perform the same function as Ishii’s connection portions 50 (which are formed of the aforementioned solder layers 33 and 47) in that each forms electrical connections between substrates. Further Lee discloses the use of pins as a suitable alternative for solder balls for forming electrical connections between substrates (Lee [0016]: “copper pillars or solder bumps…may be used for flip-chip bonding assembly”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute Lee’s micro-pillars 34/570 for Ishii’s solder layers, such that solder layers 33 and 47 are replaced by signal transmission metal pins and ground metal pins, since all the claimed elements were known in the prior art and one skilled in the art could have substituted the elements as claimed with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007).
The resulting structure of the combined references would be such that the plurality of first and second signal transmission metal pins being bonded to each other and the plurality of first and second ground metal pins being bonded to each other, since the pins are used as substitutions for solder layers 33 and 47, which are bonded to each other.
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Regarding dependent claim 2, Ishii, as modified by Lee, further discloses in Ishii FIG. 3 and 4(b) and associated text a total area of the first signal transmission metal region and the first ground metal region is equal to or greater than 50% of an area of the first bonding surface, and/or a total area of the second signal transmission metal region and the second ground metal region is equal to or greater than 50% of an area of the second bonding surface (signal line conductors 43 and GND conductor 41 have a combined area clearly greater than 50% of the top surface 40Aa, as shown).
Regarding dependent claim 3, Ishii, as modified by Lee, further discloses in Ishii FIG. 3 and 4(b) and associated text an area of the first or second ground metal region is larger than an area of the first or second signal transmission metal region (GND conductor 41 has a greater area than signal line conductors 43).
Regarding dependent claim 4, Ishii, as modified by Lee, further discloses in Ishii FIG. 3 and associated text an insulating surface of the first bonding surface and an insulating surface of the second bonding surface are not bonded to each other (insulating layer 34 and insulating layer 48 are not bonded, as shown).
Regarding dependent claim 10, Ishii, as modified by Lee, further discloses in Ishii FIG. 3 and associated text the first signal transmission metal region is disposed separately from the first ground metal region in the first bonding surface (the ground metal and the signal transmission metal regions of 30Ab, as interpreted above, are separate, as shown), the second signal transmission metal region is disposed separately from the second ground metal region in the second bonding surface (the ground metal and the signal transmission metal regions of 40Aa, as interpreted above, are separate, as shown), and wherein the first bonding surface includes an insulating surface at a separation portion between the first signal transmission metal region and the first ground metal region, and/or the second bonding surface includes an insulating surface at a separation portion between the second signal transmission metal region and the second ground metal region (surfaces of insulators 45 separate signal line conductors 43 and GND conductor 41).
Regarding dependent claim 12, Ishii, as modified by Lee, further discloses in Ishii FIG. 3 and associated text the bonding structure according to claim 10, wherein the first bonding surface includes a first insulating surface disposed between the first signal transmission metal region and the first ground metal region (insulating layer 34 is disposed between pads 32 which each connect to either signal line conductors 43 or GND conductor 41 (pads corresponding to the first signal transmission metal region and first ground metal region respectively)), the second bonding surface includes a second insulating surface disposed between the second signal transmission metal region and the second ground metal region (surfaces of insulators 45 are between signal line conductors 43 and GND conductor 41). Ishii does not explicitly disclose the first insulating surface and the second insulating surface are bonded to each other.
However, in the same field of endeavor, Lee discloses in Lee FIG. 19C, 19D, 20C, and 20D and associated text the first insulating surface and the second insulating surface are bonded to each other (insulating bonding layers 52 and 521, corresponding to the claimed insulating surfaces, of memory chips 251, corresponding to claimed substrates are bonded (Lin [0323])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the bonding structure of Ishii with the oxide-to-oxide direct bonding of Lin to provide an increased degree of integration and increased layer adhesion.
Regarding dependent claim 13, Ishii, as modified by Lee, further discloses in Ishii FIG. 3 and associated text the bonding structure according to claim 10, wherein the first bonding surface includes a first insulating surface disposed between the first signal transmission metal region and the first ground metal region (insulating layer 34 is disposed between pads 32 which each connect to either signal line conductors 43 or GND conductor 41 (pads corresponding to the first signal transmission metal region and first ground metal region respectively)), the second bonding surface includes a second insulating surface disposed between the second signal transmission metal region and the second ground metal region (surfaces of insulators 45 are between signal line conductors 43 and GND conductor 41), and the first insulating surface and the second insulating surface are not bonded to each other (insulating layer 34 is not bonded to insulators 45, as shown).
Regarding dependent claim 14, Ishii, as modified by Lee, further discloses in Ishii FIG. 4(b) and associated text the first and/or second signal transmission metal region includes a plurality of first and/or second signal transmission metal regions (a plurality of signal line conductors 43 are depicted), and the plurality of first and/or second signal transmission metal regions are surrounded by a single first and/or second ground metal region (the plurality of signal line conductors 43 are surrounded by the single GND conductor 41).
Regarding dependent claim 16, Ishii, as modified by Lee, further discloses in Ishii FIG. 4(b) and associated text the first and/or second ground metal region includes a plurality of first and/or second ground metal regions insulated from each other in a corresponding bonding surface (GND conductor 41 and VDD conductors 42 (which are also considered ground metal regions consistent with the applicant’s definition in [0018]) are insulated from one another by insulators 45).
Regarding dependent claim 17, Ishii, as modified by Lee, further discloses the plurality of first and/or second ground metal regions are connected to a ground and/or different power supplies (The GND conductor 41 is connected to ground potential (GND) as exemplary first potential. The VDD conductors 42 are connected to power supply potential (VDD) as exemplary second potential. (Ishii [0056])).
Regarding dependent claim 21, Ishii, as modified by Lee, further discloses in FIG. 2 and associated text an electronic element, an electronic circuit module, or an electronic device comprising the bonding structure according to claim 1 (semiconductor module 10 is a module comprising a variety of electrically connected forming in a current path (Ishii [0005]: current passes through a path extending from VDD to GND; semiconductor module 10 includes path 100 between VDD conductor 42 and GND conductor 41), therefore semiconductor module 10 is an electronic circuit module).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ishii, and further in view of Lee and Hart et al. (US 20150069577 A1, hereinafter Hart).
Regarding dependent claim 6, Ishii, as modified by Lee, discloses the bonding structure according to claim 1. They do not explicitly disclose the first substrate and the second substrate are chips cut from a wafer by dicing, along a boundary line of a chip region, and the first and second ground metal regions are ground metal regions formed by cutting the wafer along the boundary line located within a cut metal region, or are ground metal regions composed of peripheral metal regions formed along the boundary line by cutting the wafer along the boundary line defined within a non-metal part.
However, in the same field of endeavor, Hart discloses in Hart FIG. 9-11 and associated text chips cut from a wafer by dicing, along a boundary line of a chip region (interposer 203 may be diced from an interposer wafer and when dies are attached to the interposer after dicing, it is considered a chip-on-chip flow, therefore interposers 203 are chips (Hart [0046]), and are diced along perimeters of their chips (i.e., perimeters of 203-1, 203-2, etc.), interpreted as a boundary line of a chip region), and ground metal regions formed by cutting the wafer along the boundary line located within a cut metal region (patterned metal layers 910-1/910-2 is connected to Vss (ground) and is separated into metal layers and still remaining and considered ground metal regions in individual interposers 203-1/203-2 when metal connection 706 in scribe region 804 is severed (Hart [0095]-[0096])), or are ground metal regions composed of peripheral metal regions formed along the boundary line by cutting the wafer along the boundary line defined within a non-metal part (The alternative case is already detailed, however, ground metal regions, i.e. any region of interposers 203 connected to metal layer 910, which is connected to ground, as interpreted above, are composed of, inter alia, remaining portions of 910-1/910-2 in Hart FIG. 9 and/or portions of 704 within the interposers’ edges, which are interpreted as peripheral metal regions since they are at the periphery of their respective interposers. These periphery portions are formed by the dicing process detailed above along the perimeters of interposers 203, which are lines defined within wafer 700, which is interpreted as a non-metal part in that it does not comprise solely metal, e.g. substrate 905 is a semiconductor or dielectric (Hart [0094], [0064])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the bonding structure of Ishii with the grounded metal regions in a cut metal region of Hart to mitigate damage caused by charge accumulation in chip processing (Hart [0068]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ishii, and further in view of Lee and Nishida et al. (JP 2000150802 A, hereinafter Nishida).
Regarding dependent claim 15, Ishii, as modified by Lee discloses in Ishii FIG. 3 and 4(b) and associated text the bonding structure according to claim 1, wherein the first and/or second signal transmission metal region includes a plurality of first and/or second signal transmission metal regions (a plurality of signal line conductors 43 are depicted). They do not explicitly disclose the plurality of first and/or second signal transmission metal regions include at least one signal transmission metal region for transmitting an analog signal and at least one signal transmission metal region for transmitting a digital signal.
However, in the same field of endeavor, Nishida discloses in Nishida FIG. 1 and associated text the plurality of first and/or second signal transmission metal regions include at least one signal transmission metal region for transmitting an analog signal (analog signal pad 3) and at least one signal transmission metal region for transmitting a digital signal (digital signal pad 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the bonding structure of Ishii, as modified by Lee, with the dedicated analog and digital signal pads of Nishida as signal line conductors to provide the capability to transmit either kind of signal between bonded substrates.
Claims 22, 24, and 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii, and further in view of Lee and Takayuki (Mitsubishi Heavy Industries Technical Review Vol. 57 No. 3 (September 2020), hereinafter Takayuki).
Regarding independent claim 22, Ishii discloses in Ishii FIG. 2 and 4(b) and associated text a method of bonding a substrate, the method comprising: providing a first substrate (semiconductor package 30A) including a first bonding surface (bottom surface 30Ab) including a first signal transmission metal region (pads 32 which connect to signal line conductors 43) and a first ground metal region (pads 32 which connect to GND conductor 41) insulated from the first signal transmission metal region (Portions of printed wiring board 31 are between pads 32 corresponding to the claimed transmission and ground metal regions. Printed wiring board 31 is formed of glass epoxy substrates, which is an insulating material (Ishii [0045]).); providing a second substrate bonded to the first substrate (terminal strip 40A, bonded to semiconductor package 30A, as shown), the second substrate including a second bonding surface (top surface 40Aa) including a second signal transmission metal region (signal line conductors 43) and a second ground metal region (GND conductor 41) insulated from the second signal transmission metal region (signal line and GND conductors are insulated by insulator 45); electrically connecting the first signal transmission metal region and the second signal transmission metal region (the ground metal and the signal transmission metal regions as interpreted above are connected by connection portion 50, which is an electrical connection); and electrically connecting the first ground metal region and the second ground metal region (Path 100 indicates current flow from GND conductor 41 to a pad 32, corresponding to a first ground metal region, through connection portion 50. Therefore, connection portion 50 is conductive and electrically connects the ground metal regions.), wherein (a) the first signal transmission metal region is substantially surrounded by the first ground metal region in the first bonding surface (the pads 32 corresponding to the first ground metal region surround the pads 32 corresponding to first signal transmission metal regions, as the respective sets of pads 32 are interpreted above; see also the following annotated Ishii FIG. 6), and the second signal transmission metal region is substantially surrounded by the second ground metal region in the second bonding surface (signal line conductors 43 are surrounded by GND conductor 41, as shown in Ishii FIG. 4(b) especially); (b) the first signal transmission metal region comprises a plurality of first conductive signal connections (solder layers 33 on pads 32, corresponding to the first signal transmission metal region as described above), and the second signal transmission metal region comprises a plurality of second conductive signal connections (signal line conductor connection portions 43a of solder layer 47), the plurality of first and second conductive signal connections being bonded to each other (the signal transmission metal regions as interpreted above are bonded as shown); and (c) the first ground metal region comprises a plurality of first conductive ground connections (solder layers 33 on pads 32, corresponding to the first ground metal region as described above), and the second ground metal region comprises a plurality of second conductive ground connections (GND conductor connection portions 41a of solder layer 47), the plurality of first and second conductive ground connections being bonded to each other (the ground metal regions as interpreted above are bonded as shown). Ishii does not explicitly disclose the above limitations where the first and second conductive signal connections are signal transmission metal pins or the first and second conductive ground connections are ground metal pins.
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However, in the same field of endeavor, Lee discloses in Lee FIG. 20A and associated text metal pins (micro-pillars 34 and 570 are interpreted as metal pins, which are in both bonding surfaces). Additionally, one of ordinary skill in the art would recognize that Lee’s micro-pillars 34/570 perform the same function as Ishii’s connection portions 50 (which are formed of the aforementioned solder layers 33 and 47) in that each forms electrical connections between substrates. Further Lee discloses the use of pins as a suitable alternative for solder balls for forming electrical connections between substrates (Lee [0016]: “copper pillars or solder bumps…may be used for flip-chip bonding assembly”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute Lee’s micro-pillars 34/570 for Ishii’s solder layers, such that solder layers 33 and 47 are replaced by signal transmission metal pins and ground metal pins, since all the claimed elements were known in the prior art and one skilled in the art could have substituted the elements as claimed with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007).
The resulting structure of the combined references would be such that the plurality of first and second signal transmission metal pins being bonded to each other and the plurality of first and second ground metal pins being bonded to each other, since the pins are used as substitutions for solder layers 33 and 47, which are bonded to each other.
Ishii does not explicitly disclose (d) before electrically connecting the first signal transmission metal region and the second signal transmission metal region and electrically connecting the first ground metal region and the second ground metal region, a surface of at least one of the first signal transmission metal region and the second signal transmission metal region is activated to form at least one activated signal transmission metal surface, and a surface of at least one of the first ground metal region and the second ground metal region is activated to form at least one activated ground metal surface; (e) said electrically connecting the first signal transmission metal region and the second signal transmission metal region includes bringing the at least one activated signal transmission metal surface into contact with another surface of the first or second signal transmission metal region, and said electrically connecting the first ground metal region and the second ground metal region includes bringing the at least one activated ground metal surface into contact with another surface of the first or second ground metal region; and (f) the activation includes a process selected from the group consisting of plasma treatment, ion bombardment, atom beam irradiation, radical irradiation, and electromagnetic wave irradiation.
Ishii teaches a base method of bonding a substrate of which the claimed invention can be seen as an improvement in that activation of the bonding surface can improve the bonding strength. Takayuki teaches a known technique of room-temperature bonding that is comparable to the base process comprising (d) before electrically connecting metal bonding materials, activating a surface of the bonding materials (Takayuki Figure 2 shows the activation step occurs before the bonding step where a second surface is shown to be put in contact with the first); (e) said electrically connecting the bonding materials includes bringing the activated surface into contact with another surface (The technique is disclosed to be applicable to bonding of metals (Takayuki pg. 6-7) and bringing metals into contact with one another is inherently a method of forming an electrical connection between them); and (f) the activation includes a process selected from the group consisting of plasma treatment, ion bombardment, atom beam irradiation, radical irradiation, and electromagnetic wave irradiation (activation is performed by Ar beam irradiation (Takayuki pg. 2, 6)).
Takayuki’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base bonding of the plurality of signal and ground metal regions of Ishii and the results would have been predictable and resulted in the method of bonding a substrate as claimed which results in a bonding structure with improved bonding strength among other listed benefits (Takayuki pg. 3).
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Regarding dependent claim 24, Ishii, as modified by Lee and Takayuki, further discloses said bringing the at least one activated signal transmission metal surface into contact with another surface of the first or second signal transmission metal region and said bringing the at least one activated ground metal surface into contact with another surface of the first or second ground metal region are performed in a vacuum (activation and bonding steps are performed in a vacuum of 10-6 Pa (Takayuki pg. 2, Figure 2)).
Regarding dependent claim 26, Ishii, as modified by Lee and Takayuki, discloses in Takayuki the method according to claim 22 wherein said electrically connecting the first signal transmission metal region and the second signal transmission metal region and said electrically connecting the first ground metal region and the second ground metal region are performed in an unheated manner or at room temperature (the entire disclosed process of Takayuki, including bringing bonding surfaces into contact (which forms an electrical connection in metals, on which the technique is applicable), occurs at room temperature (Takayuki pg. 2)).
Regarding dependent claim 27, Ishii, as modified by Lee and Takayuki, further discloses in Lee FIG. 20A-20B and associated text after electrically connecting the first signal transmission metal region and the second signal transmission metal region and electrically connecting the first ground metal region and the second ground metal region (micro-pillars 34 and 570 are brought into contact, constituting forming an electrical connection), heating the first substrate and the second substrate (micro-pillars 34 may be thermally compressed onto micro-pillars 570 (Lee [0315])).
Additionally, Applicant will note that it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the first and second substrates of the device would be heated during testing, use, and/or other subsequent manufacturing steps of the device by electrical currents in the conductive regions of the device. While Takayuki may appear to teach away from heating the first and second substrates (Takayuki 3), the type of heating to which Takayuki is referring is heating for bonding, which occurs at temperatures in the hundreds of degrees Celsius (Takayuki FIG. 1), not to the heating which occurs innately in use of electrical devices, which occurs at far lower temperatures during typical use. The heating of the first and second substrates by electrical currents in the conductive regions of the device is not sufficient to cause significant problems of thermal stress and distortion cited by Takayuki as reasons to avoid heating, therefore Takayuki is not considered to teach away from heating of this kind.
Regarding dependent claim 28, Ishii, as modified by Lee and Takayuki, discloses in Takayuki the method according to claim 22, wherein said electrically connecting the first signal transmission metal region and the second signal transmission metal region; and said electrically connecting the first ground metal region and the second ground metal region comprise: activating surfaces of the first signal transmission metal region, the second signal transmission metal region, the first ground metal region and the second ground metal region by irradiation of a particle beam (activation is performed by Ar beam irradiation (Takayuki pg. 2)) under a vacuum of equal to or less than 1 x10-5 Pascal (Pa) (activation and bonding steps are performed in a vacuum of 10-6 Pa (Takayuki pg. 2, Figure 2)); and bonding the first signal transmission metal region and the second signal transmission metal region and bonding the first ground metal region and the second ground metal region, as they remain active (activated surfaces are brought into contact with each other (Takayuki pg. 2)).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Ishii, and further in view of Takayuki.
Regarding independent claim 30, Ishii discloses in Ishii FIG. 2 and 4(b) and associated text a first substrate (semiconductor package 30A) having a first bonding surface (bottom surface 30Ab), the first bonding surface including a first signal transmission metal region (pads 32 which connect to signal line conductors 43) and a first ground metal region (pads 32 which connect to GND conductor 41) insulated from the first signal transmission metal region (Portions of printed wiring board 31 are between pads 32 corresponding to the claimed transmission and ground metal regions. Printed wiring board 31 is formed of glass epoxy substrates, which is an insulating material (Ishii [0045]).); and a second substrate bonded to the first substrate (terminal strip 40A, bonded to semiconductor package 30A, as shown), the second substrate including a second bonding surface (top surface 40Aa), the second bonding surface including a second signal transmission metal region (signal line conductors 43) and a second ground metal region (GND conductor 41) insulated from the second signal transmission metal region (signal line and GND conductors are insulated by insulator 45), wherein: (a) the first signal transmission metal region and the second signal transmission metal region are bonded to each other, and the first ground metal region and the second ground metal region are bonded to each other (the signal transmission and ground metal regions, as interpreted, are bonded to each other, as shown); (b) the first signal transmission metal region is substantially surrounded by the first ground metal region within the first bonding surface (the pads 32 corresponding to the first ground metal region surround the pads 32 corresponding to first signal transmission metal regions, as the respective sets of pads 32 are interpreted above; see also the following annotated Ishii FIG. 6), and the second signal transmission metal region is substantially surrounded by the second ground metal region within the second bonding surface (signal line conductors 43 are surrounded by GND conductor 41, as shown in Ishii FIG. 4(b) especially); and (c) each of the first ground metal region and the second ground metal region has a metal material formed or disposed substantially gaplessly or planarly over the entire region thereof (the pads 32 corresponding to the first ground metal region are substantially planar over the entire first ground metal region, which is interpreted as the regions of the pads 32 which connect to GND conductor 41; GND conductor 41, corresponding to second ground metal region is both substantially gapless and planar, as shown in Ishii FIG. 3-4). Ishii does not explicitly disclose the first signal transmission metal region and the second signal transmission metal region are directly bonded to each other, and the first ground metal region and the second ground metal region are directly bonded to each other without an intervening solder or bump.
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Ishii teaches a base method of bonding a substrate of which the claimed invention can be seen as an improvement in that activation of the bonding surface can improve the bonding strength. Takayuki teaches a known technique of room-temperature bonding that is comparable to the base process comprising metal regions are directly bonded to each other without an intervening solder or bump (Takayuki FIG. 10 shows copper films bonded to each other directly and without intervening structures).
Takayuki’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base bonding of the plurality of signal and ground metal regions of Ishii and the results would have been predictable and resulted in the method of bonding a substrate as claimed which results in a bonding structure with improved bonding strength among other listed benefits (Takayuki pg. 3).
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Ishii, and further in view of Lee, Takayuki, and Hart.
Regarding dependent claim 31, Ishii discloses the bonding structure according to claim 22. Ishii does not explicitly disclose the first substrate and the second substrate are chips cut from a wafer by dicing, along a boundary line of a chip region, and the first and second ground metal regions are ground metal regions formed by cutting the wafer along the boundary line located within a cut metal region, or are ground metal regions composed of peripheral metal regions formed along the boundary line by cutting the wafer along the boundary line defined within a non-metal part.
However, in the same field of endeavor, Hart discloses in Hart FIG. 9-11 and associated text chips cut from a wafer by dicing, along a boundary line of a chip region (interposer 203 may be diced from an interposer wafer and when dies are attached to the interposer after dicing, it is considered a chip-on-chip flow, therefore interposers 203 are chips (Hart [0046]), and are diced along perimeters of their chips (i.e., perimeters of 203-1, 203-2, etc.), interpreted as a boundary line of a chip region), and ground metal regions formed by cutting the wafer along the boundary line located within a cut metal region (patterned metal layers 910-1/910-2 is connected to Vss (ground) and is separated into metal layers and still remaining and considered ground metal regions in individual interposers 203-1/203-2 when metal connection 706 in scribe region 804 is severed (Hart [0095]-[0096])), or are ground metal regions composed of peripheral metal regions formed along the boundary line by cutting the wafer along the boundary line defined within a non-metal part (The alternative case is already detailed, however, ground metal regions, i.e. any region of interposers 203 connected to metal layer 910, which is connected to ground, as interpreted above, are composed of, inter alia, remaining portions of 910-1/910-2 in Hart FIG. 9 and/or portions of 704 within the interposers’ edges, which are interpreted as peripheral metal regions since they are at the periphery of their respective interposers. These periphery portions are formed by the dicing process detailed above along the perimeters of interposers 203, which are lines defined within wafer 700, which is interpreted as a non-metal part in that it does not comprise solely metal, e.g. substrate 905 is a semiconductor or dielectric (Hart [0094], [0064])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the bonding structure of Ishii with the grounded metal regions in a cut metal region of Hart to mitigate damage caused by charge accumulation in chip processing (Hart [0068]).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 5902118 A, further pertaining to the use of vertical contact pins in interconnections between substrates.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu: 8:30 am - 6:30 pm.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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