DETAILED ACTION
Claim Objections
1. Claims 47, 48, 55 are objected to because of the following informalities:
In claim 47, line 2, “the first and second device” should be changed to “the first and second devices”
In claim 48, line 2, “the first and second device” should be changed to “the first and second devices”
In claim 55, lines 1 - 4, “the substrate comprises a plurality of layers with etched conductive paths and a plurality of vias associated therewith for making operative interconnections between the first and second devices and one or more components of the thermal barrier” should be changed “the operative interconnections between one or more components of the thermal barrier” because “the substrate comprises a plurality of layers with etched conductive paths and a plurality of vias associated therewith for making operative interconnections between the first and second devices” in claim 55 is redundant from claim 1 wherein the claim 1 comprises “a substrate having a plurality of layers with etched conductive paths and a first plurality of vias associated therewith for making operative interconnections between devices”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 40 – 43, 45 – 51, 53 - 55 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (9391046).
With regard to claim 40, Park et al. disclose a system (a system including active devices 124, 212) in a Package apparatus (for example, see fig. 8), comprising:
a substrate (referred to as “A” by examiner’s annotation shown in fig. 8 below; wherein the substrate “A” including layers 142, 148, 158) having a plurality of layers with etched conductive paths (the conductive layers 150 are formed over the exposed substrate 142 and conductive vias 146 using a patterning; for example, column 8, lines 37 – 39; wherein the patterning method inherently having an etch step) and a first plurality of vias (146) associated therewith for making operative interconnections between devices (138, 142) mounted on the substrate (A);
a first active device (referred to as “124A” by examiner’s annotation shown in fig. 8 below) mounted in a first area (a left area of fig. 8) of the substrate (A) and having a first maximum operating temperature (the first active device inherently having any operating temperature functioning as a first maximum operating temperature);
a second active device (referred to as “124B” by examiner’s annotation shown in fig. 8 below) mounted in a second area (a right area of fig. 8) of the substrate (A) and having a second maximum operating temperature (the second active device inherently having any operating temperature functioning as a second maximum operating temperature); and
a thermal barrier (a structure, including the discrete passive components 212 can be resistors, functioning as a thermal barrier; for example, column 8, lines 2 - 6) that thermally isolates the first device (124A) from the second device (124B).
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With regard to claim 41, Park et al. disclose the thermal barrier (the structure, including the discrete passive components 212, fig. 8 or conductive components 162, fig. 7 can be resistors, functioning as a thermal barrier; for example, column 8, lines 2 - 6) is comprised of a plurality of components selected from surface-mount resistors (212).
With regard to claim 42, Park et al. disclose the plurality of components (212, fig. 8 or 162, fig. 7) are arranged in one array (for example, figs. 4e, 7, 8).
With regard to claim 43, Park et al. disclose the one array comprise one or more of two or more rows of components (162, fig. 4e).
With regard to claim 45, Park et al. disclose the thermal barrier (the structure, including the discrete passive components 212, fig. 8 or conductive components 162, fig. 7 can be resistors, functioning as a thermal barrier; for example, column 8, lines 2 - 6) is mounted on an upper surface (a top surface) of the substrate (A).
With regard to claim 46, Park et al. disclose a plurality of connection elements (182, 160) on a bottom surface of the substrate (A), wherein the thermal barrier comprises one or more additional vias (referred to as “146A” by examiner’s annotation shown in fig. 8 below) extending from a top surface of the substrate (A) to the bottom surface of substrate (A), and wherein at least one of the additional vias (A) forms a thermal junction with at least one of the connection elements (182, 160) in an intersection at the bottom surface of the substrate (A).
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With regard to claim 47, Park et al. disclose an encapsulant (layers 180 functioning as an encapsulant) formed over at least the first and second devices (124A, 124B).
With regard to claim 48, Park et al. disclose the thermal barrier comprises a gap (referred to as “G” by examiner’s annotation shown in fig. 8) in the encapsulant (layers 180 functioning as an encapsulant) between the first and second devices (124A, 124B).
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With regard to claim 49, Park et al. disclose a first heat sink (a heat spreader 194, forming as a sink, functioning as a first heat sink), wherein the first heat sink (194) is located above the first active device (124A), and is not below (not directly under) the second device (124B).
With regard to claim 50, Park et al. disclose the first heat sink (194) is also located above the thermal barrier (the structure, including the discrete passive components 212 can be resistors, functioning as a thermal barrier; for example, column 8, lines 2 - 6); or the first heat sink (referred to as “174A” by examiner’s annotation shown in fig. 8 below; wherein the conductive layer 174A forming in the holes functioning as a sinks) is also located above the thermal barrier (the structure, including the discrete passive components 212 can be resistors, functioning as a thermal barrier; for example, column 8, lines 2 - 6).
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With regard to claim 51, Park et al. disclose a second heat sink (referred to as “174b” by examiner’s annotation shown in fig. 8 below; wherein the conductive layer 174B forming in the holes functioning as a sinks), wherein the second heat sink is located above the second active device (124B), and is not above the first device (124A).
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With regard to claim 53, Park et al. disclose the thermal barrier comprises a gap (referred to as “146C” by examiner’s annotation shown in fig. 8) in one or more conductive traces (150, 160) in the substrate (A) between the first and second active devices (124A, 124B).
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With regard to claim 54, Park et al. disclose the thermal barrier comprises a gap (referred to as “146C1” by examiner’s annotation shown in fig. 8) in a ball grid array (182) on a bottom surface of the substrate (A).
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With regard to claim 55, Park et al. disclose the substrate (referred to as “A” by examiner’s annotation shown in fig. 8 below; wherein the substrate “A” including layers 142, 148, 158) having a plurality of layers with etched conductive paths (the conductive layers 150 are formed over the exposed substrate 142 and conductive vias 146 using a patterning; for example, column 8, lines 37 – 39; wherein the patterning method inherently having an etch step) and a first plurality of vias (146) associated therewith for making operative interconnections between devices (138, 142) mounted on the substrate (A) and one or more components (212) of the thermal barrier (the structure, including the discrete passive components 212 can be resistors, functioning as a thermal barrier; for example, column 8, lines 2 - 6).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 44, 52 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (9391046) in view of Wan et al. (11444003).
With regard to claim 44, Park et al. do not clearly disclose the first device generates more heat than the second device.
However, Wan et al. disclose the first device generates more heat than the second device. (for example, see claim 15 of Wan et al.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park et al.’s device to have the first device generates more heat than the second device as taught by Wan et al. in order to allow heat to be spread from the relatively much hotter processors to the lesser hot memory for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 52, Park et al. do not clearly disclose the first device is a processing element and the second device is a memory.
However, Wan et al. disclose the first device (chip type 1) is a processing element and the second device (chip type 2) is a memory. (for example, see fig. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park et al.’s device to have the first device is a processing element and the second device is a memory as taught by Wan et al. in order to perform high efficiency of the memory device package and enhance a high dissipation efficiency, as is known to one of ordinary skill in the art.
6. Claim(s) 56 - 58 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (9391046) in view of Lee et al. (11610871).
With regard to claims 56, 57, Park et al. do not clearly disclose at least one marking on an exterior surface of the apparatus identifying one or more locations for measuring operational temperatures of the apparatus wherein the marking is on an exterior surface of the apparatus at the location of the second device.
However, Lee et al. disclose at least one marking (150) on an exterior surface of the apparatus (fig. 5) inherently identifying one location and wherein the marking (150) is on an exterior surface of the apparatus (fig. 5) at the location of the second device (210a-1). (for example, see fig. 5 of Lee et al.).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park et al.’s device to have at least one marking on an exterior surface of the apparatus identifying one or more locations and wherein the marking is on an exterior surface of the apparatus at the location of the second device as taught by Lee et al. in order to use for identification of the package, and outer boundaries of the upper package on the lower package for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. It would have been obvious to one of ordinary skill in the art to form at least one marking (150) for measuring operational temperatures of the apparatus
because the final structure after the incorporating references of Park et al. and Lee et al. is formed the same as that of applicant, thus the final structure has the same results “for measuring operational temperatures of the apparatus” as the claimed invention.
With regard to claim 58, Lee et al. disclose the second active device (210-1) is the most temperature sensitive component (CMOS sensor 210-1 functioning as a temperature sensitive component) of the SiP (for example, see column 6, lines 6 – 15, fig. 5).
7. Claim(s) 59 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (9391046) in view of Lee et al. (11610871) and further in view of Yamauchi (20020006151).
With regard to claim 59, Park et al. and Lee et al. do not clearly disclose the marking is a circular marking.
However, Yamauchi discloses the marking (15, 16) is a circular marking. (for example, see fig. 5 of Wan et al.).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park et al. and Lee et al.’s device to have the marking is a circular marking as taught by Yamauchi in order to enhance a high measurement efficiency of accuracy, as is known to one of ordinary skill in the art.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812