DETAILED ACTION
Response to Amendment
The amendment filed on 7/7/2026 under 37 CFR 1.312 has been entered. Corrections to the objections to Spec and Drawings are acknowledged. Status of claims: claims 1, 5, and 23 are amended. Claims 4, 6-8, 11, 13, 18-19 are cancelled. Claims 1-3, 5, 9-10, 12, 14-17, 20-28 are pending in the application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 9-10, 12, 14, 15, 17, 20, 27-28 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Choi (US 20180190750 A1).
Regarding Claim 1, Choi discloses (reproduced Choi Fig. 10 below) a display substrate (SUB, Fig. 9) comprising:
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a base substrate (SUB, Fig. 9); and
a plurality of pixel circuits (Fig. 3), wherein the plurality of pixel circuits is arranged on the base substrate in an array,
wherein the plurality of pixel circuits comprise a plurality of active patterns (SE, ACT, DE of respective transistors, Fig. 10), each of the plurality of active patterns extends along a first direction (DR2), the plurality of active patterns are arranged along a second direction (DR1), adjacent active patterns are spaced apart from each other in the second direction, and at least one of the plurality of active patterns comprises at least one disconnection position (annotated disconnection position) to form a plurality of active sub- patterns (annotated active sub-patterns) independent of each other (pixel circuits in respective columns separated from each other, adjacent active sub-patterns are not connected in the first direction in a layer where the plurality of active patterns are located ( adjacent active sub-patterns are not connected because they are separated by the disconnection position, annotated Fig. 10 above).
Regarding Claim 2 (Original): Choi discloses (reproduced Fig. 13 below)
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the substrate of claim 1 wherein two adjacent active sub-patterns are connected through a same connection portion (annotated connection portion) at the disconnection position, and/or two adjacent active sub-patterns are respectively connected to two different signal lines at the disconnection position.
Regarding Claim 3 (Currently Amended): Choi discloses (reproduced Fig. 10 above) the display substrate according to claim 1, and wherein the active pattern comprises a semiconductor region (ACT) and a conductor region (SE, DE), and the disconnection position of the active pattern is located in the conductor region.
Regarding Claim 5 (Currently Amended): Choi discloses (reproduced Fig. 10 above) the display substrate according to claim 3, wherein each of the plurality of pixel circuits comprises transistors (T1-T7, Fig. 3), and each of the transistors comprises a control electrode, a first electrode, and a second electrode (Fig. 3), the semiconductor region is configured to form a channel region (ACT, Fig. 10) of the transistor corresponding to the control electrode, and the conductor region (DE, SE, Fig. 10) is configured to form the first electrode and the second electrode of the transistor.
Regarding Claim 9 (Original): Choi discloses the display substrate according to claim 5, further comprising a first connection layer (Fig. 13),
wherein the first connection layer is provided on a side of the plurality of active patterns facing away from the base substrate (CNL on top of SE, DE, Fig.9), the first connection layer comprises a plurality of connection portions (annotated connection portions in Fig. 13 above), and at least one of the plurality of connection portions is configured to connect the transistors (¶ [0176]).
Regarding Claim 10 (Currently Amended): Choi discloses (annotated Fig. 10 above) the display substrate according to claim 9, wherein the conductor region comprises a first conductor portion (annotated conductor portion), and the first conductor portion is disconnected and comprises a first disconnection end (annotated Fig. 10) and a second disconnection end at the disconnection position (annotated Fig. 10),
the transistor comprises a first reset transistor (T4) and a threshold compensation transistor (T3),
the first disconnection end is served as a second electrode of the first reset transistor (DE4 is part of the first disconnection end of first sub-pattern), and the second disconnection end is served as a second electrode of the threshold compensation transistor (DE3 is part of the second disconnection end of second sub-pattern), and
the plurality of connection portions comprise a first connection portion (annotated first connection portion, Fig. 13 above), and the first connection portion is configured to connect the first disconnection end of the first conductor portion and the second disconnection end of the first conductor portion (CH2 on first sub-pattern of first connection portion connects to DE4 of first sub-pattern, (CH2 on second sub-pattern of first conductor portion connects to DE3 of second sub-pattern) wherein the transistors further comprise a driving transistor (T1, Fig. 3), and the first connection portion is connected to a control electrode of the driving transistor (CH1 connect to GE1 of T1, ¶ [0134]).
Regarding Claim 12 (Currently Amended): Choi discloses the display substrate according to claim 9, wherein the conductor region further comprises a second conductor portion (annotated Fig. 10-2 below),
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and the second conductor portion (comprising third and fourth disconnection ends) is disconnected and comprises a third disconnection end and a fourth disconnection end at the disconnection position (annotated Fig. 10-2 above),
the transistor further comprises a first light-emitting control transistor (T6) and a second reset transistor (T7, Fig. 3),
the third disconnection end is served as a second electrode (DE6) of the first light- emitting control transistor, and the fourth disconnection end is served as a second electrode (DE7) of the second reset transistor, and
the plurality of connection portions comprising second connection portion, and the second connection portion is configured to connect the third disconnection end of the second conductor portion and the fourth disconnection end of the second conductor portion (¶ [0178], CH7 connects to DE6 which is also DE7, DE6 and DE7 are integrally conformed within respective pixel circuit),
the display substrate further comprises a light-emitting element (OLED, Fig. 3), wherein the second connection portion is connected to the light-emitting element, the third disconnection end, and the fourth disconnection end, respectively (¶ [0156]).
Regarding Claim 14, Choi discloses (reproduced Fig. 10-2 above) the display substrate according to claim 9,
wherein the conductor region further comprises a third conductor portion (fifth and sixth disconnection ends combined), and the third conductor portion is disconnected and comprises a fifth disconnection end and a sixth disconnection end at the disconnection position,
the transistor further comprises a first reset transistor (T4) and a second reset transistor (T7, Fig. 3),
the fifth disconnection end is served as a first electrode (CH8 of respective disconnection end) of the first reset transistor, and the sixth disconnection end is served as a first electrode (CH8) of the second reset transistor (¶ [0145] disclosing CH8 of respective disconnection end connecting SE4 of respective pixel circuit, SE4 and SE7 are integrally conformed as in Fig. 3),
the display substrate further comprises a first conductive layer (Fig. 11) and a second conductive layer (Fig. 12), and the plurality of active patterns, the first conductive layer, and the second conductive layer are provided sequentially along a direction away from the base substrate (Fig. 8), and the plurality of connection portions comprise a fifth connection portion (AUX1, Fig. 13) and a sixth connection portion (AUX1, Fig. 13), and the second conductive layer comprises a first initialization signal line (IPL) and a second initialization signal line (also IPL), the first electrode of the first reset transistor is connected to the first initialization signal line through the fifth connection portion (via CH8), and the first electrode of the second reset transistor is connected to the second initialization signal line through the sixth connection portion (via CH8, ¶ [0177], SE4 and SE7 are integrally conformed).
Regarding Claim 17, Choi discloses (reproduced Fig. 10-2 above) the display substrate according to claim 1wherein active patterns corresponding to at least one column (a column of reproduced Fig. 10-2 above)of the pixel circuits are all provided with at least one disconnection position, and/or active patterns corresponding to at least one row of the pixel circuits are all provided with at least one disconnection wherein the active patterns corresponding to at least one column of the pixel circuits are all provided with at least one same disconnection position, and/or the active patterns corresponding to at least one row of the pixel circuits are all provided with at least one same disconnection position.
Regarding Claim 20 (Currently Amended): Choi discloses the display substrate of claim 9, wherein the transistor comprises a threshold compensation transistor (T3, Fig. 3), and the threshold compensation transistor is a single-gate transistor,
further comprising the display substrate further comprises a first conductive layer (Fig. 11) and a second conductive layer (Fig. 12),
wherein the first conductive layer is located between the plurality of active patterns and the first connection layer (Fig. 9 showing layers stack), and a control electrode (GE2, Fig. 11) of the threshold compensation transistor is located in the first conductive layer,
the second conductive layer is located between the first conductive layer and the first connection layer (layers stack, Fig. 9), the second conductive layer comprises a first power supply signal line (IPL, Fig. 12), and the first power supply signal line extends along the second direction (DR1), and
the transistor further comprises a driving transistor (T1, Fig. 3), and in the first direction, the first supply power signal line is located on a side of the control electrode of the threshold compensation transistor away from the driving transistor (Fig. 4).
Regarding claim 27, Choi discloses The display substrate according to claim 20, wherein the first conductive layer (Fig, 11) comprises a first capacitor portion, the first capacitor portion comprises a plurality of first capacitor sub-portions, and the plurality of first capacitor sub-portions are spaced apart from each other along the second direction, and the second conductive layer (Fig. 12) comprises a second capacitor portion, the second capacitor portion comprises a plurality of capacitor islands, the plurality of capacitor islands are spaced apart from each other, and each of the plurality of first capacitor sub-portions is provided opposite to at least part of one of the plurality of capacitor islands.
Regarding claim 28, Choi discloses A display device, comprising the display substrate according to claim 1 (¶ [0007]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20180190750 A1) in view of Heo (US 20200294448 A1).
Regarding claim 16, Choi discloses the display of claim 1. Choi is silent regarding the active patterns in at least two columns are not equal.
Heo discloses (Fig. 7A) a notch screen wherein the pixel circuits is removed in the hole area and thus the number of active patterns in at least two columns are not equal. Ordinarily skilled artisans would have adopted the pixel circuits as taught by Choi to the notch screen of Heo by removing portions of active patterns in a column that intersects with the hole area. Therefore, it would have been obvious to one of ordinary skill in the art before the filing date of the invention adjust some of the active patterns of Choi’s display to adapt to different display designs such as the notch screen as taught by Heo.
Allowable Subject Matter
Claim 15, 21-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 15 would be allowable for disclosing A display substrate, comprising: a base substrate; and a plurality of pixel circuits, wherein the plurality of pixel circuits are arranged on the base substrate in an array, wherein the plurality of pixel circuits comprise a plurality of active patterns, each of the plurality of active patterns extends along a first direction, the plurality of active patterns are arranged along a second direction, adjacent active patterns are spaced apart from each other in the second direction, and at least one of the plurality of active patterns comprises at least one disconnection position to form a plurality of active sub-patterns independent of each other, wherein at least one of the plurality of active patterns comprises adjacent disconnection positions spaced apart by at least one row of the pixel circuits. Choi as the prior art discloses the disconnection position of the active patterns occurs in every row of pixel circuits.
Claim 21 would be allowable for discussing a first power signal line in the first conductive layer comprising a main portion extending along the first direction and at least one isolated portion extending along the second direction, and a via hole surrounded by the main portion and an isolated portion is the via hole to connect the gate electrode of driving transistor to the first connection portion of the first connection layer.
Claim 22 would be allowable because it is dependent on claim 21.
Claim 23 would be allowable for disclosing a first power signal line of the second conductive layer and the first power signal line comprising a plurality of supply portions, and a via located between adjacent supply portions to connect the gate electrode of the driving transistor to the first connection portion of the first connection layer.
Claim 24 would be allowable because it is dependent on claim 23.
Claim 25 would be allowable for disclosing A display substrate, comprising: a base substrate; and a plurality of pixel circuits, wherein the plurality of pixel circuits are arranged on the base substrate in an array, wherein the plurality of pixel circuits comprise a plurality of active patterns, each of the plurality of active patterns extends along a first direction, the plurality of active patterns are arranged along a second direction, adjacent active patterns are spaced apart from each other in the second direction, and at least one of the plurality of active patterns comprises at least one disconnection position to form a plurality of active sub-patterns independent of each other, the active pattern comprises a semiconductor region and a conductor region, and the disconnection position of the active pattern is located in the conductor region, each of the plurality of pixel circuits comprises transistors, and each of the transistors comprises a control electrode, a first electrode, and a second electrode, the semiconductor region is configured to form a channel region of the transistor corresponding to the control electrode, and the conductor region is configured to form the first electrode and the second electrode of the transistor, the display substrate further comprises a first connection layer, wherein the first connection layer is provided on a side of the plurality of active patterns facing away from the base substrate, the first connection layer comprises a plurality of connection portions, and at least one of the plurality of connection portions is configured to connect the transistors, the display substrate further comprises a first conductive layer and a second conductive layer, wherein the first conductive layer, the second conductive layer, and the first connection layer are arranged sequentially along a direction away from the base substrate, the second conductive layer comprises a first power supply signal line, the first power supply signal line comprises a plurality of power supply portions, and the plurality of power supply portions are arranged along the second direction and spaced apart from each other, the conductor region comprises a first conductor portion, the transistor further comprises a first reset transistor, a threshold compensation transistor, and a driving transistor, and the first conductor portion is served as a second electrode of the first reset transistor and a second electrode of the threshold compensation transistor, and the plurality of connection portions comprise a first connection portion, a control electrode of the driving transistor is connected to the first conductor portion through the first connection portion at a first via hole, and the first via hole is located between adjacent power supply portions.
Claim 26 would be allowable because it is dependent on claim 25.
Response to Amendment
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot in view of new ground of rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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