DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 71 and 82 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arvelo (US 9298231 B2).
As to Claim 71, Arvelo discloses:
71. (Currently Amended) An apparatus comprising:
a dual in-line memory module socket (space between 216, 217, see Fig. 8B; col. 12, Lines 11-15 “the electronics card 212 may comprise, for instance, a dual-in-line memory module, which contains a plurality of electronic components to be cooled, such as dynamic random access memory (DRAM) chips and ASIC chips”);
a cold plate 216 associated with the dual in-line memory module socket (col. 12, Lines 32-34 “The first thermal spreader 216 and second thermal spreader 217 are sized and configured to sandwich electronics card 212 therebetween when coupled together”; Lines 50-52 “the first thermal spreader 216 includes a coolant-carrying channel 202 extending therethrough”);
a circuit board 211;
an electronic component 213 on the circuit board 211 (col. 12, Lines 23-27 “the electronics card 212 is shown to comprise a plurality of electronic components, such as memory controllers 213 and dynamic random access memories (DRAMs) 214, arrayed on opposite main surfaces or sides of a board or substrate 211 of electronics card 212”), the circuit board 211 and the electronic component 213 being parts of a dual in-line memory module to be inserted into the socket adjacent the cold plate 216 col. 12, Lines 11-15 “the electronics card 212 may comprise, for instance, a dual-in-line memory module, which contains a plurality of electronic components to be cooled, such as dynamic random access memory (DRAM) chips and ASIC chips”; disposed adjacent 216); and
a thermal interface material 219 covering the electronic component 213 such that the electronic component 213 is sealed from an environment of the circuit board 211 (at least a outer surface of 213 is sealed from an environment of board 211 by 219), the thermal interface material 219 dimensioned to extend from the electronic component 213 to a surface of the cold plate 216 without an intervening material between the thermal interface material 219 and the surface of the cold plate 216 (219 directly contacts 216; col. 12, Lines 35-37 “a memory controller thermal interface material 219 may be provided between memory controllers 213 and first thermal spreader 216”; Lines 38-43 “first thermal spreader 216 may include recesses 207 on a main surface thereof, which are sized and configured to accommodate the respective memory controller cards to ensure good thermal coupling between the first thermal spreader and the electronic components on the one side of electronics card 212”).
As to Claim 82, Arvelo discloses:
wherein the cold plate is a first cold plate 216 and further including a second cold plate 217 associated with the dual in-line memory module socket (between 216,217; thermal spreader 217 conducts heat to 216; col. 12-13, Lines 64-67 and 1-6 “that second thermal spreader 217 further includes thermally conductive extensions 241′, which (in one embodiment) are mechanically coupled via fasteners 205′ to thermally conductive extensions 241 of first thermal spreader 216, for instance, to facilitate thermal conduction of heat from second thermal spreader 217 to the thermally conductive extensions 241 of first thermal spreader 216, and thereby facilitate transfer of heat from second thermal spreader to the liquid coolant flowing through the fluidic and mechanical attachment mechanisms”), wherein a distance between the first cold plate 216 and the second cold plate 217 is less than a thickness of the circuit board 211 including the thermal interface material 219 (see Fig. 10E, distance between 216 and 217 is less than thickness of card 212 (e.g., 211 and 219)), the circuit board 211 to be received between the first cold plate 216 and the second cold plate 217 via an interference fit (board 211 of card 212 sandwiched between 216,217 and coupled via spring fasteners 205; col. 12, Lines 32-34 “The first thermal spreader 216 and second thermal spreader 217 are sized and configured to sandwich electronics card 212 therebetween when coupled together, for instance, via spring-biased fasteners 205”).
Claims 76-78 and 83 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe (JP H0567893 A). See previous PTO-892.
As to Claim 76, Watanabe discloses:
A method comprising:
applying a thermal interface material (resin 7b; see Fig. 3; Par. 0013 of attached translation “It is desirable that the resin 7b has high thermal conductivity”) over a first subset of electronic components (components 3a,3b) on a circuit board 2 (see Fig. 3, 7b covers components 3a,3b disposed on circuit board 2), the thermal interface material 7b in at least one of a liquid form or a gel form when being applied over the first subset of electronic components 3a,3b, the thermal interface material 7b to be spaced apart from a second subset of the electronic components (other components disposed on circuit board 2, not covered by resin) on the circuit board 2; and
allowing the thermal interface material 7b to cure through a curing process, the thermal interface material 7b to be a solid after the curing process (Par. 0012 “then resin 7b with good thermal conductivity is filled in so that it comes into contact with the housing and is then hardened”; 7b must be at least in liquid or gel form when it is filled in and before it is hardened), the solid thermal interface material 7b to encapsulate the first subset of electronic components (7b encapsulates 3a,3b).
As to Claim 77, Watanabe discloses:
wherein the curing process includes application of heat to the thermal interface material 7b (heat present when 7b is hardened).
As to Claim 78, Watanabe discloses:
further including flattening the thermal interface material 7b after the curing process through a planarization process (7b is at least flattened by housing 1).
As to Claim 83, Watanabe discloses:
wherein applying the thermal interface material 7b over the first subset of electronic components 3a,3b includes applying the thermal interface material 7b to the circuit board 2 (7b is at least indirectly applied to circuit board 2 via 7a and components).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 47-48 and 51 are rejected under 35 U.S.C. 103 as being unpatentable over Mayo (US 20140190930 A1) alone.
As to Claim 47, Mayo discloses:
An apparatus (circuit board module 200) comprising:
a circuit board (substrate 202; see Figs. 2A-2B);
a first electronic component 208, a second electronic component 210, and a third electronic component 212 carried by the circuit board 202 (208, 210, 212 on substrate 202), the first electronic component 208 distinct and spaced apart from the second electronic component 210 and the third electronic component 212 on the circuit board 202 (208 spaced from 210 and 212), the second electronic component 210 distinct and spaced apart from the first electronic component 208 and the third electronic component 212 on the circuit board 202 (210 spaced from 208 and 212), and the third electronic component 212 distinct and spaced apart from the first electronic component 208 and the second electronic component 210 (212 spaced from 208 and 210); and
an encapsulant (encapsulant of region 204) in contact with the circuit board 202 around the first electronic component 208 and the second electronic component 210, the encapsulant encapsulating the first electronic component 208 and the second electronic component 210 but not the third electronic component 212 (Par. 0034 “Region 204 can represent an area where encapsulant is applied to protect electrical components 208 and 210, while region 206 can represent an area where no encapsulant is included or where encapsulant is removed”).
Mayo does not disclose (in the present embodiment):
a thermal interface material in contact with the circuit board around the first electronic component and the second electronic component, the thermal interface material encapsulating the first electronic component and the second electronic component but not the third electronic component.
However, Mayo discloses (in another embodiment):
a thermal interface material 314 in contact with the circuit board around the first electronic component 308 (Par. 0037 “Various types of encapsulants can be used to accommodate the needs of different components included in circuit board module 300”; “Region 314 surrounding thermally active component 308 can be encapsulated using a thermally conductive encapsulant, such as an epoxy including a filler material designed to increase thermal conductivity or the like”);
in order to increase thermal conductivity for thermally active components (Par. 0037).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Mayo as further suggested by Mayo e.g., providing:
a thermal interface material in contact with the circuit board around the first electronic component and the second electronic component, the thermal interface material encapsulating the first electronic component and the second electronic component but not the third electronic component;
in order to increase thermal conductivity for thermally active components.
As to Claim 48, the obvious modification of Mayo alone does not disclose:
wherein the thermal interface material extends between a surface of the circuit board and at least a portion of the first electronic component facing the surface of the circuit board.
However, Mayo further discloses (in another embodiment):
wherein the thermal interface material (encapsulation 411; see Fig. 4B) extends between a surface of the circuit board 402 and at least a portion of the first electronic component 408 facing the surface of the circuit board 402 (411 between bottom of 408 and top of 402; Par. 0042 “component 408 can represent a flex cable, internal structural component, or any other component included in the electronic device”; “the thickness of encapsulation 411 is reduced in areas 412 between components 404. The reduced thickness can allow additional clearance for component 408, reducing the thickness of the device, while also allowing some structural support for component 408 from the remnant encapsulant 411 in areas 412”);
in order to reduce the thickness of the device and proving structural support for the component (Par. 0042).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Mayo in view of Mayo as further suggested by Mayo e.g., providing:
wherein the thermal interface material extends between a surface of the circuit board and at least a portion of the first electronic component facing the surface of the circuit board;
in order to reduce the thickness of the device and proving structural support for the component.
As to Claim 51, the obvious modification of Mayo alone discloses:
wherein the thermal interface material (encapsulant of region 204 of Figs. 2A-2B) is to be spaced apart from the third electronic component 212 (encapsulant of 204 is spaced from 212).
Claim 50 is rejected under 35 U.S.C. 103 as being unpatentable over Mayo (US 20140190930 A1) as applied to claim 47 above, and further in view of Selvidge (US 20200241609 A1).
As to Claim 50, the obvious modification of Mayo alone discloses:
the circuit board 202 and the first 208, second 210, and third 212 electronic components;
without an anti-scratch film between the thermal interface material (encapsulant of region 204) and the first 208 and second 210 electronic components (no anti-scratch film between 208,210 and encapsulant of 204).
Mayo does not disclose:
wherein the circuit board and the first, second, and third electronic components are parts of a dual in-line memory module to be selectively inserted into a socket adjacent a cold plate, the thermal interface material dimensioned to extend from the first and second electronic components to the cold plate.
However, Selvidge discloses:
wherein the circuit board and the first, second, and third electronic components are parts of a dual in-line memory module (DIMM cards 520; see Fig. 5, components of cards 520 correspond to components of 202 of Mayo) to be selectively inserted into a socket adjacent a cold plate (thermal plate 230; Par. 0032 “thermal plates 230 may be “cold plates””; Par. 0045 “DIMM cards 520 are inserted in a socket and make thermal contact, on each of two opposite sides, with thermal interfaces 220”; “Clips 240 keep the assemblies including the two thermal plates 230 and the two thermal interfaces 220 securely packed and in thermal contact with one another”), the thermal interface material 220 dimensioned to extend from the first and second electronic components 520 to the cold plate 230.
in order to enable cooling of a DIMM by transferring heat from a hot surface of the DIMM to the liquid coolant (Par. 0043).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Mayo in view of Mayo as further suggested by Selvidge e.g., providing:
wherein the circuit board and the first, second, and third electronic components are parts of a dual in-line memory module to be selectively inserted into a socket adjacent a cold plate, the thermal interface material dimensioned to extend from the first and second electronic components to the cold plate;
in order to enable cooling of a DIMM by transferring heat from a hot surface of the DIMM to the liquid coolant.
Claim 52 is rejected under 35 U.S.C. 103 as being unpatentable over Mayo (US 20140190930 A1) as applied to claim 47 above, and further in view of Chehade (US 20220316816 A1).
As to Claim 52, the obvious modification of Mayo alone discloses:
wherein the circuit board 202, the thermal interface material (encapsulant of region 204) to separate the first electronic component 208 and the second electronic component 210 from the outside (208 and 210 separated from outside environment by encapsulant of 204 region).
Mayo in view of Mayo does not disclose:
wherein the circuit board is to be immersed in an immersion cooling fluid, the thermal interface material to separate the first electronic component and the second electronic component from the immersion cooling fluid.
However, Chehade discloses:
wherein the circuit board (support board 30; see Fig. 8) is to be immersed in an immersion cooling fluid (Par. 0054 “FIG. 8 is a schematic diagram of a cooling system 2000 comprising an immersion cooling arrangement 2100. In this embodiment, the immersion cooling arrangement 2100 comprises a tank 2110 filled with a dielectric heat transfer fluid collecting thermal energy of the heat generating components 50 (shown on earlier Figures), the heat generating components 50 being disposed under respective heat sinks 700 and on a support board 30 (e.g. a Printed Circuit Board). As such, the heat generating components 50 and the heat sinks 700 are at least partially immersed in the dielectric heat transfer fluid”), the thermal interface material to separate the first electronic component and the second electronic component from the immersion cooling fluid (heat transfer fluid in tank 2110; in combination with Mayo, encapsulant of region 204 separates 208, 210 from heat transfer fluid of Chehade);
in order to provide cooling to the heat generating components by using dielectric heat transfer fluid to collect the thermal energy of the heat generating components 50 (Par. 0054).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Mayo in view of Mayo as further suggested by Chehade e.g., providing:
wherein the circuit board is to be immersed in an immersion cooling fluid, the thermal interface material to separate the first electronic component and the second electronic component from the immersion cooling fluid;
in order to provide cooling to the heat generating components by using dielectric heat transfer fluid to collect the thermal energy of the heat generating components.
Claims 53-54 and 81 are rejected under 35 U.S.C. 103 as being unpatentable over Mayo (US 20140190930 A1) as applied to claim 47 above, and further in view of Huang (US 20220293484 A1).
As to Claim 53, the obvious modification of Mayo alone does not disclose:
further including a heat sink disposed on an exterior surface of the thermal interface material, the first electronic component positioned between the circuit board and the heat sink, the thermal interface material positioned between the first electronic component and the heat sink.
However, Huang discloses:
further including a heat sink (21 of Fig. 2) disposed on an exterior surface of the thermal interface material (encapsulating body 19; Par. 0040 “The second heat sink 21 is mounted on a second top surface 192 of the encapsulating body 19”), the first electronic component (at least one semiconductor 13) positioned between the circuit board 10 and the heat sink 21 (13 is between 10 and 21), the thermal interface material 19 positioned between the first electronic component 13 and the heat sink 21 (19 is disposed between 13 and 21);
in order to effectively dissipate the heat of the semiconductor devices (Par. 0013)
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Mayo in view of Mayo as further suggested by Huang e.g., providing:
further including a heat sink disposed on an exterior surface of the thermal interface material, the first electronic component positioned between the circuit board and the heat sink, the thermal interface material positioned between the first electronic component and the heat sink;
in order to effectively dissipate the heat of the semiconductor devices/electronics.
As to Claim 54, the obvious modification of Mayo in view of Mayo and Huang discloses:
wherein the second electronic component (other 13 of Huang) is positioned between the circuit board 10 and the heat sink 21 (other 13 disposed between 10 and 21) and the thermal interface material 19 is positioned between the second electronic component (other 13) and the heat sink 21 (19 is depose between other 13 and 21; Huang).
As to Claim 81, the obvious modification of Mayo in view of Mayo and Huang discloses:
wherein a width of a base of the heat sink (21 of Huang) does not extend beyond a width of the thermal interface material 19 (width of 21 does not extend beyond 19 of Huang).
Claim 55 is rejected under 35 U.S.C. 103 as being unpatentable over Mayo (US 20140190930 A1) as applied to claim 47 above, and further in view of Hoffmeyer (US 20200411411 A1).
As to Claim 55, the obvious modification of Mayo in view of Mayo does not disclose:
wherein the thermal interface material is elastic.
However, Hoffmeyer discloses:
wherein the thermal interface material is elastic (Par. 0041 “The first layer 102 and the second layer 104 may each include a material from any of several known thermal interface materials, including polymeric elastomer materials”);
in order to provide a desired level of gap filling capability, reuse properties and inherent tackiness (Par. 0041).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Mayo in view of Mayo as further suggested by Hoffmeyer e.g., providing:
wherein the thermal interface material is elastic;
in order to provide a desired level of gap filling capability, reuse properties and inherent tackiness.
Claim 56 is rejected under 35 U.S.C. 103 as being unpatentable over Mayo (US 20140190930 A1) as applied to claim 47 above, and further in view of Arvelo (US 20140238640 A1).
As to Claim 56, the obvious modification of Mayo in view of Mayo does not disclose:
wherein the thermal interface material is a cured thermal gel material.
However, Arvelo discloses:
wherein the thermal interface material is a cured thermal gel material (Par. 0055 “The TIM material 126a-126n will be of sufficient elasticity to allow for compression without harming the VTMs, such as a fully-cured thermal gel”);
in order to provide a sufficiently elastic TIM to allow for compression without arming the components (Par. 0055).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Mayo in view of Mayo as further suggested by Arvelo e.g., providing:
wherein the thermal interface material is a cured thermal gel material;
in order to provide a sufficiently elastic TIM to allow for compression without arming the components.
Claim 73 is rejected under 35 U.S.C. 103 as being unpatentable over Arvelo (US 9298231 B2) as applied to claim 71 above, and further in view of Chehade (US 20220316816 A1).
As to Claim 73, Arvelo does not disclose:
wherein the circuit board is to be immersed in an immersion cooling system.
However, Chehade discloses:
wherein the circuit board 30 is to be immersed in an immersion cooling system (Par. 0054 “FIG. 8 is a schematic diagram of a cooling system 2000 comprising an immersion cooling arrangement 2100. In this embodiment, the immersion cooling arrangement 2100 comprises a tank 2110 filled with a dielectric heat transfer fluid collecting thermal energy of the heat generating components 50 (shown on earlier Figures), the heat generating components 50 being disposed under respective heat sinks 700 and on a support board 30 (e.g. a Printed Circuit Board). As such, the heat generating components 50 and the heat sinks 700 are at least partially immersed in the dielectric heat transfer fluid”);
in order to provide cooling to the heat generating components by using dielectric heat transfer fluid to collect the thermal energy of the heat generating components 50 (Par. 0054).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Arvelo as further suggested by Chehade e.g., providing:
wherein the circuit board is to be immersed in an immersion cooling system;
in order to provide cooling to the heat generating components by using dielectric heat transfer fluid to collect the thermal energy of the heat generating components.
Claim 74 is rejected under 35 U.S.C. 103 as being unpatentable over Arvelo (US 9298231 B2) as applied to claim 71 above, and further in view of Hoffmeyer (US 20200411411 A1).
As to Claim 74, Arvelo does not disclose:
wherein the thermal interface material is a resiliently compliant solid.
However, Hoffmeyer discloses:
wherein the thermal interface material is a resiliently compliant solid (Par. 0041 “The first layer 102 and the second layer 104 may each include a material from any of several known thermal interface materials, including polymeric elastomer materials”);
in order to provide a desired level of gap filling capability, reuse properties and inherent tackiness (Par. 0041).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Arvelo as further suggested by Hoffmeyer e.g., providing:
wherein the thermal interface material is a resiliently compliant solid;
in order to provide a desired level of gap filling capability, reuse properties and inherent tackiness.
Claim 75 is rejected under 35 U.S.C. 103 as being unpatentable over Arvelo (US 9298231 B2) as applied to claim 71 above, and further in view of Link (US 4342069 A).
As to Claim 75, Arvelo does not disclose:
wherein the electronic component includes one or more packaged semiconductor chips.
However, Link discloses:
wherein the electronic component includes one or more packaged semiconductor chips (Abstract “An integrated semiconductor package containing circuitry capable of supporting separately packaged semiconductors to achieve greater circuit board density and to allow separate semiconductor packages which cooperate with the supporting semiconductor package and die to be interchanged. The supporting die is interconnected electrically to lead pins and socket contacts using conductive circuitry compatible with the other semiconductor die”);
in order to allow for greater circuit board density and allow for separate semiconductor packages to be interchanged (Abstract).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Arvelo as further suggested by Link e.g., providing:
wherein the electronic component includes one or more packaged semiconductor chips;
in order to allow for greater circuit board density and allow for separate semiconductor packages to be interchanged.
Claim 79 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (JP H0567893 A) as applied to claim 76 above, and further in view of Igarashi (US 20230374189 A1).
As to Claim 79, Watanabe does not disclose:
further including attaching a heat sink to the thermal interface material after the curing process.
However, Igarashi discloses:
further including attaching a heat sink to the thermal interface material after the curing process (Par. 0134 “The method for bonding a heat generator and a heat sink via the thermally conductive resin composition is not particularly limited. For example, the electronic device can be obtained by bonding a heat generator and a heat sink using the hardened or semi-hardened thermally conductive resin composition heated in advance, or a heat generator and a heat sink are joined using the thermally conductive resin composition and then bonded by heating to obtain the electronic device”);
in order to thermally bond the heat generator and heat sink via the thermally conductive resin (Par. 0132).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the method of Watanabe as further suggested by Igarashi e.g., providing:
further including attaching a heat sink to the thermal interface material after the curing process;
in order to thermally bond the heat generator and heat sink via the thermally conductive resin.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW S MUIR whose telephone number is (571)270-1329. The examiner can normally be reached Monday - Friday 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash Gandhi can be reached at (571)272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW SINCLAIR MUIR/Examiner, Art Unit 2835
/Jayprakash N Gandhi/Supervisory Patent Examiner, Art Unit 2835