Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application JP 2021108104 filed on 06/29/2021 The foreign application is not in English. The certified copy of the foreign priority application JP 2021108104 has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application JP 2021108104 that is not in English, an English translation of the non-English language foreign JP 2021108104 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections – 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 recites the limitations “the wiring board assembly” in line two and "the lid assembly" in line six. There is insufficient antecedent basis for these limitations in the claim.
Examiner’s Note: For purposes of further examination this is being interpreted as reading “a wiring board assembly” and “a lid assembly.”
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Toyooka et. al. (US Pub. 20110293874), hereinafter referred to as Toyooka.
Regarding claim 1, Toyooka teaches a wiring board assembly (Toyooka, 100, Fig. 18) comprising a frame body (Toyooka, 50, Fig. 18); a sheet configured to close the frame body (Toyooka, 20A, Fig. 18); and a plurality of wiring boards adhered to one surface of the sheet (Toyooka, 10’, Fig. 18).
Claim 2 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sasaki et. al (JP 3783299) hereinafter referred to as Sasaki.
Examiner’s note: This is included in the supplied foreign references under JPH10112624.
Regarding claim 2, Sasaki teaches a lid assembly comprising (Sasaki, Fig 2): a frame body (Sasaki, 10, Fig. 2); a sheet configured to close the frame body (Sasaki, 14, Fig. 2) and a plurality of lids adhered to one surface of the sheet (Sasaki, 16, Fig. 2).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 8 and 9 are rejected under 35 U.S.C. 103 as being obvious over Toyooka in view of Sasaki.
Regarding claim 3, Toyooka teaches a wiring board assembly (Toyooka, 100, Fig. 18) comprising a frame body (Toyooka, 50, Fig. 18); a sheet configured to close the frame body (Toyooka, 20A, Fig. 18); and a plurality of wiring boards adhered to one surface of the sheet (Toyooka, 10’, Fig. 18).
Toyooka does not teach a lid assembly comprising: a second frame body; a second sheet configured to close the second frame body; and a plurality of lids adhered to one surface of the second sheet, wherein the plurality of lids are located on the one surface of the second sheet in correspondence with the plurality of wiring boards.
However, Sasaki teaches a lid assembly comprising (Sasaki Fig 2): a frame body (Sasaki, 10, Fig. 2); a sheet configured to close the frame body (Sasaki, 14, Fig. 2) and a plurality of lids adhered to one surface of the sheet (Sasaki, 16, Fig. 2). Additionally in Fig. 2, Sasaki depicts the lids facing the plurality of electrodes (Sasaki, 2 Fig. 2).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Toyooka and Sasaki to create a package set for creating reliable, sealed electronic components.
Regarding claim 8, modified Toyooka teaches the package set according to claim 3, wherein the first frame body and the plurality of wiring boards are located on an identical surface of the first sheet (Toyooka, Fig 18), and the second frame body and the plurality of lids are located on an identical surface of the second sheet (Sasaki, Fig 2).
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Regarding claim 9, modified Toyooka teaches the package set according to claim 3, wherein the first frame body of at least one of the first or second sheets is located on a surface opposite to the plurality of wiring boards or the plurality of lids (see diagram below).
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Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Toyooka and Sasaki as applied to claim above, and further in view of Watanabe et. al. (US Pub 20150287660), hereinafter referred to as Watanabe.
Regarding claim 4, modified Toyooka teaches the package set according to claim 3, but does not teach wherein an adhesive strength of the sheet of the wiring board assembly with respect to the plurality of wiring boards is different from an adhesive strength of the sheet of the lid assembly with respect to the plurality of lids.
However, Watanabe teaches a system wherein an adhesive strength of the substrate (Watanabe, 12, Fig. 4) with respect to the integrated circuits (Watanabe, 13, Fig. 4) is different than the adhesive strength of the first sheet member (Watanabe, 18, Fig. 4, paras. 46-54). While Watanabe does not state the adhesive strength of the substrate, the adhesive strength of the first sheet member is able to remove the integrated circuits from the substrate and is therefore stronger.
Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Toyooka and Sasaki with the teaching of Watanabe to create adhesive sheets with different adhesive strengths to allow for selective peeling (Watanabe, paras. 40-41, 53-54).
Regarding claim 5, modified Toyooka teaches the package set according to claim 3, wherein at least one of the first sheet assembly and the second sheet is a UV release sheet or a thermal release sheet (Watanabe, para. 54, As the first sheet member, a UV (ultraviolet) peeling film, a thermal peeling film, or the like can be used in addition to the foregoing materials. The UV peeling film is prepared by forming an adhesive layer made from a resin material which loses its adhesive force by UV irradiation over the base film. The thermal peeling film is prepared by forming an adhesive layer made from a resin material which loses its adhesive force by heat over the base film.)
Regarding claim 6, modified Toyooka teaches the package set according to claim 4, wherein a sheet having a higher adhesive strength among the first sheet and the second sheet is a UV release sheet or a thermal release sheet (Watanabe, para. 54)
Regarding claim 7, modified Toyooka teaches the package set according to claim 3, wherein the second sheet is a thermal release sheet (Watanabe, para. 54, the first sheet member (18, Fig. 4) of Watanabe is the second sheet, with the substrate (12, Fig 4) acting as the first sheet).
Claim(s) 13-15 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toyooka, Sasaki and Watanabe.
Regarding claim 13, Toyooka teaches a method for manufacturing an electronic component, the method comprising: preparing a wiring board assembly (Toyooka, 100, Fig. 18) comprising a first frame body (Toyooka, 50, Fig. 18), a first sheet configured to close the first frame body(Toyooka, 20A, Fig. 18), and a plurality of wiring boards adhered to one surface of the first sheet (Toyooka, 10’ Fig. 18, para 111-114).
Toyooka does not teach mounting each of a plurality of electronic elements on a respective wiring board of the plurality of wiring boards of the wiring board assembly; sealing the plurality of electronic elements; and peeling off the plurality of wiring boards from the first sheet.
However, Sasaki teaches mounting each of a plurality of electronic elements on a respective wiring board of the plurality of wiring boards of the wiring board assembly (Sasaki, Fig 2) and sealing the plurality of electronic elements (Sasaki, Fig 2, para. 15-17, see diagram below).
Sasaki does not teach and peeling off the plurality of wiring boards from the first sheet.
However, Watanabe teaches a method of peeling integrated circuits (Watanabe, 13, Fig. 4) from the substrate (Watanabe, 12, Fig. 4) using a first sheet member (Watanabe, 18, Fig. 4).
Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Toyooka, Sasaki and Watanabe to create a manufacturing process using peeling and package sets to increase the efficiency of component sealing and manufacturing yields.
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Regarding claim 14, Toyooka teaches a method for manufacturing an electronic component, the method comprising: preparing a wiring board assembly (Toyooka, 100, Fig. 18) comprising a first frame body (Toyooka, 50, Fig. 18), a first sheet configured to close the first frame body (Toyooka, 20A, Fig. 18), and a plurality of wiring boards adhered to one surface of the first sheet (Toyooka, 10’, Fig. 18).
Toyooka does not teach preparing a lid assembly comprising a second frame body, a second sheet configured to close the second frame body, and a plurality of lids adhered to one surface of the second sheet; mounting each of a plurality of electronic elements on a respective wiring board of the plurality of wiring boards of the wiring board assembly; overlapping the lid assembly on the wiring board assembly, the plurality of lids of the lid assembly being opposite to the plurality of wiring boards on which the plurality of electronic elements are mounted; sealing the electronic elements by bonding the plurality of lids to the plurality of wiring boards; peeling off the plurality of wiring boards from the first sheet; and peeling off the plurality of lids from the second sheet.
However, Sasaki teaches preparing a lid assembly comprising a second frame body (Sasaki, 10, Fig 2), a second sheet (Sasaki, 14, Fig. 2) configured to close the second frame body, and a plurality of lids (Sasaki, 16, Fig. 2) adhered to one surface of the second sheet;
mounting each of a plurality of electronic elements on a respective wiring board of the plurality of wiring boards of the wiring board assembly (Sasaki, Fig.2, see diagram above);
overlapping the lid assembly on the wiring board assembly, the plurality of lids of the lid assembly being opposite to the plurality of wiring boards on which the plurality of electronic elements are mounted (Sasaki Fig. 2, see diagram above); sealing the electronic elements by bonding the plurality of lids to the plurality of wiring boards (Sasaki, Fig. 2, para. 15-17, see diagram above).
Sasaki does not teach peeling off the plurality of wiring boards from the first sheet; and peeling off the plurality of lids from the second sheet.
However, Watanabe teaches a method of peeling integrated circuits (Watanabe, 13, Fig 4) from the substrate (Watanabe, 12, Fig. 4) using a first sheet member (Watanabe, 18, Fig. 4, para. 46). Additionally, Watanabe teaches peeling off the first sheet member from the IC onto a second sheet member (Watanabe, 19, Fig. 4, para. 46) that will form part of the seal.
Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Toyooka, Sasaki and Watanabe to create a manufacturing process using peeling and package sets to increase the efficiency of component sealing and manufacturing yields.
Regarding claim 15, modified Toyooka teaches the method according to claim 14, wherein the second sheet is a UV release sheet having a higher adhesive strength than the first sheet (Watanabe para. 54), and the method further comprises peeling off the plurality of lids from the second sheet by radiating UV after the plurality of wiring boards are peeled off from the first sheet (Watanabe, para. 54).
Regarding claim 18, modified Toyooka teaches, the method according to claim 13, wherein in the sealing of the plurality of electronic elements, the plurality of electronic elements and the plurality of wiring boards are collectively covered with a resin to seal the plurality of electronic elements (Watanabe, para. 59), and the method further comprises cutting the resin around the plurality of wiring boards (Watanabe, 46, Fig. 4, para. 79).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Toyooka and Sasaki as applied to claim 3 above, and further in view of Glenn et. al (US Patent 5981314), hereinafter referred to as Glenn.
Regarding claim 10, modified Toyooka teaches the package set according to claim 3, but does not teach wherein the first frame body and the second frame body each comprise an alignment portion configured to align a position of the wiring board assembly to a position of the lid assembly.
However, Glenn teaches a method of using alignment lines to clarify where each individual package is to be formed (Glenn, 56, 58, Fig. 3A).
Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined the teachings of Toyooka, Sasaki and Watanabe with the alignment lines of Glenn to ensure that the lids align properly with their matching component to ensure that each component is formed properly.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Toyooka and Sasaki as applied to claim 3 above, and further in view of Katayama et. al (US Pub. 20140091348), hereinafter referred to as Katayama.
Regarding claim 11, modified Toyooka teaches the package set according to claim 3, but does not teach, wherein any one of the first or second sheets comprises a hole at a position corresponding to each of the plurality of wiring boards or each of the plurality of lids.
However, Katayama teaches a package wherein each semiconductor element (Katayama, 26, Fig. 2(e)) has a through hole (Katayama, 21 Fig. 2(e)) corresponding to it through the support board (Katayama, 3 Fig 2(e)).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Toyooka and Sasaki with the through hole of Katayama to create through holes in the sheet material to aid in peeling the packages from the sheet (Katayama, para. 234-243).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Toyooka and Sasaki as applied to claim 3 above, and further in view of Shin etal (US Pub. 20030100142), hereinafter referred to as Shin.
Regarding claim 12, modified Toyooka teaches the package set according to claim 3, but does not teach wherein the first frame body comprises a notch or a through hole configured to expose a peripheral edge of the sheet.
However, Shin teaches vertically perforated slot (Shin, 111, Fig. 15G) which is used to allow a punch (Shin, 150, Fig. 15G) to strip off one side of cover lay tape (Shin, 120, Fig. 15G, para. 105).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Toyooka and Sasaki to create c package set wherein the first frame body comprised a notch to allow for easy removal of the sheet (Shin, para. 105).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Toyooka, Sasaki and Watanabe as applied to claim 14 above, and further in view of Katayama.
Regarding claim 16, modified Toyooka teaches the method according to claim 14, but does not teach wherein the first sheet or the second sheet comprises a hole at a position corresponding to each of the plurality of wiring boards or each of the plurality of lids, and the method further comprises peeling off the plurality of wiring boards or the plurality of lids from the first sheet or the second sheet by inserting a jig into the hole and pressing the plurality of wiring boards or the plurality of lids.
However, Katayama teaches a package wherein each semiconductor element (Katayama, 26, Fig. 2(e)) has a through hole (Katayama, 21 Fig. 2(e)) corresponding to it through the support board (Katayama, 3 Fig 2(e)) where a pressing member (Katayama, 14, Fig. 2(e)) presses through the through hole to peel off the LED’s (Katayama, 10, Fig. 2(e), para. 234-243)
Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Toyooka, Sasaki, and Watanabe with the through hole and pressing member of Katayama in order to efficiently peel the individual components from the adhesive layer (Katayama, para. 234-243).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Toyooka, Sasaki and Watanabe as applied to claim 14 above, and further in view of Shin.
Regarding claim 17, modified Toyooka teaches the method of claim 14, but does not teach wherein the first frame body or the second frame body comprises a notch or a through hole at a peripheral edge and the first sheet or the second sheet is adhered to the first frame body or the second frame body, the first sheet or the second sheet being exposed from the notch or the through hole, and the method further comprises peeling off the first sheet or the second sheet from the first frame body or the second frame body by gripping the first sheet or the second sheet from the notch or the through hole after the plurality of wiring boards or the plurality of lids are peeled off from the first sheet or the second sheet.
However, Shin teaches vertically perforated slot (Shin, 111, Fig. 15G) which is used to allow a punch (Shin, 150, Fig. 15G) to strip off one side of cover lay tape (Shin, 120, Fig. 15G, para. 105).
Therefore it Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Toyooka, Sasaki, and Watanabe with the teachings of Shin to create a notch or hole through the frame body to allow the sheet to be removed prior to singulating the individual components, thus improving process efficiency and reducing cost (Shin, para 105).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shim et. al. (US Pub. 20120199971) teaches a method of singulating the semiconductor packages using a saw blade or laser tool.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 7:30-5:00.
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/KIERAN M. CUNNINGHAM/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893