DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the second direction" in line 9. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation “the ion beam” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, it will be assumed that claim 13 should depend from claim 11.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 8, 10 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sekine et al. (JP 2020-43309A).
Regarding claim 1, Sekine teaches a transistor device, comprising a gate (Fig. 1, gate 24), a gate insulator (gate insulator 22), and a drift region (drift region 48) stacked with the body region (body region 44) in a first direction (up-down direction),
wherein the gate comprises a top surface (top of 24), a bottom surface (bottom of 24) arranged opposite to the top surface, and a side surface (side of 24) between the top surface and the bottom surface, the bottom surface is in the first direction of the top surface (Fig. 1), the gate insulator covers the bottom surface and at least a portion of the side surface of the gate (Fig. 1), the gate insulator comprises a sidewall (22b) and a bottom (22a), the body region covers a portion of the sidewall of the gate insulator (Fig. 1), and the gate insulator is extended from the surface of the drift region facing the body region to the drift region along the first direction (Fig. 1);
wherein the body region comprises a first subregion (44a), a second subregion (44b) and a third subregion (44c) arranged sequentially along a second direction (left-right direction), the second direction is perpendicular to the first direction and pointing to a direction away from the gate insulator (Fig. 1), wherein an average carrier concentration in the first subregion and an average carrier concentration in the third subregion are greater than an average carrier concentration in the second subregion (see Fig. 3, carrier/hole concentration in region 44b is lowest).
Regarding claim 5, Sekine teaches the transistor device according to claim 1, wherein a distance between the midline along the first direction of the second subregion and the sidewall of the gate insulator ranges from 5nm to 10nm (see translation page, under 500 nm, which encompasses 5-10 nm).
Regarding claim 8, Sekine teaches the transistor device according to claim 1, wherein base materials of the body region and the drift regions are silicon carbide (translation page 2).
Regarding claim 10, Sekine teaches a manufacturing method of a transistor device, comprising:
providing an initial body region (Fig. 1, body 44) and a drift region (Fig. 1, drift 48) stacked along a first direction (to-bottom direction);
forming a gate trench (Fig. 1, trench 20) inside the initial body region and the drift region (Fig. 1), wherein the gate trench passes through the initial body region from a surface of the initial body region backward away from the drift region in the first direction, and is extended to the drift region (Fig. 1); and
injecting a doped substance into the initial body region by an ion implantation process (see translation page 3) to obtain a buried trench body region, wherein the buried trench body region comprises a first subregion (44a), a second subregion (44b) and a third subregion (44c), the first subregion, the second subregion and the third subregion are sequentially arranged in the second direction (Fig. 1, left-right direction), the second direction is perpendicular to the first direction (Fig. 1) and pointing to a direction away from the gate trench (Fig. 1), wherein an average carrier concentration in the first subregion and an average carrier concentration in the third subregion are greater than an average carrier concentration in the second subregion (see Fig. 3).
Regarding claim 15, Sekine teaches the manufacturing method according to claim 10, wherein the base material of the initial body region and the drift region is silicon carbide (Sekine translation page 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 6-7, 9 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sekine.
Regarding claim 2, Sekine teaches the transistor device according to claim 1, but does not specifically teach wherein the average carrier concentration in the second subregion is 60% to 80% of the average carrier concentration in the third subregion.
Sekine does not specifically teach the exact ratio of concentration in the second subregion compared to the first and third subregion. However, the non-critical ratio could have been optimized through routine experimentation or calculation based on the materials/dopants used, and electrical characteristics desired. Additionally, because the concentration is a curve, it encompasses a wide range of potential values, and therefore can cover a larger range of specific values of difference. See MPEP 2144.05(II)(A).
Regarding claim 3, Sekine teaches the transistor device according to claim 2, but does not specifically teach wherein the average carrier concentration in the first subregion is 90% to 100% of the average carrier concentration in the third subregion.
Sekine does not specifically teach the exact ratio of concentration in the second subregion compared to the first and third subregion. However, the non-critical ratio could have been optimized through routine experimentation or calculation based on the materials/dopants used, and electrical characteristics desired. Additionally, because the concentration is a curve, it encompasses a wide range of potential values, and therefore can cover a larger range of specific values of difference. See MPEP 2144.05(II)(A).
Regarding claim 4, Sekine teaches the transistor device according to claim 2, wherein both the first subregion and the third subregion comprise a doped substance of a first conductive type (p-type, see Fig. 2), the drift region comprises a doped substance of a second conductive type (n-type, see Fig. 1), and the second subregion comprises a doped substance of the first conductive type and a doped substance of the second conductive type (see Fig. 2, 44b has both p and n-types).
Sekine does not specifically teach in the second subregion, the average dopant concentration of the doped substance of the second conductive type is from 20% to 40% of the average dopant concentration of the doped substance of the first conductive type. However, the non-critical ratio could have been optimized through routine experimentation or calculation based on the materials/dopants used, and electrical characteristics desired. Additionally, because the concentration is a curve, it encompasses a wide range of potential values, and therefore can cover a larger range of specific values of difference. See MPEP 2144.05(II)(A).
Regarding claim 6, Sekine teaches the transistor device according to claim 1, but does not specifically teach wherein a width of 6the second subregion along the second direction is 60% to 100% of a distance between the midline along the first direction of the second subregion and the sidewall of the gate insulator.
Sekine shows that the distances are approximately equal (Fig. 1), but does not specifically teach the values of the widths. However, the non-critical specific widths could have been optimized through routine experimentation or calculation based on the specific materials and electrical characteristics. See MPEP 2144.05(II)(A).
Regarding claim 7, Sekine teaches the transistor device according to claim 4, further comprising a dopant concentration rising region (see Fig. 2, area where n-dopant rises) in the drift region and is located aligning with the second subregion along the first direction (Fig. 2), wherein the average dopant concentration of the doped substance of the second conductive type (n-type) in the dopant concentration rising region is greater than the average dopant concentration of the doped substance of the second conductive type in the drift region (see Fig. 2, Cp vs Cxj average).
Regarding claim 9, Sekine teaches the transistor device according to claim 1, wherein a dimension of the gate insulator in the second direction is 2 to 5 times a dimension of the gate insulator in the first direction (see Fig. 2).
Sekine does not specifically teach the exact ratio of the bottom gate thickness compared to the side gate thickness. However, it would have been obvious to a person of skill in the art that the specific ratio could have been optimized through routine experimentation or calculation based on the specific materials and electrical characteristics of the device. See MPEP 2144.05(II)(A).
Regarding claim 19, Sekine teaches the transistor device according to claim 3, wherein both the first subregion and the third subregion comprise a doped substance of a first conductive type (Fig. 2, P-type), the drift region comprises a doped substance of a second conductive type (Fig. 2, n-type), and the second subregion comprises a doped substance of the first conductive type and a doped substance of the second conductive type (Fig. 2).
Sekine does not teach in the second subregion, the average dopant concentration of the doped substance of the second conductive type is from 20% to 40% of the average dopant concentration of the doped substance of the first conductive type. However, the non-critical ratio could have been optimized through routine experimentation or calculation based on the materials/dopants used, and electrical characteristics desired. Additionally, because the concentration is a curve, it encompasses a wide range of potential values, and therefore can cover a larger range of specific values of difference. See MPEP 2144.05(II)(A).
Regarding claim 20, Sekine teaches the transistor device according to claim 19, further comprising a dopant concentration rising region (Fig. 2, n-type rising area), wherein the dopant concentration rising region is in the drift region and located aligning with the second subregion along the first direction (Fig. 2), the average dopant concentration of the doped substance of the second conductive type in the dopant concentration rising region is greater than the average dopant concentration of the doped substance of the second conductive type in the drift region (Fig. 2).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Sekine in view of Kyogoku (U.S. Publication No. 2021/0296447)
Regarding claim 11, Sekine teaches the manufacturing method according to claim 10, but does not teach wherein the step of injecting a doped substance into the initial body region by the ion implantation process to obtain a buried trench body region comprises:
injecting an ion beam containing the doped substance into the initial body region through the gate trench in a direction at a non-zero angle to the second direction.
However, Kyogoku teaches a similar method including injecting an ion beam containing the doped substance into the initial body region through the gate trench in a direction at a non-zero angle to the second direction (see Kyogoku Fig. 9, dopants injected at non-zero angle through gate trench). It would have been obvious to a person of skill in the art at the time of the effective filing date that the dopants of Sekine could have been injected at a non-zero angle through the gate trench because this allows access to the vertical sidewalls that are doped through the gate trench opening.
Regarding claim 12, Sekine in view of Kyogoku teaches the manufacturing method according to claim 11, wherein the step of injecting an ion beam containing the doped substance into the initial body region through the gate trench in a direction at a non-zero angle to the second direction comprises:
injecting the ion beam into the initial body region at different angles during at least two ion injection processes (Kyogoku Fig. 9-10).
Regarding claim 13, Sekine teaches the manufacturing method according to claim 10 (Examiner note, assumed to be claim 11 for 112(b) purposes), wherein the angle between the ion beam and the second direction ranges from 30° to 60° (Koyogoku paragraph [0107]).
Regarding claim 17, Sekine teaches the manufacturing method according to claim 12, wherein the angle between the ion beam and the second direction ranges from 30° to 60° (Koyogoku paragraph [0107]).
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sekine in view of Guan et al. (CN 114068720)
Regarding claim 14, Sekine teaches the manufacturing method according to claim 10, but does not specifically teach wherein the temperature of the ion implantation process ranges from 500°C to 700°C.
However, Guan teaches that implantation into SiC requires higher temperatures because of the hardness of the material, over 500C (Guan translation page 2). It would have been obvious to a person of skill in the art at the time of the effective filing date that the implantation of Sekine would require a similar temperature because it is also done into SiC.
Regarding claim 16, Sekine teaches the manufacturing method according to claim 10, but does not specifically teach further comprising: after injecting a doped substance into the initial body region by an ion implantation process to obtain a buried trench body region, annealing the buried trench body region in the range of 1500°C to 1700°C.
However, Guan teaches that SiC implantation requires higher temperature annealing because of the hardness of the material, over 1500C (Guan translation page 2). It would have been obvious to a person of skill in the art at the time of the effective filing date that the annealing of Sekine would require a similar temperature because it is also done into SiC.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Sekine in view of Tanaka et al. (U.S. Publication No. 2023/0299150).
Regarding claim 18, Sekine teaches the manufacturing method according to claim 15, but does not teach further comprising: thermally oxidizing the gate trench to form a silicon oxide gate oxide on the inner wall of the gate trench.
However, Tanaka teaches that the gate oxide is formed by thermal oxidation (Tanaka paragraph [0039]). It would have been obvious to a person of skill in the art at the time of the effective filing date that thermal oxidation could have been used for the gate oxide of Sekine because it would have been a simple substitution of one oxide formation method for another with predictable results.
Conclusion
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899