Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/30/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7, 15, 16 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re Claim 7, 15, 16 and 18, the limitation of “the positive voltage applied from the outside” lacks antecedent basis. Limitation of “a state in which positive voltage is applied to the P-type semiconductor from outside” first listed in claim 2 and 5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Topping US 2019/0259896 in view of Bulja et al. US 2019/0346730.
Re claim 1, Topping teaches a semiconductor diode (fig3 and 4) comprising:
a P-type semiconductor (120 as NiO Eg~3.7eV, fig4, [56, 57, 148]);
an N-type semiconductor (122 as n-type Si Eg~1.12eV, fig4, [56, 58, 148]) having a band gap smaller than a band gap of the P-type semiconductor; and
Topping does not explicitly show an insulator provided between the P-type semiconductor and the N-type semiconductor, the insulator having a band gap larger than the band gap of the P-type semiconductor and the band gap of the N-type semiconductor, wherein a difference between the band gap of the P-type semiconductor and the band gap of the N-type semiconductor is 1 eV or higher, and a difference between the band gap of the P-type semiconductor and the band gap the insulator is 1 eV or lower.
Bulja teaches an insulator (108 as LiNbO3, fig1A, [16]) provided between the P-type semiconductor (110 as NiO, fig1A, [17]) and the N-type semiconductor (106, fig1A, [17]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Topping and Bulja to insert a LiNbO3 layer between 120 and 122 of Topping. The motivation to do so is to tune the optical characteristics and lower dielectric losses of the optoelectronic device (Bulja, [24]).
Topping in view of Bulja teaches the insulator (Topping, LiNbO3 Eg~3.9eV added between NiO Eg~3.7 eV 120 and n-Si 122 Eg~1.12eV, fig4) having a band gap larger than the band gap of the P-type semiconductor (Topping 120 as NiO Eg~3.7eV, fig4, [57, 148]) and the band gap of the N-type semiconductor (Topping, 122 as n-type Si Eg~1.12eV, fig4, [58,148]),
wherein a difference between the band gap of the P-type semiconductor (Topping 120 as NiO Eg~3.7eV, fig4, [57, 148]) and the band gap of the N-type semiconductor (Topping, 122 as n-type Si Eg~1.12eV, fig4, [58,148]) is 1 eV or higher (Topping, Eg(NiO) – Eg(n-Si) ~2.58eV), and a difference between the band gap of the P-type semiconductor (Topping 120 as NiO Eg~3.7eV, fig4, [57, 148]) and the band gap the insulator (Topping, LiNbO3 Eg~3.9eV added between 120 122, fig4) is 1 eV or lower (Topping, Eg(LiNbO3) – Eg(NiO) ~0.2eV).
Re claim 2 Topping modified above teaches the semiconductor diode according to claim 1, wherein in a state in which positive voltage is applied to the P-type semiconductor from outside of the semiconductor diode by using the N-type semiconductor as a reference, an energy level of a conduction band of the N-type semiconductor is set so as to be higher than an energy level of a conduction band of the P-type semiconductor, and an energy level of a valence band of the P-type semiconductor is set so as to be higher than an energy level of a valence band of the N-type semiconductor (Topping in view of Bulja teaches the structural limitations of the claim; therefore, the claimed properties are inherently possessed by Topping in view of Bulja. When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).).
Re claim 3, Topping modified above teaches the semiconductor diode according to claim 1,wherein an oxide semiconductor is used for the P-type semiconductor (Topping 120 as NiO Eg~3.7eV, fig4, [57, 148]), and an N-type single-element semiconductor (Topping, 122 as n-type Si Eg~1.12eV, fig4, [58,148]) or an N-type zero band-gap semiconductor is used for the N-type semiconductor.
Re claim 4, Topping teaches a semiconductor diode (fig3 and 4) comprising:
a P-type semiconductor (120 as p-type Si Eg~1.12eV, fig4, [56, 59, 148]);
an N-type semiconductor (122 as n-type TiO Eg~3.2eV, fig4, [56, 58, 148]) having a band gap larger than a band gap of the P-type semiconductor;
Topping does not explicitly show an insulator provided between the P-type semiconductor and the N-type semiconductor, the insulator having a band gap larger than the band gap of the P-type semiconductor and the band gap of the N-type semiconductor, wherein a difference between the band gap of the P-type semiconductor and the band gap of the N type semiconductor is 1 eV or higher, and a difference between the band gap of the N-type semiconductor and the band gap of the insulator is 1 eV or lower.
Bulja teaches an insulator (108 as LiNbO3, fig1A, [16]) provided between the P-type semiconductor (110, fig1A, [17]) and the N-type semiconductor (106 as TiO2, fig1A, [17]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Topping and Bulja to insert a LiNbO3 layer between 120 and 122 of Topping. The motivation to do so is to tune the optical characteristics and lower dielectric losses of the optoelectronic device (Bulja, [24]).
Topping in view of Bulja teaches the insulator (Topping, LiNbO3 Eg~3.9eV added between TiO Eg~3.2 eV 122 and p-Si 120 Eg~1.12eV, fig4) having a band gap larger than the band gap of the P-type semiconductor (Topping, 120 as p-type Si Eg~1.12eV, fig4, [56, 59, 148]) and the band gap of the N-type semiconductor (Topping, 122 as TiO Eg~3.2eV, fig4, [56, 58, 148]), wherein a difference between the band gap of the P-type semiconductor(Topping, 120 as p-type Si Eg~1.12eV, fig4, [56, 59, 148]) and the band gap of the N type semiconductor (Topping, 122 as TiO Eg~3.2eV, fig4, [56, 58, 148]) is 1 eV or higher (Topping, Eg(TiO) – Eg(p-Si) ~2.08eV), and
a difference between the band gap of the N-type semiconductor (Topping, 122 as TiO Eg~3.2eV, fig4, [56, 58, 148]) and the band gap of the insulator (Topping, LiNbO3 Eg~3.9eV added between 120 122, fig4) is 1 eV or lower (Topping, Eg(LiNbO3) – Eg(TiO) ~0.7eV).
Re claim 5, Topping modified above teaches the semiconductor diode according to claim 4, wherein in a state in which positive voltage is applied to the P-type semiconductor from outside of the semiconductor diode by using the N-type semiconductor as a reference, an energy level of a valence band of the P-type semiconductor is set so as to be lower than an energy level of a valence band of the N-type semiconductor, and an energy level of a conduction band of the N-type semiconductor is set so as to be lower than an energy level of a conduction band of the P-type semiconductor (Topping in view of Bulja teaches the structural limitations of the claim; therefore, the claimed properties are inherently possessed by Topping in view of Bulja. When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).).
Re claim 6, Topping modified above teaches the semiconductor diode according to claim 4,wherein a P-type single-element semiconductor (Topping, 120 as p-type Si Eg~1.12eV, fig4, [56, 59, 148]) or a P-type zero band-gap semiconductor is used for the P-type semiconductor, and an oxide semiconductor (Topping, 122 as TiO Eg~3.2eV, fig4, [56, 58, 148]) is used for the N-type semiconductor.
Re claim 7, Topping modified above teaches the semiconductor diode according to claim 1,wherein the positive voltage applied from the outside is 1 V or higher (Bulja, 4-10V, [27]; a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim).
Re claim 8, Topping modified above teaches the semiconductor diode according to claim 1,wherein a surface of the P-type semiconductor (Topping, 120, fig4, [56, 57, 148]) or the N-type semiconductor (Topping, 122, fig4, [56, 58, 148]) facing the insulator (Topping, LiNbO3 added between 122 and 120, fig4) is formed to have a shape with projections and depressions (Topping, fig4) or a porous shape.
Re claim 9, Topping modified above teaches the semiconductor diode according to claim 1,wherein a lithium-based perovskite compound such as LiNbO3 (Topping, LiNbO3 added between 122 and 120, fig4), Li3PS4, LiBH4, or the like or a manganese-based perovskite compound such as LaMnO3, etc. is used for the insulator.
Re claim 10, Topping modified above teaches the semiconductor diode according to claim 2, wherein an oxide semiconductor is used for the P-type semiconductor (Topping 120 as NiO Eg~3.7eV, fig4, [57, 148]), and an N-type single-element semiconductor or an N-type zero band-gap semiconductor is used for the N-type semiconductor (Topping, 122 as n-type Si Eg~1.12eV, fig4, [58,148]).
Re claim 11, Topping modified above teaches the semiconductor diode according to claim 5, wherein a P-type single-element semiconductor (Topping, 120 as p-type Si Eg~1.12eV, fig4, [56, 59, 148]) or a P-type zero band-gap semiconductor is used for the P-type semiconductor, and an oxide semiconductor is used for the N-type semiconductor (Topping, 122 as TiO Eg~3.2eV, fig4, [56, 58, 148]).
Re claim 12, Topping modified above teaches the semiconductor diode according to claim 11, wherein the positive voltage applied from the outside is 1 V or higher (Bulja, 4-10V, [27]; a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim).
Re claim 13, Topping modified above teaches the semiconductor diode according to claim 10, wherein the positive voltage applied from the outside is 1 V or higher (Bulja, 4-10V, [27]; a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim).
Re claim 14, Topping modified above teaches the semiconductor diode according to claim 2, wherein the positive voltage applied from the outside is 1 V or higher (Bulja, 4-10V, [27]; a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim).
Re claim 15, Topping modified above teaches the semiconductor diode according to claim 3, wherein the positive voltage applied from the outside is 1 V or higher (Bulja, 4-10V, [27]; a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim).
Re claim 16, Topping modified above teaches the semiconductor diode according to claim 4, wherein the positive voltage applied from the outside is 1 V or higher (Bulja, 4-10V, [27]; a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim).
Re claim 17, Topping modified above teaches the semiconductor diode according to claim 5, wherein the positive voltage applied from the outside is 1 V or higher (Bulja, 4-10V, [27]; a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim).
Re claim 18, Topping modified above teaches the semiconductor diode according to claim 6, wherein the positive voltage applied from the outside is 1 V or higher (Bulja, 4-10V, [27]; a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim).
Re claim 19, Topping modified above teaches the semiconductor diode according to claim 2, wherein a surface of the P-type semiconductor (Topping, 120, fig4, [56, 57, 148]) or the N-type semiconductor (Topping, 122, fig4, [56, 58, 148]) facing the insulator is formed to have a shape with projections and depressions (Topping, fig4) or a porous shape.
Re claim 20, Topping modified above teaches the semiconductor diode according to claim 3, wherein a surface of the P-type semiconductor (Topping, 120, fig4, [56, 57, 148]) or the N-type semiconductor (Topping, 122, fig4, [56, 58, 148]) facing the insulator is formed to have a shape with projections and depressions (Topping, fig4) or a porous shape.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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