DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/01/2023, 01/07/2026, and 01/23/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6-8, and 11 are rejected under U.S.C. 103 as being unpatentable over Hino et al.; US 2023/0036221 A1; 02/2020 in view of Kang et al.; US 2021/0098483 A1; 06/2020
Claim 1: Hino discloses a silicon carbide semiconductor device (Fig. 1: silicon carbide semiconductor device ), comprising: a semiconductor substrate ( Fig. 1: substrate 10 ) made of silicon carbide of a first conductivity type ( [0043] a semiconductor substrate 10 made of n-type low-resistance silicon carbide ); a drift layer formed on the semiconductor substrate, the drift layer being of the first conductivity type; a well region ( Fig. 1: well regions 30 ) formed in a surface layer ( as shown in Fig. 1 ) of the drift layer ( Fig. 1: drift layer 20 ), the well region being of a second conductivity type ( [0043] A pair of well regions 30, the regions being separated from each other in the cross-sectional diagram, made of p-type silicon carbide ); a source region ( Fig. 1: source region 40 ) formed in a surface layer of the well region ( [0044] A source region 40, which is made of n-type silicon carbide, is formed at the location a certain distance inwardly away from the side of the second separation region 22 toward the first separation region 21, the certain distance being a distance from the edge of the well region 30 on the side of the second separation region 22 ) and formed inside the well region ( Fig. 1 #30 ) in a plan view ( as shown in Fig. 1 ), the source region being of the first conductivity type ( as discussed above); a first separation region ( Fig. 1 first separation region 21 ) of the first conductivity type ( [0043] a drift layer 20 made of n-type silicon carbide ) that is a stripe ( as shown in Fig. 1 ), formed in a constant width ( as shown in Fig. 1 ), and formed in the well region ( Fig. 2 #21 is inside #30 ) in the plan view, a Schottky electrode ( Fig. 1 a first Schottky electrode 71 ) formed on and Schottky connected to the first separation region ( [0050] A first Schottky electrode 71 forming a Schottky connection with each of the first separation regions 21 is formed on a surface of the first separation region 21 ); a source electrode ( Fig. 1: source electrode 80 ) ohmic connected to the well region ( Fig. 1 #30 ) and the source region ( Fig. 1 #40 ), the source electrode ( [0051] The source electrode 80 to be connected to the ohmic electrodes 70, the first Schottky electrodes 71, and the contact regions 32 is formed on the surface of these ) being formed on the Schottky electrode ( as discussed above ); a second separation region ( Fig. 1: second separation region 22 ) formed adjacent to the well region ( as shown in Fig. 1 ), the second separation region being of the first conductivity type ( as discussed above ); and a gate electrode ( Fig. 1 gate electrode 60 ) formed on the well region through a gate insulating film ( [0052] A gate electrode 60 is formed on the gate insulating film 50 at least on the first well regions 30 ), the well region ( Fig. 1 #30 ) being formed between the source region ( Fig. 1 #40 ) and the second separation region ( Fig. 1 #22 ) in the plan view.
Hino does not appear to disclose the first separation region including a tip formed in a bent shape in the plan view;
However, Kang teaches the first separation region ( Fig. 5 #170L ) including a tip formed in a bent shape in the plan view ( [0061] A bent portion may be formed on a boundary between the first region 170U and the second region 170L depending on a change in width );
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kang with Hino to implement the first separation region including a tip formed in a bent shape in the plan view because this would implement an edge termination structure used to manage electric fields.
Claim 3: Hino and Kang disclose the silicon carbide semiconductor device according to claim 1 ( as discussed above ).
Hino teaches the first separation region ( Fig. 1 # 21 ) is not connected to its own first separation region ( as shown in Fig. 1 #21 does not loop back on itself ).
Claim 6: Hino and Kang disclose the silicon carbide semiconductor device according to claim 1 ( as discussed above ).
Hino does not appear to disclose the source region is not formed around the tip.
However, Kang teaches the source region is not formed around the tip ( [0061] The bent portion may be disposed in the substrate 101 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kang with Hino to implement the source region is not formed around the tip because this would protect the gate oxide from high electric field stress and reduce parasitic capacitances.
Claim 7: Hino and Kang disclose the silicon carbide semiconductor device according to claim 1 ( as discussed above ).
Hino teaches a plurality of well regions ( Fig. 1 pair of well regions 30 ) including the well region, wherein the plurality of well regions are formed spaced apart in the surface layer of the drift layer ( [0043] A pair of well regions 30, the regions being separated from each other in the cross-sectional diagram, made of p-type silicon carbide is provided near the surface of the drift layer 20 ).
Claim 8: Hino and Kang disclose the silicon carbide semiconductor device according to claim 1 ( as discussed above ).
Hino teaches a plurality of well regions ( Fig. 2 #30 ) including the well region, wherein the plurality of well regions each including the first separation region ( Fig. 2 #21 ) in the plan view are connected to each other ( [0050] As understood from FIG. 2, the well region 30 and some other portions, which appear to be more than one in FIG. 1, may be continuous behind the page of the cross-section drawing ) to be formed in the surface layer of the drift layer ( [0043] A pair of well regions 30, the regions being separated from each other in the cross-sectional diagram, made of p-type silicon carbide is provided near the surface of the drift layer 20 ).
Claim 11: Hino and Kang disclose the silicon carbide semiconductor device according to claim 1 ( as discussed above).
Hino teaches a contact region ( Fig. 1 contact region 35 ) enclosing the first separation region ( Fig. 1 #21 ) in the well region ( as shown in Fig. 2 ) and being higher in impurity concentration of the second conductivity type ( [0044] A contact region 35, which is made of p-type low-resistance silicon carbide, is formed near the surface of the well region 30 at the location further inside the source region 40 ) than the well region ( [0056] Also, by the same method, the contact region 35 is formed by implanting Al ions into a given region inside the well region 30 at an impurity concentration higher than that of the well region 30 ), the contact region being of the second conductivity type ( as discussed above ).
Claim 2 is rejected under U.S.C. 103 as being unpatentable over Hino et al.; US 2023/0036221 A1; 02/2020 in view of Kang et al.; US 2021/0098483 A1; 06/2020 as it relates to claim 1 and further in view of Choi; US 11488962 B2; 03/2021
Claim 2: Hino and Kang disclose the silicon carbide semiconductor device according to claim 1 ( as discussed above ).
Neither Hino nor Kang appear to disclose the tip of the first separation region is bent at an angle of 180 ̊.
However, Choi teaches the tip of the first separation region ( Fig. 4A #115 ;Col. 9 lines 40-42 The first and second supporter openings 115 and 116 may denote a cell separation area for separating the memory cells ) is bent at an angle of 180 ̊.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Choi with Hino and Kang to implement the tip of the first separation region is bent at an angle of 180 ̊ because this would implement a highly efficient edge termination structure to manage high electric fields.
Claims 4 and 5 are rejected under U.S.C. 103 as being unpatentable over Hino et al.; US 2023/0036221 A1; 02/2020 in view of Kang et al.; US 2021/0098483 A1; 06/2020 as it relates to claim 1 and further in view of Nagashima et al.; US 2015/0129947 A1; 02/2014
Claim 4: Hino and Kang disclose the silicon carbide semiconductor device according to claim 1 ( as discussed above ).
Neither Hino nor Kang appear to disclose an outer periphery of a bent portion of the tip of the first separation region is a curve.
However, Nagashima teaches an outer periphery of a bent portion ( Fig. 3B stopper film 26 ) of the tip of the first separation region is a curve ( as shown in Fig. 3B #26 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nagashima with Hino and Kang to implement an outer periphery of a bent portion of the tip of the first separation region is a curve because this approach can reduce electric field crowding and prevent premature dielectric field breakdown.
Claim 5: Hino and Kang disclose the silicon carbide semiconductor device according to claim 1 ( as discussed above ).
Neither Hino nor Kang appear to disclose the first separation region is bent three times or more in the plan view.
However, Nagashima teaches the first separation region ( Fig. 3B stopper film 26 ) is bent three times or more in the plan view ( as shown in Fig. 3B #26 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nagashima with Hino and Kang to implement the first separation region is bent three times or more in the plan view because this approach is used to achieve electric field management.
Claims 9 and 10 are rejected under U.S.C. 103 as being unpatentable over Hino et al.; US 2023/0036221 A1; 02/2020 in view of Kang et al.; US 2021/0098483 A1; 06/2020 as it relates to claim 1 and further in view of Hino et al.; US 2019/0181259 A1; 04/2016
Claim 9: Hino (‘221) and Kang disclose the silicon carbide semiconductor device according to claim 1 ( as discussed above ).
Neither Hino (`221 ) nor Kang appear to disclose a region sandwiched by the first separation region in the well region is a part of the well region.
However, Hino (`259) teaches a region sandwiched by the first separation region ( Fig. 1 #21 ) in the well region ( Fig. 1 #31 ) is a part of the well region ( [0102] The region in the well region 31 which is sandwiched between the separation region 21 and the source region 40 and positioned below the gate electrode 60 with the gate insulating film 50 interposed therebetween is referred to as a channel region ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hino (‘259) with Hino (‘221) and Kang to implement a region sandwiched by the first separation region in the well region is a part of the well region because this approach shields the gate oxide from high electric fields, reduces on-resistance, and manages surface charges.
Claim 10: Hino (`221), Kang, and Hino (`259) disclose the silicon carbide semiconductor device according to claim 9 ( as discussed above ).
Neither Hino (‘221) nor Kang appear to disclose the source electrode is formed on the part of the well region that is the region sandwiched by the first separation region in the well region.
However, Hino (‘259 ) teaches the source electrode ( Fig. 1 #80 ) is formed on the part of the well region ( Fig. 1 #31 ) that is the region sandwiched by the first separation region ( Fig. 1 #21 ) in the well region ( Fig. 1 #31 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hino (‘259) with Hino (‘221) and Kang to implement the source electrode is formed on the part of the well region that is the region sandwiched by the first separation region in the well region because this approach would improve reliability and reduce contact resistance.
Claim 12 is rejected under U.S.C. 103 as being unpatentable over Hino et al.; US 2023/0036221 A1; 02/2020 in view of Kang et al.; US 2021/0098483 A1; 06/2020 as it relates to claim 1 and further in view of Kawahara et al.; US 2023/0139229 A1; 05/2020
Claim 12: Hino and Kang disclose the silicon carbide semiconductor device according to claim 1 ( as discussed above).
Neither Hino nor Kang appear to disclose a power converter , comprising: a main conversion circuit including the silicon carbide semiconductor device according to claim 1, the main conversion circuit converting an input power to output a resulting power; a driving circuit performing an OFF operation so that a voltage of the gate electrode is equal to a voltage of the source electrode, and outputting, to the silicon carbide semiconductor device, a drive signal for driving the silicon carbide semiconductor device, the gate electrode and the source electrode being included in the silicon carbide semiconductor device; and a control circuit outputting, to the driving circuit, a control signal for controlling the driving circuit.
However, Kawahara teaches a power converter ( Fig. 20 power converter 800 ), comprising: a main conversion circuit ( Fig. 20 main conversion circuit 801 ) including the silicon carbide semiconductor device ( [0082] The semiconductor substrate 1, the drift layer 2, the well region 3, the source region 4, the sense well region 13, the sense source region 14, and the dummy sense well region 23 are formed of silicon carbide (SiC) ) according to claim 1 ( as discussed above ), the main conversion circuit ( Fig. 20 #801 ) converting an input power to output a resulting power ( [0168] As shown in FIG. 20, the power converter 800 includes a main conversion circuit 801 for converting an inputted DC power into AC power and outputting the AC power ); a driving circuit ( Fig. 20 driving circuit 802 ) performing an OFF operation so that a voltage of the gate electrode ( [0172] The driving circuit 802 generates driving signals for driving the switching devices of the main conversion circuit 801 and supplies the signals to the gate electrodes of the switching devices of the main conversion circuit 801 ) is equal to a voltage of the source electrode ( [0172] The driving signal to keep a switching device in an OFF state is a signal having a voltage lower than the threshold voltage of the switching device (OFF signal)), and outputting, to the silicon carbide semiconductor device ( Fig. 20 #801 ), a drive signal for driving the silicon carbide semiconductor device ( [0173] The driving circuit 802 outputs the ON signal or the OFF signal to the gate electrode of each switching device as a driving signal in accordance with the control signal ), the gate electrode and the source electrode being included in the silicon carbide semiconductor device ( as discussed above ); and a control circuit ( Fig. 20 control circuit 803 ) outputting, to the driving circuit ( Fig. 20 #802 ), a control signal for controlling the driving circuit ( [0173] The driving circuit 802 outputs the ON signal or the OFF signal to the gate electrode of each switching device as a driving signal in accordance with the control signal ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kawahara with Hino and Kang to implement a power converter , comprising: a main conversion circuit including the silicon carbide semiconductor device according to claim 1, the main conversion circuit converting an input power to output a resulting power; a driving circuit performing an OFF operation so that a voltage of the gate electrode is equal to a voltage of the source electrode, and outputting, to the silicon carbide semiconductor device, a drive signal for driving the silicon carbide semiconductor device, the gate electrode and the source electrode being included in the silicon carbide semiconductor device; and a control circuit outputting, to the driving circuit, a control signal for controlling the driving circuit because this approach is used to achieve high-efficiency and stable power control.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817