DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4 and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawazoe (JP 2019160847).
Regarding claim 1, Kawazoe discloses an imaging element package, comprising:
a semiconductor substrate provided with a photodiode (20, fig. 4);
a support portion (4, fig. 1) provided along an outer periphery of the semiconductor substrate to support a cover glass (3, fig. 1) that protects a light-receiving surface of the semiconductor substrate (fig. 1 and paragraphs 0020-0036, 0046-0099); and
an antireflection layer provided between the support portion and the
semiconductor substrate at least in an area where the support portion is provided (33, fig. 4, note: 33 is deposited across substrate 20 of CMOS imager 2, fig. 4 is blow up of 2).
Regarding claim 2, Kawazoe further discloses wherein the antireflection layer is provided entirely on the light-receiving surface of the semiconductor substrate, and
the support portion is stacked on the antireflection layer (33, fig. 4, note: 33 is deposited across substrate 20 of CMOS imager 2, fig. 4 is blow up of 2, fig. 1).
Regarding claim 4, Kawazoe further discloses wherein a part of the support portion (4, fig. 1) and a part of an organic layer (34, fig. 4) provided to cover the
antireflection layer overlap each other when viewed in a plan view (figs. 1,4).
Regarding claim 11, Kawazoe further discloses wherein a light-shielding resin layer is provided on an uppermost surface of a peripheral area provided in a peripheral part that is outside of an effective pixel area where pixels effectively used for capturing images are provided (39, fig. 4 and paragraphs 0020-0036, 0046-0099).
Regarding claim 12, Kawazoe further discloses wherein the light-shielding resin layer is provided from a vicinity of the boundary between the effective pixel area and the peripheral area to an area that overlaps the support portion (39, figs. 4, 1 and paragraphs 0020-0036, 0046-0099).
Regarding claim 13, Kawazoe further discloses wherein the light-shielding resin layer is provided from a vicinity of the boundary between the effective pixel area and the peripheral area to an area before the support portion (39, figs. 4-5 and paragraphs 0020-0036, 0046-0099).
Regarding claim 14, Kawazoe further discloses wherein
the light-shielding resin layer is patterned by providing slits (39, figs. 4-5 and paragraphs 0020-0036, 0046-0099).
Regarding claim 15, Kawazoe further discloses wherein a light-shielding layer provided under the light-shielding resin layer is patterned by providing slits according to the pattern of the light-shielding resin layer (39, figs. 4-5 and paragraphs 0020-0036, 0046-0099).
Regarding claim 16, Kawazoe further discloses an antireflection layer provided entirely on the light-receiving surface of the semiconductor substrate (33, fig. 4 and paragraphs 0020-0036, 0046-0099);
a light-shielding layer stacked on the antireflection layer in the peripheral area (39, figs. 4-5 and paragraphs 0020-0036, 0046-0099);
a resin layer stacked on the light-shielding layer to absorb light (34, fig. 4 and paragraphs 0020-0036, 0046-0099); and
a lens material stacked on the light-shielding layer and the resin layer (36, fig. 4 and paragraphs 0020-0036, 0046-0099).
Regarding claim 17, Kawazoe further discloses wherein the light-shielding layer is provided in a range substantially the same as an edge of the lens material (39, figs. 4-5 and paragraphs 0020-0036, 0046-0099), and
the light-shielding resin layer is stacked on the lens material and the antireflection
layer (39, figs. 4-5 and paragraphs 0020-0036, 0046-0099).
Regarding claim 18, Kawazoe further discloses wherein the light-shielding layer is provided as far as to an edge of the semiconductor substrate, and
the light-shielding resin layer is separated into a part to be stacked on the lens
material and a part to be stacked on the light-shielding layer by providing a slit in a vicinity of an edge of the lens material (39, figs. 4-5 and paragraphs 0020-0036, 0046-0099).
Regarding claim 19, Kawazoe further discloses wherein the light-shielding layer is provided with a slit in a location corresponding to the slit provided in the light-shielding resin layer (39, figs. 4-5 and paragraphs 0020-0036, 0046-0099).
Regarding claim 20, Kawazoe discloses an electronic device comprising an imaging element package, comprising:
a semiconductor substrate provided with a photodiode (20, fig. 4);
a support portion (4, fig. 1) provided along an outer periphery of the semiconductor substrate to support a cover glass (3, fig. 1) that protects a light-receiving surface of the semiconductor substrate (fig. 1 and paragraphs 0020-0036, 0046-0099); and
an antireflection layer provided between the support portion and the
semiconductor substrate at least in an area where the support portion is provided (33, fig. 4, note: 33 is deposited across substrate 20 of CMOS imager 2, fig. 4 is blow up of 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kawazoe (JP 2019160847).
Kawazoe discloses the imaging element package according to claim 2, as mentioned above. Kawazoe further discloses a light-shielding layer provided between the peripheral circuit and the support portion so as to overlap the peripheral circuit when viewed in a plan view (39, figs. 4-5 and paragraphs 0020-0036, 0046-0099), and a sensor substrate having the semiconductor substrate (20, fig. 4) and a logic substrate (6, fig. 1) provided with a logic circuit are layered on each other to constitute a layered structure (2, 6, fig. 1), the peripheral circuit is provided on the side of the logic circuit (fig. 1), and a light-shielding layer arranged between the peripheral circuit and the support
portion is provided at least one of a wiring layer for the sensor substrate and a wiring
layer for the logic substrate so that the light-shielding layer overlaps the peripheral circuit when viewed in a plan view (13, fig. 1).
Kawazoe does not explicitly disclose wherein a peripheral circuit including a capacitor is provided in a peripheral area. However, the use of capacitors in imaging devices was well established at the time of filing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Allowable Subject Matter
Claims 3 and 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, there is no teaching or suggestion in the art of record disclosing the imaging element package of claim 2 further comprising the light-shielding layer configured in accordance with the limitations of claim 3.
Claims 7-10 depend on claim 3.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2018/0204870 discloses a relevant solid state image sensor device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 2/4/26