DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claims Status
Claims 1-17 are currently pending and being examined. Claims 5-6 and 13-14 have been amended. No claims have been canceled, and no new claims have been added.
Claim Rejections - 35 USC § 112
The rejection of Claims 5-6 and 13-14 are rejected under 35 U.S.C. 112(b), second paragraph is withdrawn. Claims 5-6 and 13-14 have been amended to overcome their rejections.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nagasawa et al (US 2020/0006046 A1-IDS prior art of record, hereafter Nagasawa) in view of Lei et al (US 2005/0042842 A1-of record, hereafter Lei).
Re claim 1, Nagasawa discloses in FIGS. 5A-5D (with references to FIGS. 3A-3C) a method of fabricating a semiconductor structure (laminated substrate), the method comprising:
a) providing a donor substrate (4a in FIG. 5A; [0109]) of monocrystalline silicon carbide ([0073] and [0109]) and a carrier substrate (4b; [0109]) of silicon carbide ([0073] and [0109]);
b) preparing a working layer (4a’; [0114]) to be transferred (to 4b; [0114]), comprising:
implanting light species (hydrogen ions; [0112] and [0114]) in the donor substrate (4a) on a front face (A PLANE) to form a damage profile (4ion; [0114]), the damage profile (4ion) having a depth of defects (100-2000 nm; [0114]) defining a buried brittle plane (dotted line at “4ion”),
the working layer (4a’) to be transferred (to 4b), the working layer (4a’) to be transferred (to 4b) having a thickness of between 50 nm and 1400 nm (200-400 nm; [0114]);
c) joining (bonding in FIG. 5C; [0116]) the donor substrate (4a), on a side (horizontal plane) of the front surface (A PLANE), and the carrier substrate (4b) by way of molecular-adhesion (as in 3ab in FIG. 3C; [0075]-[0078]; [0087] and [0109]) to form an assembly (40; [0118]) bonded along a bonding interface (4ab; [0124]); and
d) separating (FIG. 5D; [0118]) along the buried brittle plane (dotted line at “4ion”), leading to transferring the working layer (4a’) onto the carrier substrate (4b) to form the semiconductor structure (laminated substrate).
Nagasawa fails to disclose the damage profile having a main peak of depth defects defining the buried brittle plane (dotted line at “4ion”) and a secondary peak of defects defining a damaged surface layer,
removing the damaged surface layer by way of chemical etching and/or by way of chemical-mechanical polishing of the front face (A PLANE) of the donor substrate (4a) to form a new front surface of the donor substrate (4a), the buried brittle plane (dotted line at “4ion”) delimiting, with the new front surface of the donor substrate (4a), (and)
joining the donor substrate (4a), on a side of the new front surface.
However,
A. Nagasawa discloses the preparing the working layer (4a’) to be transferred (to 4b) comprising implanting light species hydrogen at doses of 1x10¹⁶/cm² and 9x10¹⁷/cm² ([0112]) and an energy of 65 keV ([0171]), where both parameters are described by the instant specification as producing a damage profile having a main peak of depth defects defining the buried brittle plane and a secondary peak of defects defining a damaged surface layer, in monocrystalline silicon carbide as in donor substrate (4a).
Therefore, since Nagasawa discloses a substantially identical process, comprising an identical material, a prima facie case of obviousness is established (MPEP § 2112.02) that the process of Nagasawa yields a damage profile having a main peak of depth defects defining the buried brittle plane and a secondary peak of defects defining a damaged surface layer as claimed.
And,
B. Lei discloses in FIG. 6 a semiconductor device method comprising removing a damaged surface layer ([0064]) by way of chemical etching and/or by way of chemical-mechanical polishing ([0064]) of the front face (plane of ion implantation; [0064]) of a donor substrate (GOI/Ge/SiO2 laminate; [0064]) to form a new front surface (repaired surface; [0064]) of the donor substrate (GOI/Ge/SiO2 laminate).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Nagasawa by using the chemical-mechanical polishing of Lei, in between the steps of FIGS. 5B-5C of Nagasawa, removing the damaged surface layer by way of the chemical-mechanical polishing of the front face (A PLANE) of the donor substrate (4a) to form a new front surface of the donor substrate (4a), the buried brittle plane (dotted line at “4ion”) delimiting, with the new front surface of the donor substrate (4a), to provide a smooth and/or flat surface for bonding (Lei; [0064]), and thus joining the donor substrate (4a), on a side of the new front surface.
Re claim 2, Nagasawa discloses the method of claim 1.
But, fails to disclose wherein the removing of the damaged surface layer results in
between 5 nm and 200 nm being stripped away.
However, Nagaswa discloses damaged profiles up to 2000 nm ([0114]) and preferred working layer (4a’) thicknesses of 200-400 nm ([0114]).
Thus, with Lei’s CMP disclosure, it would have been obvious that the removing of the damaged surface layer results in between 5 nm and 200 nm being stripped away, as part of the smooth and/or flat surface for bonding discussed for claim 1.
Re claim 3, Nagasawa discloses the method of claim 1, wherein the carrier substrate (4a) comprises monocrystalline ([0073] and [0109]) or polycrystalline material (SiC).
Re claim 4, Nagasawa discloses the method of claim 1, wherein the light species are hydrogen ions ([0114]), implanted with an energy of between 30 keV and 210 keV (65 keV; [0171]) and at a dose of between 1x10¹⁶/cm² and x 5x10¹⁷/cm² (1x10¹⁶/cm² and 9x10¹⁷/cm²; [0112]).
Re claim 9, Nagasawa discloses he method of claim 1, further comprising forming at least one high-voltage microelectronic component (power semiconductor device; [0001]) on the semiconductor structure (laminated substrate).
Re claim 10, Nagasawa discloses he method of claim 2, wherein the removing of the damaged surface layer results in between 30 nm and 50 nm being stripped away (see claim 2).
Re claim 11, Nagasawa discloses he method of claim 2, wherein the carrier substrate comprises monocrystalline or polycrystalline material (see claim 3).
Re claim 12, Nagasawa discloses he method of claim 11, wherein the light species are hydrogen ions, implanted with an energy of between 30 keV and 210 keV and at a dose of between x10¹⁶/cm² and 5x10¹⁷/cm² (see claim 4).
Claims 5, 7, 8, 13 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nagasawa and Lei as applied to claim 1 above, and further in view of IMAOKA et al (US 2020/0006493 A1-IDS prior art of record, hereafter Imaoka).
Re claim 5, Nagasawa discloses the method of claim 1.
But, fails to disclose the method further comprising heat treating the semiconductor structure (laminated substrate) at a temperature of between 1300°C and 1700°C after the separating along the buried brittle plane (dotted line at “4ion”) to form the semiconductor structure (laminated substrate).
However,
Imaoka discloses in FIGS. 1 and 7-8 a method comprising heat treating a semiconductor structure (11/13c/13 laminate; [0031]) at a temperature of between 1300°C and 1700°C (1100°C and 1700°C; [0032]) after a separating (delaminating; [0031]) along a buried brittle plane (15; [0031]) to form the semiconductor structure (11/13b/13 laminate; [0032]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Nagasawa by using the heat treatment of Imaoka of between 1300°C and 1700°C after the separating along the buried plane to form the semiconductor structure, to form a bonding interface with an electrical resistance favorable to operation of devices formed on the semiconductor structure ([0003]).
Re claim 13, Nagasawa and Imaoka disclose the method of claim 12, further comprising heat treating the semiconductor 13. structure at a temperature of between 1300°C and 1700°C after the separating along the buried brittle plane to form the semiconductor structure (see claim 5).
Re claim 7, Nagasawa discloses the method of claim 1.
But, fails to disclose, wherein: the joining of the donor substrate (4a) and the carrier substrate (4b) further comprises forming at least one additional layer on the front surface (A PLANE) of the donor substrate (4a) and/or on a front face of the carrier substrate (4b), prior to the joining by way of molecular adhesion; and
the bonded assembly (40), obtained after the joining by way of molecular adhesion, comprises the at least one additional layer between the donor substrate (4a) and the carrier substrate (4b), the at least one additional layer being adjacent to or including the bonding interface (4ab).
However, Imaoka discloses forming at least one additional layer (SiC 13b; [0024]-[0026]) on a front surface (13a; [0026]) of a donor substrate (13; [0026]) and/or on a front face of the carrier substrate (4b), prior to bonding with a carrier substrate (11; [0030]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Nagasawa by using the forming at least one additional layer on the front surface of the donor substrate of Imaoka, prior to the joining by way of molecular adhesion; and the bonded assembly (40), obtained after the joining by way of molecular adhesion, comprises the at least one additional layer between the donor substrate (4a) and the carrier substrate (4b), the at least one additional layer being adjacent to or including the bonding interface (4ab), to form a bonding interface with an electrical resistance favorable to operation of devices formed on the semiconductor structure ([0003]).
Re claim 15, Nagasawa and Imaoka disclose the method of claim 14, wherein: the joining of the donor substrate and the carrier substrate further comprises forming at least one additional layer on the front surface of the donor substrate and/or on a front face of the carrier substrate, prior to the joining by way of molecular adhesion; and the bonded assembly, obtained after the joining by way of molecular adhesion, comprises the at least one additional layer between the donor substrate and the carrier substrate, the at least one additional layer being adjacent to or including the bonding interface (see claim 7).
Re claim 8, Nagasawa and Imaoka disclose the method of claim 7, wherein the at least one additional layer (Imaoka: 13b) comprises at least one material chosen from among the group including silicon ([0026]), tungsten, carbon ([0026]) and or titanium, as would be part of the bonding interface discussed for claims 5 and 7.
Re claim 16, Nagasawa and Imaoka disclose the method of claim 15, wherein the at least one additional layer comprises at least one material chosen from among the group including silicon, tungsten, carbon or titanium (see claim 8).
Re claim 17, Nagasawa discloses the method of claim 16, further comprising forming at least one high-voltage microelectronic component on the semiconductor structure (see claim 9).
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Nagasawa and Lei and Imaoka as applied to claims 5 and 13 above, and further in view of SCHULZE et al (US 2020/0068709 A1-of record, hereafter Schulze).
Re claim 6, Nagasawa and Lei and Imaoka disclose the method of claim 5.
But, fail to disclose the method further comprising applying a chemical-mechanical smoothing treatment to a free surface of the working layer (4a’) after the separating along the buried brittle plane (dotted line at “4ion”) to form the semiconductor structure (laminated substrate).
However,
Schulze discloses in FIG. 7C a method comprising applying a chemical-mechanical smoothing treatment (CMP polishing; [0096]) to a free surface (bottom plane) of a working layer (118; [0096]) after the separating (splitting; [0092]) along a buried brittle plane (123; [0092]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Nagasawa and Lei and Imaoka by adding the applying a chemical-mechanical smoothing treatment to a free surface of the working layer after the separating along the buried brittle plane of Schulze, to provide a substrate for mechanically stable for a range of high-voltage devices (Schulze; [0103]).
Re claim 14, Nagasawa and Lei and Imaoka and Schulze disclose the further comprising applying a chemical-mechanical smoothing treatment to a free surface of the working layer after the separating along the buried brittle plane to form the semiconductor structure (see claim 6).
Response to Arguments
Applicant's arguments filed 3/30/2026 have been fully considered but they are not persuasive for the following reason(s):
A. With respect to claim 1, the applicant without admitting to the examiner’s assertion that Nagasawa inherently discloses the limitations of “a secondary peak of defects defining a damaged surface layer” argues that the teachings of Lei are incompatible with the process of Nagasawa for “removing the damaged surface layer by way of chemical etching and/or by way of chemical-mechanical polishing of the front face of the donor substrate to form a new front surface of the donor substrate” since the damaged surface of Lei is on a dielectric layer instead of a monocrystalline silicon carbide donor substrate as claimed by the applicant.
The examiner, respectfully, disagrees with the applicant since Lei is being relied upon for its teaching of removing surface damage of a layer caused by ion implantation, independent of the material of the layer. Wherein, upon removal of the surface damage, a smoother surface of the layer is available for bonding with another object.
The examiner contends that since Nagasawa is concerned with bonding of a donor substrate and a carrier substrate after ion implantation and thinning of the ion damaged front face of the donor substrate to a desired thickness, it would have been obvious and plausible to use the teachings of Lei for the particular type of thinning (CMP or etching) specifically for removing the ion implanted damaged surface layer of Nagasawa.
Further, in response to applicant’s arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Thus, the examiner submits that applying the ion implanted damaged surface removal of Lei to the donor substrate of Nagasawa does not change the principle of operation of the primary reference or render the reference inoperable for its intended purpose. See MPEP § 2143.01. The test for obviousness is not whether the features of the secondary reference may be bodily incorporated into the structure of the primary reference. Rather, the test is what the combined teachings of those references would have suggested to those of ordinary skill in the art. In re Keller, 642 F.2d 413, 425, 208 USPQ 871, 881 (CCPA 1981).
B. With respect to dependent claims 2-17 and the respective prior art references (Imaoka and Schulze) used for their rejections, the applicant’s arguments, in summary, of the respective prior art references being incapable of overcoming the perceived deficiencies of Nagasawa in view of Lei for claim 1 are rendered moot by the above rebuttal. Further, neither Imaoka or Schulze were, and are not currently being used to satisfy limitations of claim 1. But rather, claims 2-17 as discussed above.
Lastly, it is concluded that the examiner has presented rational for the combination of Nagasawa in view of Lei to sustain and maintain the rejection of claim 1 and its dependent claims 2-17.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC W JONES/Primary Examiner, Art Unit 2892
Prosecution Insights