DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Interpretation (Contingent Limitations)
In Applicant’s claims, Applicant recites contingent limitations. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B. See MPEP 2111.04.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 27 March 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 6-10, 12, 13, 16, 17, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Loh et al. (US 2013/0238856) in view of Abramson et al. (US 5,577,200), Lowe-Power (gem5 Tutorial 0.1 documentation), and Tune et al. (US 2014/0372696).
In regards to claim 1, Loh teaches a data processing method, comprising:
receiving a data processing request ([0011] describes memory access requests), wherein data requested by the data processing request comprises data that is suitable for being stored in at least two cache units ([0011] describing wherein the requested data when not stored in the cache is moved into the cache and when the data is stored in the cache, it is accessed therein), and main memory addresses of data in each of the cache units are consecutive ([0013], lines 1-8 describing consecutive main memory addresses); and
in a case where main memory address information of each of cache units that satisfy a mapping relationship comprises all the main memory addresses ([0052] describing the main memory address information; [0051] wherein they are mapped to the same row), simultaneously performing data processing on data corresponding to each of the main memory addresses ([0051] wherein the activation of the entire row is simultaneously performing data processing on all cache lines within that row), wherein each of the cache units that satisfy the mapping relationship is a cache unit corresponding to a main memory address in the data processing request ([0051] as described wherein the cache units correspond to consecutive main memory addresses),
wherein the data processing method further comprises:
in a case where the main memory address information of each of the cache units that satisfy the mapping relationship does not comprise all the main memory addresses ([0011] wherein the cache does not hold the data requested according to the sequential main memory addresses), respectively writing each of the main memory addresses that are missing into each of the cache units to be processed ([0011] wherein the data is accessed from the main memory and stored into the cache memory), wherein original main memory address information of each of the cache units to be processed is different from each of the main memory addresses corresponding to data of the data processing request ([0052] wherein the look up can distinguish data that needs to be retrieved from main memory vs. data already stored in the cache; thereby indicating that the information is changed),
wherein the data processing request comprises a data read request ([0049], lines 1-2), and in a case where the main memory address information of each of the cache units that satisfy the mapping relationship comprises all the main memory addresses ([0051] wherein the activation of the entire row is simultaneously performing data processing on all cache lines within that row), the step of simultaneously performing data processing on data corresponding to each of the main memory addresses, comprises:
in a case where the main memory address information of each of the cache units that satisfy the mapping relationship comprises all the main memory addresses, returning data corresponding to all the main memory addresses ([0052] wherein the cache line is already stored in the cache).
Loh fails to teach that the data processing request further comprises a data processing request type identification, and the data processing request type identification is used for identifying that data requested by the data processing request comprises data suitable for being stored in at least two cache units,
wherein the data processing request type identification comprises one or more bits, and a value of the one or more bits is used for indicating read/write type of data requested by the data processing request and a number of cache units storing the data requested by the data processing request,
wherein the data is not written to each of the cache units to be processed, so that when the data is obtained, the data is written into the cache units corresponding to the main memory addresses,
wherein a significant bit of each of the cache units indicates that a corresponding cache unit is valid, wherein returning data corresponding to all the main memory addresses occurs simultaneously.
Abramson teaches that the data processing request further comprises a data processing request type identification (“The opcode, which is dispatched with the load operation by the RS 35, identifies the load operation and the size of the load operation.”, Col. 8, lines 35-38; “As described earlier, the opcode type comprises a number of control bits indicating whether the load operation is data chunk split misaligned, cache line split misaligned, and the last of the aligned subset load operations, which are set by the LB 46.”, Col. 8, lines 40-44), and the data processing request type identification is used for identifying that data requested by the data processing request comprises data suitable for being stored in at least two cache units (“As described earlier, the opcode type comprises a number of control bits indicating whether the load operation is data chunk split misaligned, cache line split misaligned, and the last of the aligned subset load operations, which are set by the LB 46.”, Col. 4, lines 61-65; “A second control bit of the opcode type 19 when set indicates that the load or store operation is cache line split misaligned.”, Col. 5, lines 7-9),
wherein the data processing request type identification comprises one or more bits (“Each buffered load operation comprises its opcode, and linear address (LA[31:0]). Additionally, each buffered load operation also includes an opcode type, and a number of control bits including a valid bit (v) and an execution state (e) field.”, Col. 8, lines 30-35), and a value of the one or more bits is used for indicating read/write type of data requested by the data processing request (“The opcode, which is dispatched with the load operation by the RS 35, identifies the load operation and the size of the load operation.”, Col. 8, lines 35-38; “The opcode, which is dispatched with the store operation by the RS 35, identifies the store operation and the size of the store operation.”, Col. 9, lines 6-8) and a number of cache units storing the data requested by the data processing request (“As described earlier, the opcode type comprises a number of control bits indicating whether the load operation is data chunk split misaligned, cache line split misaligned, and the last of the aligned subset load operations, which are set by the LB 46.”, Col. 4, lines 61-65; “A second control bit of the opcode type 19 when set indicates that the load or store operation is cache line split misaligned.”, Col. 5, lines 7-9)
in order to support misaligned data for compatibility reasons (Col. 2, lines 28-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Loh with Abramson such that the data processing request further comprises a data processing request type identification, and the data processing request type identification is used for identifying that data requested by the data processing request comprises data suitable for being stored in at least two cache units,
wherein the data processing request type identification comprises one or more bits, and a value of the one or more bits is used for indicating read/write type of data requested by the data processing request and a number of cache units storing the data requested by the data processing request
in order to support misaligned data for compatibility reasons (id.).
Loh in view of Abramson fails to teach that the data is not written to each of the cache units to be processed, so that when the data is obtained, the data is written into the cache units corresponding to the main memory addresses,
wherein a significant bit of each of the cache units indicates that a corresponding cache unit is valid, wherein returning data corresponding to all the main memory addresses occurs simultaneously.
Lowe-Power teaches that the data is not written to each of the cache units to be processed (“In this case, if the initial state is I and the event is Load then transition to IS_D (was invalid, going to shared, waiting for data).”, page 1, paragraph 4; “Then, inside the transition code block, all of the actions that will execute are listed in order. For this transition first we allocate the cache block. Remember that in the allocateCacheBlock action the newly allocated entry is set to the entry that will be used in the rest of the actions.”, page 1, paragraph 5), so that when the data is obtained, the data is written into the cache units corresponding to the main memory addresses (“transition(IS_D, {DataDirNoAcks, DataOwner}, S) { writeDataToCache;”, page 2, code block 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Loh with Abramson and Lowe-Power such that the data is not written to each of the cache units to be processed, so that when the data is obtained, the data is written into the cache units corresponding to the main memory addresses in order to guarantee memory ordering.
Loh in view of Abramson and Lowe-Power fails to explicitly teach that a significant bit of each of the cache units indicates that a corresponding cache unit is valid, wherein returning data corresponding to all the main memory addresses occurs simultaneously. Tune teaches that a significant bit of each of the cache units indicates that a corresponding cache unit is valid ([0054]), wherein returning data corresponding to all the main memory addresses occurs simultaneously ([0058]) because it provides for greater bandwidth ([0058]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Loh with Abramson, Lowe-Power, and Tune such that a significant bit of each of the cache units indicates that a corresponding cache unit is valid, wherein returning data corresponding to all the main memory addresses occurs simultaneously because it provides for greater bandwidth (id.).
In regards to claim 3, Loh further teaches that the cache units to be processed comprise at least one of a cache unit to be replaced and a free cache unit ([0053] describing wherein the available memory spaces are construed to be free).
In regards to claim 4, Tune further teaches that the cache units to be replaced are determined by a Least Recently Used principle (LRU) ([0060]).
In regards to claim 6, Loh further teaches that the data processing request comprises a data read request ([0011] describes read operations), and in a case where the main memory address information of each of the cache units that satisfy the mapping relationship does not comprise all the main memory addresses ([0052] wherein the look up can determine data that needs to be retrieved from main memory), after the step of respectively writing each of the main memory addresses that are missing into each of the cache units to be processed, further comprises:
generating and sending missing data read requests for reading data corresponding to each of the main memory addresses that are missing ([0052] wherein the look up can determine data that needs to be retrieved from main memory).
In regards to claim 7, Loh further teaches that the step of generating the missing data read requests for reading data corresponding to each of the main memory addresses that are missing comprises:
generating each of the missing data read requests for respectively reading data corresponding to each of the main memory addresses that are missing, wherein a number of the missing data read requests is same as a number of each of the main memory addresses that are missing ([0011] wherein the data is accessed from the main memory and stored into the cache memory); and
the data processing method further comprises:
in a case of receiving all data corresponding to each of the main memory addresses that are missing, returning data corresponding to all the main memory addresses ([0052] wherein the look up can determine data that needs to be retrieved from main memory).
Tune further teaches that returning data corresponding to all the main memory addresses occurs simultaneously ([0058]).
In regards to claim 8, Loh further teaches that the step of generating the missing data read requests for reading data corresponding to each of the main memory addresses that are missing comprise:
acquiring main memory addresses of addresses being consecutive in each of the main memory addresses that are missing, and obtaining each of consecutive main memory addresses ([0011] wherein the data is accessed from the main memory and stored into the cache memory; [0013], lines 1-8 describing consecutive main memory addresses);
generating consecutive missing data read requests for reading data corresponding to each of the consecutive main memory addresses that are missing according to each of the consecutive main memory addresses ([0052] wherein the look up can determine data that needs to be retrieved from main memory); and
the data processing method further comprises:
in a case of receiving all data corresponding to each of the main memory addresses that are missing, returning data corresponding to all the main memory addresses ([0052] wherein the look up can determine data that needs to be retrieved from main memory).
Tune further teaches that returning data corresponding to all the main memory addresses occurs simultaneously ([0058]).
In regards to claim 9, Loh further teaches that the data processing request comprises a data write request ([0011]), and in a case where the main memory address information of each of the cache units that satisfy the mapping relationship comprises all the main memory addresses, the step of simultaneously performing data processing on data corresponding to each of the main memory addresses, comprises:
in a case where the main memory address information of each of the cache units that satisfy the mapping relationship comprises all the main memory addresses, receiving data corresponding to each of the main memory addresses, and writing each of the data into a corresponding cache unit ([0011]; [0052]).
Tune teaches that receiving data corresponding to each of the main memory addresses occurs simultaneously ([0058]).
In regards to claim 10, Loh further teaches that the data processing request comprises a data write request ([0011]), and in a case where the main memory address information of each of the cache units that satisfy the mapping relationship does not comprise all the main memory addresses, after the step of respectively writing each of the main memory addresses that are missing into each of the cache units to be processed, further comprises:
receiving data corresponding to each of the main memory addresses, and writing each of the data into a corresponding cache unit ([0011]; [0052]).
Tune further teaches that receiving data corresponding to each of the main memory addresses occurs simultaneously ([0058]).
In regards to claim 12, Loh further teaches that an implementation method of the data processing request type identification comprises increasing a number of main memory address identification bits or increasing a type of request type identification ([0054] wherein then consecutive main memory addresses are stored in the cache, a second pointer is included as opposed on only pointer being included for nonsequential cache lines. This additional pointer is construed to be an increase in a type of request type identification).
In regards to claim 13, Loh teaches a data processing apparatus, comprising a hardware processor configured to:
receive a data processing request ([0011] describes memory access requests), wherein data requested by the data processing request comprises data that is suitable for being stored in at least two cache units ([0011] describing wherein the requested data when not stored in the cache is moved into the cache and when the data is stored in the cache, it is accessed therein), and main memory addresses of data in each of the cache units are consecutive ([0013], lines 1-8 describing consecutive main memory addresses); and
in a case where main memory address information of each of cache units that satisfy a mapping relationship comprises all the main memory addresses ([0052] describing the main memory address information; [0051] wherein they are mapped to the same row), simultaneously perform data processing on data corresponding to each of the main memory addresses ([0051] wherein the activation of the entire row is simultaneously performing data processing on all cache lines within that row), wherein each of the cache units that satisfy the mapping relationship is a cache unit corresponding to a main memory address in the data processing request ([0051] as described wherein the cache units correspond to consecutive main memory addresses),
wherein the hardware processor is further configured to in a case where the main memory address information of each of the cache units that satisfy the mapping relationship does not comprise all the main memory addresses ([0011] wherein the cache does not hold the data requested according to the sequential main memory addresses), respectively write each of the main memory addresses that are missing into each of cache units to be processed ([0011] wherein the data is accessed from the main memory and stored into the cache memory), wherein original main memory address information of each of the cache units to be processed is different from a main memory address of data requested by the data processing request ([0052] wherein the look up can distinguish data that needs to be retrieved from main memory vs. data already stored in the cache; thereby indicating that the information is changed),
wherein the hardware processor is further configured to:
receive a data read request ([0049], lines 1-2), data requested by the data read request comprising data that is suitable for being stored in at least two cache units, and main memory addresses of data in each of the cache units being consecutive ([0051] wherein the activation of the entire row is simultaneously performing data processing on all cache lines within that row); and
in a case where the main memory address information of each of the cache units that satisfy the mapping relationship comprises all the main memory addresses, returning data corresponding to all the main memory addresses ([0052] wherein the cache line is already stored in the cache).
Loh fails to teach that the data processing request further comprises a data processing request type identification, and the data processing request type identification is used for identifying that data requested by the data processing request comprises data suitable for being stored in at least two cache units,
wherein the data processing request type identification comprises one or more bits, and a value of the one or more bits is used for indicating read/write type of data requested by the data processing request and a number of cache units storing the data requested by the data processing request,
wherein the data is not written to each of the cache units to be processed, so that when the data is obtained, the data is written into the cache units corresponding to the main memory addresses, and
in a cache where a significant bit of each of the cache units indicates that a corresponding cache unit is valid, simultaneously return data corresponding to all the main memory addresses.
Abramson teaches that the data processing request further comprises a data processing request type identification (“The opcode, which is dispatched with the load operation by the RS 35, identifies the load operation and the size of the load operation.”, Col. 8, lines 35-38; “As described earlier, the opcode type comprises a number of control bits indicating whether the load operation is data chunk split misaligned, cache line split misaligned, and the last of the aligned subset load operations, which are set by the LB 46.”, Col. 8, lines 40-44), and the data processing request type identification is used for identifying that data requested by the data processing request comprises data suitable for being stored in at least two cache units (“As described earlier, the opcode type comprises a number of control bits indicating whether the load operation is data chunk split misaligned, cache line split misaligned, and the last of the aligned subset load operations, which are set by the LB 46.”, Col. 4, lines 61-65; “A second control bit of the opcode type 19 when set indicates that the load or store operation is cache line split misaligned.”, Col. 5, lines 7-9),
wherein the data processing request type identification comprises one or more bits (“Each buffered load operation comprises its opcode, and linear address (LA[31:0]). Additionally, each buffered load operation also includes an opcode type, and a number of control bits including a valid bit (v) and an execution state (e) field.”, Col. 8, lines 30-35), and a value of the one or more bits is used for indicating read/write type of data requested by the data processing request (“The opcode, which is dispatched with the load operation by the RS 35, identifies the load operation and the size of the load operation.”, Col. 8, lines 35-38; “The opcode, which is dispatched with the store operation by the RS 35, identifies the store operation and the size of the store operation.”, Col. 9, lines 6-8) and a number of cache units storing the data requested by the data processing request (“As described earlier, the opcode type comprises a number of control bits indicating whether the load operation is data chunk split misaligned, cache line split misaligned, and the last of the aligned subset load operations, which are set by the LB 46.”, Col. 4, lines 61-65; “A second control bit of the opcode type 19 when set indicates that the load or store operation is cache line split misaligned.”, Col. 5, lines 7-9)
in order to support misaligned data for compatibility reasons (Col. 2, lines 28-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Loh with Abramson such that the data processing request further comprises a data processing request type identification, and the data processing request type identification is used for identifying that data requested by the data processing request comprises data suitable for being stored in at least two cache units,
wherein the data processing request type identification comprises one or more bits, and a value of the one or more bits is used for indicating read/write type of data requested by the data processing request and a number of cache units storing the data requested by the data processing request
in order to support misaligned data for compatibility reasons (id.).
Loh in view of Abramson fails to teach that the data is not written to each of the cache units to be processed, so that when the data is obtained, the data is written into the cache units corresponding to the main memory addresses, and
in a cache where a significant bit of each of the cache units indicates that a corresponding cache unit is valid, simultaneously return data corresponding to all the main memory addresses.
Lowe-Power teaches that the data is not written to each of the cache units to be processed (“In this case, if the initial state is I and the event is Load then transition to IS_D (was invalid, going to shared, waiting for data).”, page 1, paragraph 4; “Then, inside the transition code block, all of the actions that will execute are listed in order. For this transition first we allocate the cache block. Remember that in the allocateCacheBlock action the newly allocated entry is set to the entry that will be used in the rest of the actions.”, page 1, paragraph 5), so that when the data is obtained, the data is written into the cache units corresponding to the main memory addresses (“transition(IS_D, {DataDirNoAcks, DataOwner}, S) { writeDataToCache;”, page 2, code block 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Loh with Abramson and Lowe-Power such that the data is not written to each of the cache units to be processed, so that when the data is obtained, the data is written into the cache units corresponding to the main memory addresses in order to guarantee memory ordering.
Loh in view of Abramson and Lowe-Power fails to teach that in a cache where a significant bit of each of the cache units indicates that a corresponding cache unit is valid, simultaneously return data corresponding to all the main memory addresses. Tune teaches that that in a cache where a significant bit of each of the cache units indicates that a corresponding cache unit is valid ([0054]), simultaneously return data corresponding to all the main memory addresses ([0058]) because it provides for greater bandwidth ([0058]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Loh with Abramson, Lowe-Power, and Tune such that in a cache where a significant bit of each of the cache units indicates that a corresponding cache unit is valid, simultaneously return data corresponding to all the main memory addresses because it provides for greater bandwidth (id.).
In regards to claim 16, Loh further teaches the hardware processor is further configured to:
receive a data read request ([0011] describes read operations), data requested by the data read request comprising data that is suitable for being stored in at least two cache units, and main memory addresses of data in each of the cache units being consecutive ([0051] as described wherein the cache units correspond to consecutive main memory addresses); and
in a case where the main memory address information of each of the cache units that satisfy the mapping relationship does not comprise all the main memory addresses, respectively write each of the main memory addresses that are missing into each of cache units to be processed, and generate and send missing data read requests for reading data corresponding to each of the main memory addresses that are missing ([0052] wherein the look up can determine data that needs to be retrieved from main memory).
In regards to claim 17, Loh further teaches that the generating and sending of the missing data read requests for reading data corresponding to each of the main memory addresses that are missing, comprises:
the hardware processor is further configured to generate each of the missing data read requests for respectively reading data corresponding to each of the main memory addresses that are missing, wherein a number of the missing data read requests is the same as a number of each of the main memory addresses that are missing ([0011] wherein the data is accessed from the main memory and stored into the cache memory); and
in a case of receiving all data corresponding to each of the main memory addresses that are missing, the hardware processor is further configured to return data corresponding to all the main memory addresses ([0052] wherein the look up can determine data that needs to be retrieved from main memory).
Tune further teaches simultaneously return data corresponding to all the main memory addresses ([0058]).
In regards to claim 24, Loh further teaches a processor ([0011] control unit 112), wherein the processor executes computer-executable instructions to implement the data processing method of claim 1.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lyon (US 2003/0154345) in view of Loh et al. (US 2013/0238856), Abramson et al. (US 5,577,200), Lowe-Power (gem5 Tutorial 0.1 documentation), and Tune et al. (US 2014/0372696).
In regards to claim 23, Lyon teaches a cache, comprising a level one cache (fig. 2, level 1 cache) and a level two cache (fig. 2, level 2 cache data), wherein at least two cache units of the level one cache and at least two cache units of the level two cache are mapped simultaneously ([0008] wherein the cache tags map main memory addresses to data stored in the cache). Lyon fails to explicitly teaches that the level one cache and the level two cache both comprise the data processing apparatus of claim 13. Loh in view of Abramson, Lowe-Power, and Tune teaches that the level one cache and the level two cache both comprise the data processing apparatus of claim 13 (See the rejection of claim 13 above) because it helps to reduce access latencies involved with a row-based memory (Loh, [0022]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the cache of Lyon with the processing apparatus of Loh in view of Abramson, Lowe-Power, and Tune because it helps to reduce access latencies involved with a row-based memory (id.).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/Nathan Sadler/Primary Examiner, Art Unit 2139 6 July 2026
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