Prosecution Insights
Prosecution Insights
Technology areas: Computing & Software • Semiconductors, Circuits & Optics • Transportation, E-Commerce & Mechanical Systems
6 pending office actions • 4 art units • 6 examiners • 0 of 6 (0%) have an AI response strategy ready • 5 patents granted in the last 365 days
Hygon Information Technology Co. Ltd. currently has 6 pending office actions in the Semiconductors, Circuits & Optics technology area. These actions are distributed among 6 distinct examiners and 4 distinct art units. This distribution indicates that each pending matter is being reviewed by a different individual, which may lead to a variety of prosecution outcomes. The use of 4 distinct art units suggests that the company's semiconductor and optics filings cover a relatively broad range of technical classifications.
Lewis Alexander Bullock Jr is the busiest examiner for the company with 1 pending office action. Since there are 6 pending office actions and 6 distinct examiners, the workload is perfectly spread out among the staff. The busiest examiner pending count of 1 reflects this lack of concentration. With 6 distinct examiners and 4 distinct art units, the company must manage multiple relationships and technical standards simultaneously. Practitioners should be prepared for diverse examiner perspectives across the 4 distinct art units involved in these 6 pending office actions, as no single examiner dominates the current docket.
Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 + other | 1 (17%) |
| §103 only | 2 (33%) |
| §112 only | 1 (17%) |
| Multi-statute (no §101) | 2 (33%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| BULLOCK JR, LEWIS ALEXANDER | 1 | 31.6% | +44.8% |
| VICARY, KEITH E | 1 | 57.7% | +40.3% |
| EL-HAGE HASSAN, ABDALLAH A | 1 | 42.9% | +40.4% |
| HOSSAIN, MOAZZAM | 1 | 88.1% | +11.1% |
| YAP, DOUGLAS ANTHONY | 1 | 80.6% | +12.1% |
| ASSOUMAN, HERVE-LOUIS Y | 1 | 91.4% | +4.1% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18575114 | FAN-OUT PACKAGING METHOD, FAN-OUT PACKAGE STRUCTURE AND MANUFACTURING METHOD HEREOF | ASSOUMAN, HERVE-LOUIS Y | 54d |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18713317 | GENERATION METHOD FOR CHIP INTERNAL VOLTAGE PREDICTION MODEL, PREDICTION METHOD AND RELATED APPARATUS | EL-HAGE HASSAN, ABDALLAH A | — |
| 18702836 | CHIP TESTING STRUCTURE AND CHIP TESTING METHOD | HOSSAIN, MOAZZAM | — |
| 18294770 | CHIP ASSEMBLY, CHIP INTERPOSER AND FABRICATING METHOD FOR CHIP ASSEMBLY | YAP, DOUGLAS ANTHONY | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 5 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18718608 | DATA PROCESSING METHOD AND APPARATUS, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM | BULLOCK JR, LEWIS ALEXANDER | — |
| 18714604 | DECODING METHOD, PROCESSOR, CHIP, AND ELECTRONIC DEVICE | VICARY, KEITH E | — |
| 18713317 | GENERATION METHOD FOR CHIP INTERNAL VOLTAGE PREDICTION MODEL, PREDICTION METHOD AND RELATED APPARATUS | EL-HAGE HASSAN, ABDALLAH A | — |
| 18702836 | CHIP TESTING STRUCTURE AND CHIP TESTING METHOD | HOSSAIN, MOAZZAM | — |
| 18294770 | CHIP ASSEMBLY, CHIP INTERPOSER AND FABRICATING METHOD FOR CHIP ASSEMBLY | YAP, DOUGLAS ANTHONY | — |
| Art Unit | Apps |
|---|---|
| 2183 | 1 |
| 3623 | 1 |
| 2899 | 1 |
| 2812 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18718608 | DATA PROCESSING METHOD AND APPARATUS, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM | BULLOCK JR, LEWIS ALEXANDER | — | §103 | Non-Final OA | — | Pending | Jun 11, 2024 |
| 18714604 | DECODING METHOD, PROCESSOR, CHIP, AND ELECTRONIC DEVICE | VICARY, KEITH E | 2183 | §112 | Final Rejection | — | Pending | May 30, 2024 |
| 18713317 | GENERATION METHOD FOR CHIP INTERNAL VOLTAGE PREDICTION MODEL, PREDICTION METHOD AND RELATED APPARATUS | EL-HAGE HASSAN, ABDALLAH A | 3623 | §101§103 | Non-Final OA | — | Pending | May 24, 2024 |
| 18702836 | CHIP TESTING STRUCTURE AND CHIP TESTING METHOD | HOSSAIN, MOAZZAM | — | §102§103 | Non-Final OA | — | Pending | Apr 19, 2024 |
| 18294770 | CHIP ASSEMBLY, CHIP INTERPOSER AND FABRICATING METHOD FOR CHIP ASSEMBLY | YAP, DOUGLAS ANTHONY | 2899 | §102§103 | Non-Final OA | — | Pending | Feb 02, 2024 |
| 18575114 | FAN-OUT PACKAGING METHOD, FAN-OUT PACKAGE STRUCTURE AND MANUFACTURING METHOD HEREOF | ASSOUMAN, HERVE-LOUIS Y | 2812 | §103 | Final Rejection | 54d | Pending | Dec 28, 2023 |
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